tests: Update regressions for the new kernels and various preceeding fixes.

37 files changed, 7971 insertions, 6376 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index f7c4e30f8..8f2902a1b 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -26,8 +26,8 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -339,7 +339,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -362,7 +362,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -527,6 +527,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
@@ -577,7 +578,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
index 20fe2d682..518507880 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
@@ -1,3 +1,4 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 2d1ba2c03..537e9e8af 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,13 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 17:25:12
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:20:02
 gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 688618000
-Exiting @ tick 1960909874500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 690168000
+Exiting @ tick 1961826628500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index f259fe3aa..dd52d45d1 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.961827                       # Nu
 sim_ticks                                1961826628500                       # Number of ticks simulated
 final_tick                               1961826628500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 855480                       # Simulator instruction rate (inst/s)
-host_op_rate                                   855480                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27561784483                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318220                       # Number of bytes of host memory used
-host_seconds                                    71.18                       # Real time elapsed on the host
+host_inst_rate                                1248737                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1248737                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            40231703865                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312404                       # Number of bytes of host memory used
+host_seconds                                    48.76                       # Real time elapsed on the host
 sim_insts                                    60892387                       # Number of instructions simulated
 sim_ops                                      60892387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -728,8 +728,6 @@ system.iocache.fast_writes                      41552                       # nu
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::tsunami.ide          174                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          174                       # number of overall MSHR misses
@@ -744,16 +742,14 @@ system.iocache.overall_mshr_miss_latency::tsunami.ide     12199383
 system.iocache.overall_mshr_miss_latency::total     12199383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60199.384049                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60199.384049                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 70111.396552                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average overall mshr miss latency
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index e05c30aba..39571b45c 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -26,8 +26,8 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -260,7 +260,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -283,7 +283,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -413,6 +413,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
@@ -463,7 +464,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
index 20fe2d682..518507880 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
@@ -1,3 +1,4 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index fa5fb8ad8..612d6e177 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 17:24:48
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:20:00
 gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1920428041000 because m5_exit instruction encountered
+Exiting @ tick 1919439025000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index a2e01807e..04dd39221 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.919439                       # Nu
 sim_ticks                                1919439025000                       # Number of ticks simulated
 final_tick                               1919439025000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 960719                       # Simulator instruction rate (inst/s)
-host_op_rate                                   960718                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            32869301826                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317196                       # Number of bytes of host memory used
-host_seconds                                    58.40                       # Real time elapsed on the host
+host_inst_rate                                1406989                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1406988                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            48137648137                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309300                       # Number of bytes of host memory used
+host_seconds                                    39.87                       # Real time elapsed on the host
 sim_insts                                    56102180                       # Number of instructions simulated
 sim_ops                                      56102180                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -412,8 +412,6 @@ system.iocache.fast_writes                      41552                       # nu
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
@@ -428,16 +426,14 @@ system.iocache.overall_mshr_miss_latency::tsunami.ide     15526633
 system.iocache.overall_mshr_miss_latency::total     15526633                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide     0.999904                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.999904                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60458.661533                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 89749.323699                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699                       # average overall mshr miss latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 2198282f2..e4e3f0a2b 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
 have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
 mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.nvmem system.physmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -53,14 +53,14 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
 
 [system.bridge]
 type=Bridge
 clk_domain=system.clk_domain
 delay=50000
 eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -278,6 +278,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu0.istage2_mmu]
@@ -570,6 +571,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu1.istage2_mmu]
@@ -707,15 +709,16 @@ type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
-use_default_range=false
+use_default_range=true
 width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
 type=BaseCache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
 eventq_index=0
@@ -734,8 +737,8 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
 type=LRU
@@ -770,7 +773,7 @@ tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
 
 [system.l2c.tags]
 type=LRU
@@ -793,8 +796,8 @@ system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -824,47 +827,38 @@ in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=0:134217727
-port=system.membus.master[6]
+range=2147483648:2415919103
+port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
 pci_cfg_gen_offsets=false
 pci_io_base=0
 system=system
 
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
 pio_latency=100000
 system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
 
 [system.realview.cf_ctrl]
 type=IdeController
-BAR0=402653184
+BAR0=471465984
 BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
 BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
 BAR2=1
 BAR2LegacyIO=false
 BAR2Size=8
@@ -934,18 +928,18 @@ VendorID=32902
 clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
-disks=system.cf0
+disks=
 eventq_index=0
-io_shift=1
+io_shift=2
 pci_bus=2
-pci_dev=7
+pci_dev=0
 pci_func=0
 pio_latency=30000
 platform=system.realview
 system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.clcd]
 type=Pl111
@@ -954,8 +948,8 @@ clk_domain=system.clk_domain
 enable_capture=true
 eventq_index=0
 gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
 pio_latency=10000
 pixel_clock=41667
 system=system
@@ -963,51 +957,129 @@ vnc=system.vncserver
 dma=system.iobus.slave[1]
 pio=system.iobus.master[4]
 
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
 clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
 eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
 pio_latency=100000
 system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
 
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
 clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
 eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
 system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
 pio=system.iobus.master[25]
 
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
 eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
 system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
 clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
 cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
@@ -1017,38 +1089,111 @@ platform=system.realview
 system=system
 pio=system.membus.master[2]
 
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
 clk_domain=system.clk_domain
+enable_capture=true
 eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
 system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
 
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
 clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
 eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
 system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
 
 [system.realview.kmi0]
 type=Pl050
@@ -1057,13 +1202,13 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=52
+int_num=44
 is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1072,20 +1217,20 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=53
+int_num=45
 is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.l2x0_fake]
 type=IsaFake
 clk_domain=system.clk_domain
 eventq_index=0
 fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
 pio_latency=100000
 pio_size=4095
 ret_bad_addr=false
@@ -1096,7 +1241,25 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
@@ -1105,10 +1268,10 @@ eventq_index=0
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -1116,10 +1279,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
 pio_latency=100000
 system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
 
 [system.realview.nvmem]
 type=SimpleMemory
@@ -1131,18 +1294,30 @@ in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=2147483648:2214592511
+range=0:67108863
 port=system.membus.master[1]
 
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
 [system.realview.realview_io]
 type=RealViewCtrl
 clk_domain=system.clk_domain
 eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
 pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
 system=system
 pio=system.iobus.master[1]
 
@@ -1153,34 +1328,12 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
 pio_latency=100000
 system=system
 time=Thu Jan  1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -1188,21 +1341,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
 pio_latency=100000
 system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
 
 [system.realview.timer0]
 type=Sp804
@@ -1212,9 +1354,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
 pio_latency=100000
 system=system
 pio=system.iobus.master[2]
@@ -1227,9 +1369,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
 pio_latency=100000
 system=system
 pio=system.iobus.master[3]
@@ -1241,8 +1383,8 @@ end_on_eot=false
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
 pio_latency=100000
 platform=system.realview
 system=system
@@ -1255,10 +1397,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
 pio_latency=100000
 system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -1266,10 +1408,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
 pio_latency=100000
 system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -1277,10 +1419,54 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
 pio_latency=100000
 system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -1288,10 +1474,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
 pio_latency=100000
 system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
 
 [system.terminal]
 type=Terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
index 9dee17aa2..af6ec8fad 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
@@ -1,13 +1,39 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
+warn: 	instruction 'mcr bpiall' unimplemented
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index bf118f1e9..c57bb127b 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,15 +1,32 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:07:33
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 15:58:03
 gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
-      0: system.cpu0.isa: ISA system set to: 0x6a97800 0x6a97800
-      0: system.cpu1.isa: ISA system set to: 0x6a97800 0x6a97800
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+      0: system.cpu0.isa: ISA system set to: 0x530db00 0x530db00
+      0: system.cpu1.isa: ISA system set to: 0x530db00 0x530db00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 912096767500 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2802882496500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 2e680c93e..53a29a0e7 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -1,300 +1,312 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.900830                       # Number of seconds simulated
-sim_ticks                                900829868000                       # Number of ticks simulated
-final_tick                               900829868000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.802882                       # Number of seconds simulated
+sim_ticks                                2802882496500                       # Number of ticks simulated
+final_tick                               2802882496500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1355321                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1632835                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            19839612971                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 467260                       # Number of bytes of host memory used
-host_seconds                                    45.41                       # Real time elapsed on the host
-sim_insts                                    61539136                       # Number of instructions simulated
-sim_ops                                      74139862                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1330236                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1620871                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25395755903                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 564312                       # Number of bytes of host memory used
+host_seconds                                   110.37                       # Real time elapsed on the host
+sim_insts                                   146815698                       # Number of instructions simulated
+sim_ops                                     178892459                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           22                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           53                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               75                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           22                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           53                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           75                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           22                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           53                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              75                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.inst           24                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst           52                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            76                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           24                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst           52                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           76                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            6                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           19                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               27                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           19                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           27                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            9                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           19                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              27                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          512                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           468620                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6508860                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           266564                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2938616                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             49504452                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       468620                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       266564                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          735184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3365568                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       3027048                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst          1117476                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          9458684                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           149780                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1082912                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11810580                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1117476                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       149780                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1267256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6081216                       # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6392656                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd       4915200                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8417296                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            8                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             13550                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            101760                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              4256                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             45934                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               5080703                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           52587                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           756762                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             25914                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            148317                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2495                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16944                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                193697                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           95019                       # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               809359                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43650418                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker            71                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           142                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              520209                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             7225404                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              295909                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             3262121                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                54954275                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         520209                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         295909                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             816119                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3736075                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            3360288                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                 44                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7096408                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3736075                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43650418                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker           71                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          142                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             520209                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10585693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             295909                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            3262165                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               62050682                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq             6129610                       # Transaction distribution
-system.membus.trans_dist::ReadResp            6129610                       # Transaction distribution
-system.membus.trans_dist::WriteReq             767040                       # Transaction distribution
-system.membus.trans_dist::WriteResp            767040                       # Transaction distribution
-system.membus.trans_dist::Writeback             52587                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            37380                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          20039                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14449                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            163617                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           136674                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382414                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         8564                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          682                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1995948                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4387646                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port      9830400                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total      9830400                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               14218046                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      2389580                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        17128                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1364                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16575508                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18983656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     39321600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     39321600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                58305256                       # Cumulative packet size per connected master and slave (bytes)
+system.physmem.num_writes::total               135679                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide              343                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           183                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            46                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              398688                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             3374627                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker            46                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               53438                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              386357                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4213726                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         398688                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          53438                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             452126                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2169629                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide          827126                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6316                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3003086                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2169629                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide          827468                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          183                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             398688                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3380944                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              53438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             386371                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7216812                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq               75963                       # Transaction distribution
+system.membus.trans_dist::ReadResp              75963                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30903                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30903                       # Transaction distribution
+system.membus.trans_dist::Writeback             95019                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            60332                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40886                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           15607                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            196321                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           152216                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107918                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13468                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       652185                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       773609                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72952                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72952                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 846561                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           76                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        26936                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17908580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18098400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2334464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2334464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20432864                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            295628                       # Request fanout histogram
+system.membus.snoop_fanout::samples            460731                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  295628    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  460731    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              295628                       # Request fanout histogram
+system.membus.snoop_fanout::total              460731                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    60014                       # number of replacements
-system.l2c.tags.tagsinuse                50124.590156                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     136044                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   120331                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     1.130581                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   107723                       # number of replacements
+system.l2c.tags.tagsinuse                62123.921751                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     208051                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168144                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     1.237338                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37074.868959                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.077014                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     1.053163                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4876.195614                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5801.198822                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1684.572168                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      686.624416                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.565718                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.074405                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.088519                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.025705                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.010477                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.764841                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023            3                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        60314                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           81                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1748                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        13321                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        45151                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000046                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.920319                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  3837449                       # Number of tag accesses
-system.l2c.tags.data_accesses                 3837449                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker           59                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker           32                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst              12381                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data              37925                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker           68                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker           43                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst              18539                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              11807                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  80854                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          175673                       # number of Writeback hits
-system.l2c.Writeback_hits::total               175673                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             221                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             174                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 395                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            20                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            20                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                40                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             7332                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             6046                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                13378                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker            59                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            32                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               12381                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               45257                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            68                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            43                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               18539                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               17853                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                   94232                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker           59                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           32                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              12381                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              45257                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker           68                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           43                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              18539                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              17853                       # number of overall hits
-system.l2c.overall_hits::total                  94232                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
+system.l2c.tags.occ_blocks::writebacks   48622.171138                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.975943                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030392                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7348.709599                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3778.182164                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     1.823425                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1628.255131                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      741.773959                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.741915                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.112132                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.057650                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000028                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.024845                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.011319                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.947936                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        60415                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           73                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1884                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        13069                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        45357                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.921860                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  4905185                       # Number of tag accesses
+system.l2c.tags.data_accesses                 4905185                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker           79                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker           74                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::total                 127129                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          225966                       # number of Writeback hits
+system.l2c.Writeback_hits::total               225966                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             512                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              65                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 577                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            56                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            11                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                67                       # number of SCUpgradeReq hits
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+system.l2c.overall_hits::cpu0.data              89956                       # number of overall hits
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+system.l2c.overall_hits::total                 144183                       # number of overall hits
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 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             6907                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             9458                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.data             1478                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22005                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          5858                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          6485                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             12343                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          694                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          773                       # number of SCUpgradeReq misses
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 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              6907                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            102294                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.data             45955                       # number of demand (read+write) misses
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 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             6907                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           102294                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             4159                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            45955                       # number of overall misses
-system.l2c.overall_misses::total               159318                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker           60                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker           34                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst          19288                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data          47383                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker           68                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker           43                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst          22698                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          13285                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             102859                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       175673                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           175673                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         6079                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         6659                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           12738                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          714                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          793                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1507                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       100168                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        50523                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           150691                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker           60                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           34                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           19288                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          147551                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker           68                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           43                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           22698                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           63808                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              253550                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker           60                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           34                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          19288                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         147551                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           68                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           43                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          22698                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          63808                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             253550                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.016667                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.058824                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.358098                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.199607                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.183232                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.111253                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.213934                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.963645                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.973870                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.968990                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.971989                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.974779                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.973457                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.926803                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.880332                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.911222                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.016667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.058824                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.358098                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.693279                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.183232                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.720207                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.628349                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.016667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.058824                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.358098                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.693279                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.183232                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.720207                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.628349                       # miss rate for overall accesses
+system.l2c.overall_misses::cpu0.inst            16897                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           148112                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker            2                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2330                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            16956                       # number of overall misses
+system.l2c.overall_misses::total               184307                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker           87                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker           76                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst          44954                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data          87301                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker           44                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker           33                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst          13842                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          12489                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             158826                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       225966                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           225966                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        10479                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         3367                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           13846                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          819                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1192                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2011                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       150767                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        18897                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           169664                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker           87                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           76                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           44954                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          238068                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           44                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           33                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           13842                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           31386                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              328490                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker           87                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           76                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          44954                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         238068                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           44                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           33                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          13842                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          31386                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             328490                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.091954                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.026316                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.375873                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.129621                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.045455                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.168328                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.091440                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.199571                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.951140                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.980695                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.958327                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.931624                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.990772                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.966683                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.907334                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.836852                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.899484                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.091954                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.026316                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.375873                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.622142                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.045455                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.168328                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.540241                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.561073                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.091954                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.026316                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.375873                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.622142                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.045455                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.168328                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.540241                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.561073                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -303,101 +315,129 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               52587                       # number of writebacks
-system.l2c.writebacks::total                    52587                       # number of writebacks
+system.l2c.writebacks::writebacks               95019                       # number of writebacks
+system.l2c.writebacks::total                    95019                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            1357667                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           1357667                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            767040                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           767040                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           175673                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           37136                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         20079                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          57215                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           177634                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          177634                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      2263595                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      2631190                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               4894785                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     23563666                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     15087382                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               38651048                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                               0                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           575784                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean                   1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
+system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq             305028                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            305028                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30903                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30903                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           225966                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           60515                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         40953                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         101468                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           213769                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          213769                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1117772                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       410530                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1528302                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34667382                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10427306                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               45094688                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           36713                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           838693                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.043491                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.203961                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 575784    100.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 802217     95.65%     95.65% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  36476      4.35%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             575784                       # Request fanout histogram
-system.iobus.trans_dist::ReadReq              6098452                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             6098452                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                7955                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               7955                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30522                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7906                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total             838693                       # Request fanout histogram
+system.iobus.trans_dist::ReadReq                31002                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31002                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59433                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              23209                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56624                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          684                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          488                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          834                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382414                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side      9830400                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total      9830400                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                12212814                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        40294                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio        15812                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107918                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180870                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71568                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio         1368                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          268                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          441                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      2389580                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     39321600                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total     39321600                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                 41711180                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162808                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2484056                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -421,25 +461,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7391828                       # DTB read hits
-system.cpu0.dtb.read_misses                      1916                       # DTB read misses
-system.cpu0.dtb.write_hits                    6659769                       # DTB write hits
-system.cpu0.dtb.write_misses                     1130                       # DTB write misses
-system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1223                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.read_hits                    20338466                       # DTB read hits
+system.cpu0.dtb.read_misses                      6871                       # DTB read misses
+system.cpu0.dtb.write_hits                   16389914                       # DTB write hits
+system.cpu0.dtb.write_misses                     1093                       # DTB write misses
+system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    3499                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                    84                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  1788                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      185                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7393744                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6660899                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                20345337                       # DTB read accesses
+system.cpu0.dtb.write_accesses               16391007                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14051597                       # DTB hits
-system.cpu0.dtb.misses                           3046                       # DTB misses
-system.cpu0.dtb.accesses                     14054643                       # DTB accesses
+system.cpu0.dtb.hits                         36728380                       # DTB hits
+system.cpu0.dtb.misses                           7964                       # DTB misses
+system.cpu0.dtb.accesses                     36736344                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -461,127 +501,129 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    37936653                       # ITB inst hits
-system.cpu0.itb.inst_misses                      1207                       # ITB inst misses
+system.cpu0.itb.inst_hits                    97433991                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3358                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                     848                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2160                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                37937860                       # ITB inst accesses
-system.cpu0.itb.hits                         37936653                       # DTB hits
-system.cpu0.itb.misses                           1207                       # DTB misses
-system.cpu0.itb.accesses                     37937860                       # DTB accesses
-system.cpu0.numCycles                      1801220958                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                97437349                       # ITB inst accesses
+system.cpu0.itb.hits                         97433991                       # DTB hits
+system.cpu0.itb.misses                           3358                       # DTB misses
+system.cpu0.itb.accesses                     97437349                       # DTB accesses
+system.cpu0.numCycles                      5605766965                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   37699441                       # Number of instructions committed
-system.cpu0.committedOps                     44947195                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             39864660                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4171                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1205511                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4698026                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    39864660                       # number of integer instructions
-system.cpu0.num_fp_insts                         4171                       # number of float instructions
-system.cpu0.num_int_register_reads           70364659                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          26109079                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3915                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                256                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           134799783                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           18388749                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     14597797                       # number of memory refs
-system.cpu0.num_load_insts                    7571468                       # Number of load instructions
-system.cpu0.num_store_insts                   7026329                       # Number of store instructions
-system.cpu0.num_idle_cycles              1756040520.255098                       # Number of idle cycles
-system.cpu0.num_busy_cycles              45180437.744902                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.025083                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.974917                       # Percentage of idle cycles
-system.cpu0.Branches                          6054439                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                13280      0.03%      0.03% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 30339474     67.42%     67.45% # Class of executed instruction
-system.cpu0.op_class::IntMult                   51765      0.12%     67.56% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc               639      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.56% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7571468     16.82%     84.39% # Class of executed instruction
-system.cpu0.op_class::MemWrite                7026329     15.61%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   95421538                       # Number of instructions committed
+system.cpu0.committedOps                    115553717                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            100756647                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
+system.cpu0.num_func_calls                    7999979                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     13203645                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   100756647                       # number of integer instructions
+system.cpu0.num_fp_insts                         9755                       # number of float instructions
+system.cpu0.num_int_register_reads          182446507                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          69131058                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           349951369                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           44905035                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     37871263                       # number of memory refs
+system.cpu0.num_load_insts                   20596038                       # Number of load instructions
+system.cpu0.num_store_insts                  17275225                       # Number of store instructions
+system.cpu0.num_idle_cycles              5488189135.402444                       # Number of idle cycles
+system.cpu0.num_busy_cycles              117577829.597556                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.020974                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.979026                       # Percentage of idle cycles
+system.cpu0.Branches                         21940727                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 78883166     67.49%     67.50% # Class of executed instruction
+system.cpu0.op_class::IntMult                  110618      0.09%     67.59% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              8087      0.01%     67.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.60% # Class of executed instruction
+system.cpu0.op_class::MemRead                20596038     17.62%     85.22% # Class of executed instruction
+system.cpu0.op_class::MemWrite               17275225     14.78%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  45002955                       # Class of executed instruction
+system.cpu0.op_class::total                 116875407                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   42789                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           346148                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.428315                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           37590948                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           346660                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           108.437512                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       4521683000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.428315                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998883                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998883                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    1971                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements          1109428                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.809991                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           96326384                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1109940                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            86.785217                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6345717500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.809991                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999629                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999629                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          212                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         76221879                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        76221879                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     37590948                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       37590948                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     37590948                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        37590948                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     37590948                       # number of overall hits
-system.cpu0.icache.overall_hits::total       37590948                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       346661                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       346661                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       346661                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        346661                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       346661                       # number of overall misses
-system.cpu0.icache.overall_misses::total       346661                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     37937609                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     37937609                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     37937609                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     37937609                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     37937609                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     37937609                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009138                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.009138                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009138                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.009138                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009138                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.009138                       # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses        195982615                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       195982615                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     96326384                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       96326384                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     96326384                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        96326384                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     96326384                       # number of overall hits
+system.cpu0.icache.overall_hits::total       96326384                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1109949                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1109949                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1109949                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1109949                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1109949                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1109949                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     97436333                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     97436333                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     97436333                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     97436333                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     97436333                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     97436333                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011392                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011392                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011392                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011392                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011392                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011392                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -600,121 +642,123 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements          133971                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       15179.385733                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs            737408                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          149269                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            4.940128                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle       992860000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  7074.912262                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     8.111336                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.268775                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3357.655544                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  4738.437815                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.431818                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000495                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.204935                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.289211                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.926476                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           20                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15278                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3216                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5292                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         6770                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.001221                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.932495                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        17962499                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       17962499                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         4364                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         1619                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst       326789                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data       179454                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        512226                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       323282                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       323282                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data            2                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total            2                       # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data        38112                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total        38112                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         4364                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         1619                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst       326789                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       217566                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total         550338                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         4364                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         1619                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst       326789                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       217566                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total        550338                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker           89                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           56                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        19767                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data        70654                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        90566                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        12767                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        12767                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data         8852                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total         8852                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       114761                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       114761                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker           89                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker           56                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        19767                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       185415                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       205327                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker           89                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker           56                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        19767                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       185415                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       205327                       # number of overall misses
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         4453                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         1675                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst       346556                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data       250108                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       602792                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       323282                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       323282                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        12769                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        12769                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data         8852                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total         8852                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       152873                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       152873                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         4453                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         1675                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst       346556                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       402981                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total       755665                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         4453                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         1675                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst       346556                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       402981                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total       755665                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.019987                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.033433                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.057038                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.282494                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.150244                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999843                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999843                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.tags.replacements          252470                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16140.899010                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           1809063                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          268660                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.733652                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle      1814551000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  8130.897895                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.403919                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.095149                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4678.277611                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3330.224436                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.496271                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000086                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000006                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.285539                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.203261                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.985162                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        16181                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          280                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5558                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7600                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2662                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.987610                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        39435786                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       39435786                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7516                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3210                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1064995                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.data       352145                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total       1427866                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       511188                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       511188                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data           17                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total           17                       # number of UpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data        94088                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total        94088                       # number of ReadExReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7516                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3210                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1064995                       # number of demand (read+write) hits
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+system.cpu0.l2cache.demand_hits::total        1521954                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7516                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3210                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1064995                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       446233                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1521954                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          216                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          135                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.inst        44954                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.data       128031                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total       173336                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26217                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        26217                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18426                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        18426                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       175429                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       175429                       # number of ReadExReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          216                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          135                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        44954                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       303460                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       348765                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          216                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          135                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        44954                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       303460                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       348765                       # number of overall misses
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         7732                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3345                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1109949                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.data       480176                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total      1601202                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       511188                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       511188                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        26234                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        26234                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        18426                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        18426                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269517                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       269517                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         7732                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3345                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1109949                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       749693                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      1870719                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         7732                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3345                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1109949                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       749693                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      1870719                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.027936                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.040359                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.040501                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.266633                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.108254                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999352                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999352                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.750695                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.750695                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.019987                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.033433                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.057038                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.460109                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.271717                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.019987                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.033433                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.057038                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.460109                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.271717                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.650901                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.650901                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.027936                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.040359                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040501                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.404779                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.186434                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.027936                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.040359                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040501                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.404779                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.186434                       # miss rate for overall accesses
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -723,79 +767,81 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       114351                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          114351                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks       192932                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          192932                       # number of writebacks
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           371621                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          458.751149                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           12812322                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           371931                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            34.448115                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         22109000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   458.751149                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.895998                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.895998                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          310                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          310                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.605469                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         26837769                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        26837769                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6854480                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6854480                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5591690                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5591690                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        77211                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        77211                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       134223                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       134223                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       135188                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       135188                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12446170                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12446170                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12523381                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12523381                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       187851                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       187851                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       165642                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       165642                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        51876                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total        51876                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10381                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        10381                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         8852                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         8852                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       353493                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        353493                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       405369                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       405369                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7042331                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7042331                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5757332                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5757332                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       129087                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       129087                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       144604                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       144604                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144040                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       144040                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12799663                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12799663                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12928750                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12928750                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.026675                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.026675                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.028771                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.028771                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.401869                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.401869                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.071789                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.071789                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.061455                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.061455                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027617                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.027617                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031354                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.031354                       # miss rate for overall accesses
+system.cpu0.dcache.tags.replacements           693475                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.745909                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           35929913                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           693987                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            51.773179                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         23662000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.745909                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966301                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.966301                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          277                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         74108905                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        74108905                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     19107323                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       19107323                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     15689235                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15689235                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       346054                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       346054                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       379605                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       379605                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       363036                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       363036                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     34796558                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        34796558                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     35142612                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       35142612                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       373110                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       373110                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       295751                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       295751                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       100324                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       100324                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6742                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         6742                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        18426                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        18426                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       668861                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        668861                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       769185                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       769185                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     19480433                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     19480433                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     15984986                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     15984986                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446378                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       446378                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386347                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       386347                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381462                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       381462                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     35465419                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     35465419                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     35911797                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     35911797                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.019153                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.019153                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018502                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018502                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224751                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.224751                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.017451                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.017451                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.048304                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.048304                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018860                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.018860                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021419                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.021419                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -804,45 +850,45 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       323282                       # number of writebacks
-system.cpu0.dcache.writebacks::total           323282                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       511188                       # number of writebacks
+system.cpu0.dcache.writebacks::total           511188                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq        689270                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp       689270                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq       763494                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp       763494                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       323282                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        12769                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq         8852                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp        21621                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       152873                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       152873                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side       706618                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2854542                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         4790                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        11848                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          3577798                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     22212896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     49695730                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         9580                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        23696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total          71941902                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     229047                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      1276029                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.135706                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.342476                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq       1651550                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1651550                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28399                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28399                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       511188                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        26234                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        18426                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp        44660                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       269517                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       269517                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2237944                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2219872                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12828                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        28796                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          4499440                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     71072828                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80887162                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        25656                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        57592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         152043238                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     321922                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      2655621                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.082587                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.275257                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5           1102864     86.43%     86.43% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6            173165     13.57%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5           2436302     91.74%     91.74% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6            219319      8.26%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       1276029                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total       2655621                       # Request fanout histogram
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -866,25 +912,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     6029083                       # DTB read hits
-system.cpu1.dtb.read_misses                      5405                       # DTB read misses
-system.cpu1.dtb.write_hits                    4781968                       # DTB write hits
-system.cpu1.dtb.write_misses                     1104                       # DTB write misses
-system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2367                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.read_hits                    12172110                       # DTB read hits
+system.cpu1.dtb.read_misses                      2853                       # DTB read misses
+system.cpu1.dtb.write_hits                    7585805                       # DTB write hits
+system.cpu1.dtb.write_misses                      506                       # DTB write misses
+system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    2013                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   185                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   290                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      267                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 6034488                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4783072                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                12174963                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7586311                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         10811051                       # DTB hits
-system.cpu1.dtb.misses                           6509                       # DTB misses
-system.cpu1.dtb.accesses                     10817560                       # DTB accesses
+system.cpu1.dtb.hits                         19757915                       # DTB hits
+system.cpu1.dtb.misses                           3359                       # DTB misses
+system.cpu1.dtb.accesses                     19761274                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -906,130 +952,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    24627232                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3166                       # ITB inst misses
+system.cpu1.itb.inst_hits                    53664371                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1734                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1581                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    1136                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                24630398                       # ITB inst accesses
-system.cpu1.itb.hits                         24627232                       # DTB hits
-system.cpu1.itb.misses                           3166                       # DTB misses
-system.cpu1.itb.accesses                     24630398                       # DTB accesses
-system.cpu1.numCycles                      1801708036                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                53666105                       # ITB inst accesses
+system.cpu1.itb.hits                         53664371                       # DTB hits
+system.cpu1.itb.misses                           1734                       # DTB misses
+system.cpu1.itb.accesses                     53666105                       # DTB accesses
+system.cpu1.numCycles                      5605295863                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   23839695                       # Number of instructions committed
-system.cpu1.committedOps                     29192667                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             25548618                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5779                       # Number of float alu accesses
-system.cpu1.num_func_calls                     987959                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2987443                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    25548618                       # number of integer instructions
-system.cpu1.num_fp_insts                         5779                       # number of float instructions
-system.cpu1.num_int_register_reads           48280801                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          17496069                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3771                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               2012                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            86968126                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           11050847                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     11166773                       # number of memory refs
-system.cpu1.num_load_insts                    6206724                       # Number of load instructions
-system.cpu1.num_store_insts                   4960049                       # Number of store instructions
-system.cpu1.num_idle_cycles              1771724648.110516                       # Number of idle cycles
-system.cpu1.num_busy_cycles              29983387.889484                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.016642                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.983358                       # Percentage of idle cycles
-system.cpu1.Branches                          4459767                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                15552      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 18047467     61.65%     61.71% # Class of executed instruction
-system.cpu1.op_class::IntMult                   40427      0.14%     61.85% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              1550      0.01%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     61.85% # Class of executed instruction
-system.cpu1.op_class::MemRead                 6206724     21.20%     83.06% # Class of executed instruction
-system.cpu1.op_class::MemWrite                4960049     16.94%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   51394160                       # Number of instructions committed
+system.cpu1.committedOps                     63338742                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             56976202                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
+system.cpu1.num_func_calls                    9170283                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      5966381                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    56976202                       # number of integer instructions
+system.cpu1.num_fp_insts                         1792                       # number of float instructions
+system.cpu1.num_int_register_reads          110660301                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          41292600                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           196241872                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           18891627                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     20022980                       # number of memory refs
+system.cpu1.num_load_insts                   12287666                       # Number of load instructions
+system.cpu1.num_store_insts                   7735314                       # Number of store instructions
+system.cpu1.num_idle_cycles              5539691262.121797                       # Number of idle cycles
+system.cpu1.num_busy_cycles              65604600.878203                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.011704                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.988296                       # Percentage of idle cycles
+system.cpu1.Branches                         15216192                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 45395839     69.36%     69.36% # Class of executed instruction
+system.cpu1.op_class::IntMult                   28345      0.04%     69.40% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              3315      0.01%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::MemRead                12287666     18.77%     88.18% # Class of executed instruction
+system.cpu1.op_class::MemWrite                7735314     11.82%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  29271769                       # Class of executed instruction
+system.cpu1.op_class::total                  65450545                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   48299                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements           398154                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          474.812776                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           24230251                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           398666                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            60.778323                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     103932913000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   474.812776                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.927369                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.927369                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                    2734                       # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements           523179                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.711075                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           53141770                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           523691                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs           101.475431                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      76931405000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.711075                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975998                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975998                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          217                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          477                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           35                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         49656500                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        49656500                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     24230251                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       24230251                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     24230251                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        24230251                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     24230251                       # number of overall hits
-system.cpu1.icache.overall_hits::total       24230251                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       398666                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       398666                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       398666                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        398666                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       398666                       # number of overall misses
-system.cpu1.icache.overall_misses::total       398666                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     24628917                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     24628917                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     24628917                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     24628917                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     24628917                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     24628917                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.016187                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.016187                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.016187                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.016187                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.016187                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.016187                       # miss rate for overall accesses
+system.cpu1.icache.tags.tag_accesses        107854613                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       107854613                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     53141770                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       53141770                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     53141770                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        53141770                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     53141770                       # number of overall hits
+system.cpu1.icache.overall_hits::total       53141770                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       523691                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       523691                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       523691                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        523691                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       523691                       # number of overall misses
+system.cpu1.icache.overall_misses::total       523691                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     53665461                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     53665461                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     53665461                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     53665461                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     53665461                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     53665461                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009758                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.009758                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009758                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.009758                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009758                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.009758                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1048,123 +1092,121 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements           88565                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       12390.036216                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            691452                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs          104644                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            6.607660                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    876305009500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6229.071421                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     8.886003                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.649559                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3323.104999                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2826.324234                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.380192                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000542                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000162                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.202826                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.172505                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.756228                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        16066                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          380                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         3299                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         9480                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         2833                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000793                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.980591                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        15740589                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       15740589                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         5896                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2700                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst       375664                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data       151551                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        535811                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       209707                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       209707                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data           21                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total           21                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        48287                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        48287                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         5896                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2700                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       375664                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       199838                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         584098                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         5896                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2700                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       375664                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       199838                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        584098                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          349                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          263                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst        22734                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data        51350                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        74696                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        18752                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        18752                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        11227                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        11227                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        68490                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        68490                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          349                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          263                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        22734                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       119840                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       143186                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          349                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          263                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        22734                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       119840                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       143186                       # number of overall misses
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         6245                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2963                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       398398                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data       202901                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       610507                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       209707                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       209707                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        18773                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        18773                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        11227                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        11227                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data       116777                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total       116777                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         6245                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2963                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       398398                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       319678                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       727284                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         6245                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2963                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       398398                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       319678                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       727284                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.055885                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.088761                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.057064                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.253079                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.122351                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.998881                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.998881                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.tags.replacements           48552                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15311.760536                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs            716558                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           63379                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           11.305922                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  8243.045220                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     2.958358                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.015688                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3303.816337                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3759.924934                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.503116                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000181                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000123                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.201649                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.229488                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.934556                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           18                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14809                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          540                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         9336                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4933                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001099                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.903870                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        15206583                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       15206583                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3143                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1725                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.inst       509849                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.data        99406                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        614123                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       120669                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       120669                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data            8                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total            8                       # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        19820                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        19820                       # number of ReadExReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3143                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1725                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       509849                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       119226                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         633943                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3143                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1725                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       509849                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       119226                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        633943                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          348                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          271                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.inst        13842                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.data        73217                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        87678                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28845                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        28845                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22527                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22527                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        43793                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        43793                       # number of ReadExReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          348                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          271                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        13842                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       117010                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       131471                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          348                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          271                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        13842                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       117010                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       131471                       # number of overall misses
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3491                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1996                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       523691                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.data       172623                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       701801                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       120669                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       120669                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28853                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        28853                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        22527                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        22527                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        63613                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        63613                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3491                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1996                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       523691                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       236236                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       765414                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3491                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1996                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       523691                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       236236                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       765414                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.099685                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.135772                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.026432                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.424144                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.124933                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999723                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999723                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.586502                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.586502                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.055885                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.088761                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.057064                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.374877                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.196878                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.055885                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.088761                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.057064                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.374877                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.196878                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.688428                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.688428                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.099685                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.135772                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026432                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.495310                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.171765                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.099685                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.135772                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026432                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.495310                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.171765                       # miss rate for overall accesses
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1173,81 +1215,80 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        61322                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           61322                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks        33034                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           33034                       # number of writebacks
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           299305                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          464.628152                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            9384005                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           299817                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            31.299109                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      94422670000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   464.628152                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.907477                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.907477                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          286                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         19727044                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        19727044                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      4592285                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        4592285                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4538287                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4538287                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        35329                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        35329                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        94231                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        94231                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        93873                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        93873                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      9130572                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         9130572                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      9165901                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        9165901                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       163656                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       163656                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       135550                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       135550                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        28044                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        28044                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11201                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11201                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        11227                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        11227                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       299206                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        299206                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       327250                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       327250                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      4755941                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      4755941                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4673837                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4673837                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        63373                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        63373                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105432                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       105432                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       105100                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       105100                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      9429778                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      9429778                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      9493151                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      9493151                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.034411                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.034411                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029002                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.029002                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.442523                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.442523                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.106239                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.106239                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106822                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106822                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031730                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.031730                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034472                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.034472                       # miss rate for overall accesses
+system.cpu1.dcache.tags.replacements           191901                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          472.757627                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           19500351                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           192255                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs           101.429617                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     105851562500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.757627                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.923355                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.923355                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          341                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.691406                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         39745522                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        39745522                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     11856979                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       11856979                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      7396120                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       7396120                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50084                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        50084                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        91418                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        91418                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72426                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        72426                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     19253099                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        19253099                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     19303183                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       19303183                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       136590                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       136590                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        92466                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        92466                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30716                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30716                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5317                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         5317                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        22527                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        22527                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       229056                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        229056                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       259772                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       259772                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     11993569                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     11993569                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      7488586                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      7488586                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80800                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        80800                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96735                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        96735                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94953                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        94953                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     19482155                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     19482155                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     19562955                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     19562955                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011389                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.011389                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.012348                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.012348                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380149                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380149                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.054965                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.054965                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.237244                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.237244                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.011757                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.011757                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.013279                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.013279                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1256,60 +1297,88 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       209707                       # number of writebacks
-system.cpu1.dcache.writebacks::total           209707                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks       120669                       # number of writebacks
+system.cpu1.dcache.writebacks::total           120669                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       1728836                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1728836                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         3546                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         3546                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       209707                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        18773                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        11227                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        30000                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq       116777                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp       116777                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side       797550                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      3132383                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        12644                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        25448                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          3968025                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     25515060                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     36101346                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        25288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          61692590                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     259574                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1204043                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.188487                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.391100                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq        709063                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       709063                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2504                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2504                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       120669                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        28853                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        22527                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        51380                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        63613                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        63613                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1047738                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       707355                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6616                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        12080                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          1773789                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     33516936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     22861090                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13232                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        24160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          56415418                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     499577                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1371208                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.313508                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.463919                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5            977097     81.15%     81.15% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6            226946     18.85%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5            941324     68.65%     68.65% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6            429884     31.35%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1204043                       # Request fanout histogram
-system.iocache.tags.replacements                    0                       # number of replacements
-system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
+system.cpu1.toL2Bus.snoop_fanout::total       1371208                       # Request fanout histogram
+system.iocache.tags.replacements                36442                       # number of replacements
+system.iocache.tags.tagsinuse               14.586086                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
-system.iocache.tags.data_accesses                   0                       # Number of data accesses
+system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         246641119509                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.586086                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.911630                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.911630                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
+system.iocache.tags.data_accesses              328284                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
+system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          252                       # number of overall misses
+system.iocache.overall_misses::total              252                       # number of overall misses
+system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      36224                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
index f2f53421d..89f9e916a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 77c7c4efb..8b9ee8e26 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
 have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
 mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.vram system.realview.nvmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -53,14 +53,14 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
 
 [system.bridge]
 type=Bridge
 clk_domain=system.clk_domain
 delay=50000
 eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -278,6 +278,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -344,7 +345,7 @@ tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
 
 [system.cpu.l2cache.tags]
 type=LRU
@@ -398,15 +399,16 @@ type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
-use_default_range=false
+use_default_range=true
 width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
 type=BaseCache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
 eventq_index=0
@@ -425,8 +427,8 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
 type=LRU
@@ -449,8 +451,8 @@ system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -480,47 +482,38 @@ in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=0:134217727
-port=system.membus.master[6]
+range=2147483648:2415919103
+port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
 pci_cfg_gen_offsets=false
 pci_io_base=0
 system=system
 
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
 pio_latency=100000
 system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
 
 [system.realview.cf_ctrl]
 type=IdeController
-BAR0=402653184
+BAR0=471465984
 BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
 BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
 BAR2=1
 BAR2LegacyIO=false
 BAR2Size=8
@@ -590,18 +583,18 @@ VendorID=32902
 clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
-disks=system.cf0
+disks=
 eventq_index=0
-io_shift=1
+io_shift=2
 pci_bus=2
-pci_dev=7
+pci_dev=0
 pci_func=0
 pio_latency=30000
 platform=system.realview
 system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.clcd]
 type=Pl111
@@ -610,8 +603,8 @@ clk_domain=system.clk_domain
 enable_capture=true
 eventq_index=0
 gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
 pio_latency=10000
 pixel_clock=41667
 system=system
@@ -619,51 +612,129 @@ vnc=system.vncserver
 dma=system.iobus.slave[1]
 pio=system.iobus.master[4]
 
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
 clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
 eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
 pio_latency=100000
 system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
 
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
 clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
 eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
 system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
 pio=system.iobus.master[25]
 
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
 eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
 system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
 clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
 cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
@@ -673,38 +744,111 @@ platform=system.realview
 system=system
 pio=system.membus.master[2]
 
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
 clk_domain=system.clk_domain
+enable_capture=true
 eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
 system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
 
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
 clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
 eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
 system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
 
 [system.realview.kmi0]
 type=Pl050
@@ -713,13 +857,13 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=52
+int_num=44
 is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.kmi1]
 type=Pl050
@@ -728,20 +872,20 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=53
+int_num=45
 is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.l2x0_fake]
 type=IsaFake
 clk_domain=system.clk_domain
 eventq_index=0
 fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
 pio_latency=100000
 pio_size=4095
 ret_bad_addr=false
@@ -752,7 +896,25 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
@@ -761,10 +923,10 @@ eventq_index=0
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -772,10 +934,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
 pio_latency=100000
 system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
 
 [system.realview.nvmem]
 type=SimpleMemory
@@ -787,18 +949,30 @@ in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=2147483648:2214592511
+range=0:67108863
 port=system.membus.master[1]
 
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
 [system.realview.realview_io]
 type=RealViewCtrl
 clk_domain=system.clk_domain
 eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
 pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
 system=system
 pio=system.iobus.master[1]
 
@@ -809,34 +983,12 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
 pio_latency=100000
 system=system
 time=Thu Jan  1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -844,21 +996,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
 pio_latency=100000
 system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
 
 [system.realview.timer0]
 type=Sp804
@@ -868,9 +1009,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
 pio_latency=100000
 system=system
 pio=system.iobus.master[2]
@@ -883,9 +1024,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
 pio_latency=100000
 system=system
 pio=system.iobus.master[3]
@@ -897,8 +1038,8 @@ end_on_eot=false
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
 pio_latency=100000
 platform=system.realview
 system=system
@@ -911,10 +1052,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
 pio_latency=100000
 system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -922,10 +1063,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
 pio_latency=100000
 system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -933,10 +1074,54 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
 pio_latency=100000
 system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -944,10 +1129,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
 pio_latency=100000
 system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
 
 [system.terminal]
 type=Terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
index 9dee17aa2..cda172af7 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
@@ -1,13 +1,32 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index c1d447bb6..624db6e54 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -1,14 +1,31 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:06:34
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 15:56:38
 gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
-      0: system.cpu.isa: ISA system set to: 0x55f5800 0x55f5800
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+      0: system.cpu.isa: ISA system set to: 0x55e4b00 0x55e4b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2332810269000 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2783853461500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 227319fff..e8036ea95 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,171 +1,203 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.321335                       # Number of seconds simulated
-sim_ticks                                2321335404000                       # Number of ticks simulated
-final_tick                               2321335404000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.783853                       # Number of seconds simulated
+sim_ticks                                2783853461500                       # Number of ticks simulated
+final_tick                               2783853461500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1308981                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1576286                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            50301976363                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 455960                       # Number of bytes of host memory used
-host_seconds                                    46.15                       # Real time elapsed on the host
-sim_insts                                    60406834                       # Number of instructions simulated
-sim_ops                                      72742429                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1369296                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1666897                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            26699855189                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 553552                       # Number of bytes of host memory used
+host_seconds                                   104.26                       # Real time elapsed on the host
+sim_insts                                   142769281                       # Number of instructions simulated
+sim_ops                                     173798567                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1210980                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10345892                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11558408                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1210980                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1210980                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6521472                       # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8857332                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              27375                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             162174                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                189573                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          101898                       # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142503                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            161                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             46                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               435001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3716392                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4151946                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          435001                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             435001                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2342606                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide          832779                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6295                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3181680                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2342606                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide          833124                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           161                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            46                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              435001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3722687                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7333626                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst           24                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            24                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           24                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           24                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            6                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              6                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu.inst             9                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            9                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd    110100480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            705416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9071832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            119878240                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       705416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          705416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3703872                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6719688                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      13762560                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17234                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141773                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              13921575                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57873                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811827                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47429803                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            138                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             83                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               303884                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3908023                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51641930                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          303884                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             303884                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1595578                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1299173                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2894751                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1595578                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47429803                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           138                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            83                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              303884                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5207196                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54536681                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq            14973631                       # Transaction distribution
-system.membus.trans_dist::ReadResp           14973631                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763122                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763122                       # Transaction distribution
-system.membus.trans_dist::Writeback             57873                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4517                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4517                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131874                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131874                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2382824                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3360                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1892845                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4279041                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     27525120                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     27525120                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               31804161                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390127                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         6720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16497448                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18894319                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port    110100480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total    110100480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               128994799                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               74236                       # Transaction distribution
+system.membus.trans_dist::ReadResp              74236                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27560                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27560                       # Transaction distribution
+system.membus.trans_dist::Writeback            101898                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            146085                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           146085                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105446                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           12                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       498794                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       606198                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72928                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72928                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 679126                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159103                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           24                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18096444                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18259463                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2333696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2333696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20593159                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            214751                       # Request fanout histogram
+system.membus.snoop_fanout::samples            322857                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  214751    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  322857    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              214751                       # Request fanout histogram
+system.membus.snoop_fanout::total              322857                       # Request fanout histogram
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq             14945841                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            14945841                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8131                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8131                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7900                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          476                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          984                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
+system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq                30171                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30171                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59016                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22792                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54158                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          732                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          834                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382824                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     27525120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     27525120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                29907944                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        39247                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio        15800                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio          952                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio         1968                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       105446                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72928                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72928                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178374                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67875                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          390                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          441                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      2390127                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    110100480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total    110100480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                112490607                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       159103                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321152                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480255                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -190,25 +222,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     13142243                       # DTB read hits
-system.cpu.dtb.read_misses                       7297                       # DTB read misses
-system.cpu.dtb.write_hits                    11216207                       # DTB write hits
-system.cpu.dtb.write_misses                      2181                       # DTB write misses
-system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3399                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.read_hits                     31525428                       # DTB read hits
+system.cpu.dtb.read_misses                       8580                       # DTB read misses
+system.cpu.dtb.write_hits                    23123837                       # DTB write hits
+system.cpu.dtb.write_misses                      1448                       # DTB write misses
+system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                     4349                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    174                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   1613                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 13149540                       # DTB read accesses
-system.cpu.dtb.write_accesses                11218388                       # DTB write accesses
+system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 31534008                       # DTB read accesses
+system.cpu.dtb.write_accesses                23125285                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          24358450                       # DTB hits
-system.cpu.dtb.misses                            9478                       # DTB misses
-system.cpu.dtb.accesses                      24367928                       # DTB accesses
+system.cpu.dtb.hits                          54649265                       # DTB hits
+system.cpu.dtb.misses                           10028                       # DTB misses
+system.cpu.dtb.accesses                      54659293                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -230,130 +262,130 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     61430007                       # ITB inst hits
-system.cpu.itb.inst_misses                       4471                       # ITB inst misses
+system.cpu.itb.inst_hits                    147035651                       # ITB inst hits
+system.cpu.itb.inst_misses                       4762                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2370                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                     2913                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61434478                       # ITB inst accesses
-system.cpu.itb.hits                          61430007                       # DTB hits
-system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61434478                       # DTB accesses
-system.cpu.numCycles                       4642753590                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                147040413                       # ITB inst accesses
+system.cpu.itb.hits                         147035651                       # DTB hits
+system.cpu.itb.misses                            4762                       # DTB misses
+system.cpu.itb.accesses                     147040413                       # DTB accesses
+system.cpu.numCycles                       5567710004                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60406834                       # Number of instructions committed
-system.cpu.committedOps                      72742429                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              64191430                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2135762                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7544984                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     64191430                       # number of integer instructions
-system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           116427347                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           42818107                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            217570004                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            28977741                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      25221274                       # number of memory refs
-system.cpu.num_load_insts                    13499937                       # Number of load instructions
-system.cpu.num_store_insts                   11721337                       # Number of store instructions
-system.cpu.num_idle_cycles               4568976022.512934                       # Number of idle cycles
-system.cpu.num_busy_cycles               73777567.487067                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.015891                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.984109                       # Percentage of idle cycles
-system.cpu.Branches                          10298517                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                 28518      0.04%      0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu                  47536032     65.23%     65.27% # Class of executed instruction
-system.cpu.op_class::IntMult                    87771      0.12%     65.39% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc               2113      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::MemRead                 13499937     18.52%     83.92% # Class of executed instruction
-system.cpu.op_class::MemWrite                11721337     16.08%    100.00% # Class of executed instruction
+system.cpu.committedInsts                   142769281                       # Number of instructions committed
+system.cpu.committedOps                     173798567                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             153158502                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                  11484                       # Number of float alu accesses
+system.cpu.num_func_calls                    16873305                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18730015                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    153158502                       # number of integer instructions
+system.cpu.num_fp_insts                         11484                       # number of float instructions
+system.cpu.num_int_register_reads           285052059                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          107176408                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                 8772                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            530840054                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            62363143                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      55937812                       # number of memory refs
+system.cpu.num_load_insts                    31855061                       # Number of load instructions
+system.cpu.num_store_insts                   24082751                       # Number of store instructions
+system.cpu.num_idle_cycles               5389631214.604722                       # Number of idle cycles
+system.cpu.num_busy_cycles               178078789.395278                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.031984                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.968016                       # Percentage of idle cycles
+system.cpu.Branches                          36396067                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 121149664     68.36%     68.36% # Class of executed instruction
+system.cpu.op_class::IntMult                   116881      0.07%     68.43% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     68.43% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               8569      0.00%     68.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     68.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.44% # Class of executed instruction
+system.cpu.op_class::MemRead                 31855061     17.98%     86.41% # Class of executed instruction
+system.cpu.op_class::MemWrite                24082751     13.59%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   72875708                       # Class of executed instruction
+system.cpu.op_class::total                  177215263                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    82781                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            850504                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.689630                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            60581751                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            851016                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             71.187558                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        5451547500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.689630                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999394                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999394                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                     3080                       # number of quiesce instructions executed
+system.cpu.icache.tags.replacements           1698994                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.663679                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           145339246                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1699506                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             85.518525                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        7831492000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.663679                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999343                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999343                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           61                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          249                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          62283783                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         62283783                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     60581751                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        60581751                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      60581751                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         60581751                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     60581751                       # number of overall hits
-system.cpu.icache.overall_hits::total        60581751                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       851016                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        851016                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       851016                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         851016                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       851016                       # number of overall misses
-system.cpu.icache.overall_misses::total        851016                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     61432767                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     61432767                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     61432767                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     61432767                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     61432767                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     61432767                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013853                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013853                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013853                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013853                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013853                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013853                       # miss rate for overall accesses
+system.cpu.icache.tags.tag_accesses         148738270                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        148738270                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    145339246                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       145339246                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     145339246                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        145339246                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    145339246                       # number of overall hits
+system.cpu.icache.overall_hits::total       145339246                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1699512                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1699512                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1699512                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1699512                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1699512                       # number of overall misses
+system.cpu.icache.overall_misses::total       1699512                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    147038758                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    147038758                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    147038758                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    147038758                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    147038758                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    147038758                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011558                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.011558                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.011558                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.011558                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.011558                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.011558                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -363,115 +395,121 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            62250                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        50006.820137                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1669876                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           127635                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            13.083214                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2306275686000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36897.819647                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.959772                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.993972                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7014.485209                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6090.561537                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563016                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements           110027                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65155.315266                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2727659                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           175308                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            15.559239                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414938                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931995                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004344                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9064.653997                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7194.309992                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.746054                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000015                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.107033                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.092935                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.763044                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.138316                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.109776                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994191                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65380                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65276                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3672                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9281                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3716                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10700                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50640                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997620                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         17035355                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        17035355                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7540                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3151                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       838782                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       366774                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1216247                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       592630                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       592630                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       113709                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       113709                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         7540                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         3151                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       838782                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       480483                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1329956                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         7540                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         3151                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       838782                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       480483                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1329956                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            3                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        10608                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         9871                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        20487                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2917                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2917                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133474                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133474                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            3                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        10608                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143345                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        153961                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            3                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        10608                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143345                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       153961                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7545                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3154                       # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_accesses::cpu.data       376645                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1236734                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       592630                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       592630                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2943                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2943                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       247183                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       247183                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7545                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         3154                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       849390                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       623828                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1483917                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7545                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         3154                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       849390                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       623828                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1483917                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000951                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012489                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026208                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016565                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991165                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991165                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.539981                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.539981                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000951                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012489                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.229783                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.103753                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000951                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012489                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.229783                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.103753                       # miss rate for overall accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996033                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         26202376                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        26202376                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7597                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3621                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_hits::total        2197846                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       682038                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       682038                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           28                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           28                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       151041                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       151041                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         7597                       # number of demand (read+write) hits
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+system.cpu.l2cache.demand_hits::cpu.data       656532                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2348887                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         7597                       # number of overall hits
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+system.cpu.l2cache.overall_hits::total        2348887                       # number of overall hits
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+system.cpu.l2cache.ReadReq_misses::total        33901                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2728                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2728                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       147864                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       147864                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        18358                       # number of demand (read+write) misses
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+system.cpu.l2cache.demand_misses::total        181765                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
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+system.cpu.l2cache.overall_misses::cpu.data       163398                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       181765                       # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7604                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3623                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1699495                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       521025                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2231747                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       682038                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       682038                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       298905                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       298905                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7604                       # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7604                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         3623                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1699495                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       819930                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2530652                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000552                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010802                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.029814                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.015190                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989840                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989840                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494686                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.494686                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000552                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010802                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.199283                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.071825                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000552                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010802                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.199283                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.071825                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -480,77 +518,81 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        57873                       # number of writebacks
-system.cpu.l2cache.writebacks::total            57873                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       101898                       # number of writebacks
+system.cpu.l2cache.writebacks::total           101898                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            623316                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997018                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            21798557                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            623828                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             34.943217                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          21757000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997018                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            819402                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997174                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            53783051                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            819914                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.595966                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          23054000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997174                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          291                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          286                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          90313368                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         90313368                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     11240238                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11240238                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9961313                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9961313                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       110856                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        110856                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236011                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236011                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247196                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247196                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21201551                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21201551                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21312407                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21312407                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       292017                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        292017                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250126                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250126                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        73442                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        73442                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11186                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11186                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       542143                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         542143                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       615585                       # number of overall misses
-system.cpu.dcache.overall_misses::total        615585                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     11532255                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     11532255                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10211439                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10211439                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       184298                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       184298                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247197                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247197                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247196                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247196                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21743694                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21743694                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21927992                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21927992                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025322                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.025322                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024495                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.398496                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.398496                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045251                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045251                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024933                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024933                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.028073                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.028073                       # miss rate for overall accesses
+system.cpu.dcache.tags.tag_accesses         219231854                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        219231854                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     30128262                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        30128262                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     22339512                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       22339512                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       395063                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        395063                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       457334                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       457334                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460122                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460122                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      52467774                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         52467774                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     52862837                       # number of overall hits
+system.cpu.dcache.overall_hits::total        52862837                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       396291                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        396291                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       301661                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       301661                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       116123                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       116123                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data         8611                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         8611                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data       697952                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         697952                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       814075                       # number of overall misses
+system.cpu.dcache.overall_misses::total        814075                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     30524553                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     30524553                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     22641173                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     22641173                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511186                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511186                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465945                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465945                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460124                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460124                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     53165726                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     53165726                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     53676912                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     53676912                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012983                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012983                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013324                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227164                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.227164                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018481                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.018481                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.013128                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.013128                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.015166                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015166                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -559,59 +601,88 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       592630                       # number of writebacks
-system.cpu.dcache.writebacks::total            592630                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       682038                       # number of writebacks
+system.cpu.dcache.writebacks::total            682038                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2445766                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2445766                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq        763122                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp       763122                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       592630                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2943                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2943                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       247183                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       247183                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1715294                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5740322                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17852                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        37190                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7510658                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54491548                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83266131                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        35704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        74380                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          137867763                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2097938                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        2288345                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2288345                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27560                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27560                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       682038                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2758                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       298905                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       298905                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3417070                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2444678                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18430                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        36996                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5917174                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108804860                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96308747                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        36860                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        73992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          205224459                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       36632                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3268415                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.011156                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.105033                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            2097938    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            3231951     98.88%     98.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6              36464      1.12%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2097938                       # Request fanout histogram
-system.iocache.tags.replacements                    0                       # number of replacements
-system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
+system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        3268415                       # Request fanout histogram
+system.iocache.tags.replacements                36430                       # number of replacements
+system.iocache.tags.tagsinuse                0.909886                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
-system.iocache.tags.data_accesses                   0                       # Number of data accesses
+system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         227409698009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     0.909886                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.056868                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.056868                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               328176                       # Number of tag accesses
+system.iocache.tags.data_accesses              328176                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
+system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          240                       # number of overall misses
+system.iocache.overall_misses::total              240                       # number of overall misses
+system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      36224                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
index d321164ca..b3be0ec54 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index a2ee5f35a..1f2cdefde 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
 have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.realview.nvmem system.physmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -53,14 +53,14 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
 
 [system.bridge]
 type=Bridge
 clk_domain=system.clk_domain
 delay=50000
 eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -274,6 +274,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu0.istage2_mmu]
@@ -562,6 +563,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu1.istage2_mmu]
@@ -699,15 +701,16 @@ type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
-use_default_range=false
+use_default_range=true
 width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
 type=BaseCache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
 eventq_index=0
@@ -726,8 +729,8 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
 type=LRU
@@ -762,7 +765,7 @@ tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
 
 [system.l2c.tags]
 type=LRU
@@ -785,8 +788,8 @@ system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -842,6 +845,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
@@ -851,7 +855,7 @@ mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
 page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -880,46 +884,37 @@ tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
 write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
 pci_cfg_gen_offsets=false
 pci_io_base=0
 system=system
 
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
 pio_latency=100000
 system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
 
 [system.realview.cf_ctrl]
 type=IdeController
-BAR0=402653184
+BAR0=471465984
 BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
 BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
 BAR2=1
 BAR2LegacyIO=false
 BAR2Size=8
@@ -989,18 +984,18 @@ VendorID=32902
 clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
-disks=system.cf0
+disks=
 eventq_index=0
-io_shift=1
+io_shift=2
 pci_bus=2
-pci_dev=7
+pci_dev=0
 pci_func=0
 pio_latency=30000
 platform=system.realview
 system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.clcd]
 type=Pl111
@@ -1009,8 +1004,8 @@ clk_domain=system.clk_domain
 enable_capture=true
 eventq_index=0
 gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
 pio_latency=10000
 pixel_clock=41667
 system=system
@@ -1018,51 +1013,129 @@ vnc=system.vncserver
 dma=system.iobus.slave[1]
 pio=system.iobus.master[4]
 
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
 clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
 eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
 pio_latency=100000
 system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
 
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
 clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
 eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
 system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
 pio=system.iobus.master[25]
 
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
 eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
 system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
 clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
 cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
@@ -1072,38 +1145,111 @@ platform=system.realview
 system=system
 pio=system.membus.master[2]
 
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
 clk_domain=system.clk_domain
+enable_capture=true
 eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
 system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
 
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
 clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
 eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
 system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
 
 [system.realview.kmi0]
 type=Pl050
@@ -1112,13 +1258,13 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=52
+int_num=44
 is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1127,20 +1273,20 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=53
+int_num=45
 is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.l2x0_fake]
 type=IsaFake
 clk_domain=system.clk_domain
 eventq_index=0
 fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
 pio_latency=100000
 pio_size=4095
 ret_bad_addr=false
@@ -1151,7 +1297,25 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
@@ -1160,10 +1324,10 @@ eventq_index=0
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -1171,10 +1335,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
 pio_latency=100000
 system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
 
 [system.realview.nvmem]
 type=SimpleMemory
@@ -1186,18 +1350,30 @@ in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=2147483648:2214592511
+range=0:67108863
 port=system.membus.master[1]
 
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
 [system.realview.realview_io]
 type=RealViewCtrl
 clk_domain=system.clk_domain
 eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
 pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
 system=system
 pio=system.iobus.master[1]
 
@@ -1208,34 +1384,12 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
 pio_latency=100000
 system=system
 time=Thu Jan  1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -1243,21 +1397,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
 pio_latency=100000
 system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
 
 [system.realview.timer0]
 type=Sp804
@@ -1267,9 +1410,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
 pio_latency=100000
 system=system
 pio=system.iobus.master[2]
@@ -1282,9 +1425,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
 pio_latency=100000
 system=system
 pio=system.iobus.master[3]
@@ -1296,8 +1439,8 @@ end_on_eot=false
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
 pio_latency=100000
 platform=system.realview
 system=system
@@ -1310,10 +1453,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
 pio_latency=100000
 system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -1321,10 +1464,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
 pio_latency=100000
 system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -1332,10 +1475,54 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
 pio_latency=100000
 system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -1343,10 +1530,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
 pio_latency=100000
 system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
 
 [system.terminal]
 type=Terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
index 9dee17aa2..887c3abd5 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
@@ -1,13 +1,40 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
+warn: 	instruction 'mcr bpiall' unimplemented
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index 2b6d5c5d8..0ab3b3eb3 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,15 +1,32 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:08:43
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 15:58:33
 gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
-      0: system.cpu0.isa: ISA system set to: 0x6319800 0x6319800
-      0: system.cpu1.isa: ISA system set to: 0x6319800 0x6319800
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+      0: system.cpu0.isa: ISA system set to: 0x5550b00 0x5550b00
+      0: system.cpu1.isa: ISA system set to: 0x5550b00 0x5550b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1196139241000 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2866929256000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 20253081d..391ab3c97 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,171 +1,196 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.675181                       # Number of seconds simulated
-sim_ticks                                2675180779000                       # Number of ticks simulated
-final_tick                               2675180779000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.866929                       # Number of seconds simulated
+sim_ticks                                2866929256000                       # Number of ticks simulated
+final_tick                               2866929256000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 349036                       # Simulator instruction rate (inst/s)
-host_op_rate                                   416751                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14917331050                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 433588                       # Number of bytes of host memory used
-host_seconds                                   179.33                       # Real time elapsed on the host
-sim_insts                                    62593972                       # Number of instructions simulated
-sim_ops                                      74737529                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 703930                       # Simulator instruction rate (inst/s)
+host_op_rate                                   851474                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15295798763                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 599572                       # Number of bytes of host memory used
+host_seconds                                   187.43                       # Real time elapsed on the host
+sim_insts                                   131939289                       # Number of instructions simulated
+sim_ops                                     159593891                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.clcd    124256256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           120908                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data           513788                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      6659968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            37828                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           531832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher      3262144                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            135383236                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       120908                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        37828                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          158736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4300032                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7329168                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      15532032                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              8117                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data              8087                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       104062                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               682                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8328                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher        50971                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15712287                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           67188                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               824472                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46447798                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker            48                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            96                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               45196                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              192057                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2489539                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker            48                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               14140                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              198802                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher      1219411                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50607135                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          45196                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          14140                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              59337                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1607380                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6355                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            1125956                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2739691                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1607380                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46447798                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker           48                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           96                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              45196                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             198412                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2489539                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker           48                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              14140                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1324758                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher      1219411                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53346826                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15712287                       # Number of read requests accepted
-system.physmem.writeReqs                       824472                       # Number of write requests accepted
-system.physmem.readBursts                    15712287                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     824472                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM               1005465984                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    120384                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7344256                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 135383236                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7329168                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1881                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  709695                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          15472                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              981539                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              981448                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              981211                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              981521                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              988300                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              981533                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              981210                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              981071                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              981831                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              982015                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             981421                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             980878                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             981926                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             981948                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             981516                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             981038                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7155                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7293                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6957                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6994                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7537                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7187                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7207                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7058                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7329                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7596                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7177                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6681                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7505                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7329                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7034                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6715                       # Per bank write bursts
+system.realview.nvmem.bytes_read::cpu0.inst           24                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst           52                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            76                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           24                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst           52                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           76                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            6                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           18                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               27                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           18                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           27                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           18                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              27                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           234148                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data           830144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      9620672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            49876                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           440928                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher      1365312                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             12542872                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       234148                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        49876                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          284024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6392960                       # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8729040                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             12112                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             13497                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       150323                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               934                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              6913                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher        21333                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                205140                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           99890                       # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               140550                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide              335                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               81672                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              289559                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      3355741                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker            89                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               17397                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              153798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       476228                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4375020                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          81672                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          17397                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              99069                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2229898                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide          808648                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6175                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3044735                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2229898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide          808983                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              81672                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             295734                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      3355741                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker           89                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              17397                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             153812                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       476228                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7419755                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        205141                       # Number of read requests accepted
+system.physmem.writeReqs                       140550                       # Number of write requests accepted
+system.physmem.readBursts                      205141                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     140550                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 13114752                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     14272                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8743552                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12542936                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8729040                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      223                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3913                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          15151                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12845                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12298                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               13022                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12754                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               21257                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12515                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12829                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12945                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12057                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12100                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              12212                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11004                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11810                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12145                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11734                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11391                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8757                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8655                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9184                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8823                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8606                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8736                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8840                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8881                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8404                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8549                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8595                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8133                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8369                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8306                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8199                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7581                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2675178052500                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2866928814500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                    6799                       # Read request sizes (log2)
-system.physmem.readPktSize::3                15532057                       # Read request sizes (log2)
+system.physmem.readPktSize::2                    9742                       # Read request sizes (log2)
+system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  173431                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  195371                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                 757284                       # Write request sizes (log2)
+system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  67188                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1100287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    996591                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    996926                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1111424                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   1006011                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1072049                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2766642                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2669294                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3474563                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    133275                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                   114946                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                   106575                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                   103058                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    20020                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    19187                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18941                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      241                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      126                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       60                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       48                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       36                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                       35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                       23                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                       13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 136114                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    121124                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     21708                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13339                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     11204                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      9572                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      8231                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      7040                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      6218                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      5357                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       501                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      238                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      142                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      104                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       64                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       45                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
@@ -184,507 +209,511 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4098                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5767                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6804                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6950                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7066                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7024                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6754                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1051606                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      963.108084                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     883.927529                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     220.726845                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          33004      3.14%      3.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22001      2.09%      5.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9307      0.89%      6.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2514      0.24%      6.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3272      0.31%      6.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2167      0.21%      6.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8722      0.83%      7.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1051      0.10%      7.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       969568     92.20%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1051606                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6601                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2380.003939                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    98592.588392                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-262143         6595     99.91%     99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-786431            1      0.02%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-1.04858e+06            2      0.03%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06            1      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6601                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6601                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.384336                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.341066                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.250693                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2463     37.31%     37.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 32      0.48%     37.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3686     55.84%     93.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                215      3.26%     96.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 85      1.29%     98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 50      0.76%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 28      0.42%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 18      0.27%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 14      0.21%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  7      0.11%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  3      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6601                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   408788863752                       # Total ticks spent queuing
-system.physmem.totMemAccLat              703358976252                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  78552030000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       26020.26                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4176                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::55                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        80974                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      269.941463                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     151.852686                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     318.869933                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          39277     48.51%     48.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        16073     19.85%     68.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6267      7.74%     76.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3406      4.21%     80.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3201      3.95%     84.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1947      2.40%     86.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1140      1.41%     88.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1004      1.24%     89.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8659     10.69%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          80974                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6724                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        30.475461                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      574.843547                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6723     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6724                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6724                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.317965                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.827449                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.656598                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5486     81.59%     81.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             426      6.34%     87.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              82      1.22%     89.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             201      2.99%     92.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             197      2.93%     95.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              21      0.31%     95.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              19      0.28%     95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              16      0.24%     95.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              29      0.43%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               5      0.07%     96.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.06%     96.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               3      0.04%     96.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             175      2.60%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               8      0.12%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.10%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               4      0.06%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               7      0.10%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.03%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               6      0.09%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             4      0.06%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.04%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.12%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6724                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5972474500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9814687000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1024590000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29145.68                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44770.26                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         375.85                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.75                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       50.61                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.74                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47895.68                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.57                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.05                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.04                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.96                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.94                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.50                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.70                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14689438                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     84116                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.50                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.29                       # Row buffer hit rate for writes
-system.physmem.avgGap                       161771.61                       # Average gap between requests
-system.physmem.pageHitRate                      93.35                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2326940534750                       # Time in different power states
-system.physmem.memoryStateTime::REF       89330020000                       # Time in different power states
+system.physmem.avgRdQLen                         2.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.28                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     175001                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     85560                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.40                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  62.62                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8293327.90                       # Average gap between requests
+system.physmem.pageHitRate                      76.29                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2731384342500                       # Time in different power states
+system.physmem.memoryStateTime::REF       95733040000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      258906121500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       39811853000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                3975289920                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                3974851440                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                2169057000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                2168817750                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0              61291097400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1              61250069400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               371874240                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               371731680                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          174729519120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          174729519120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          149034867885                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          147923300340                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1474373657250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1475348716500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1865945362815                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1865767006230                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             697.503604                       # Core power per rank (mW)
-system.physmem.averagePower::1             697.436933                       # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           18                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           18                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           18                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq            16891737                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16891737                       # Transaction distribution
-system.membus.trans_dist::WriteReq             769090                       # Transaction distribution
-system.membus.trans_dist::WriteResp            769090                       # Transaction distribution
-system.membus.trans_dist::Writeback             67188                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            56135                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          22757                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           15472                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             15580                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             8709                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384390                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13404                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2098                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      2043502                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4443432                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     31064064                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     31064064                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               35507496                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      2392696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        26808                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4196                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18456148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     20879924                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port    124256256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               145136180                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            70292                       # Total snoops (count)
-system.membus.snoop_fanout::samples            326383                       # Request fanout histogram
+system.physmem.actEnergy::0                 323167320                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 288996120                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 176331375                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 157686375                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                861627000                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                736725600                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               456723360                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               428561280                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          187253826240                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          187253826240                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           82374692850                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           81185757210                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1647898682250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1648941608250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1919345050395                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1918993161075                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.477790                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.355049                       # Core power per rank (mW)
+system.membus.trans_dist::ReadReq              228441                       # Transaction distribution
+system.membus.trans_dist::ReadResp             228440                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31177                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31177                       # Transaction distribution
+system.membus.trans_dist::Writeback             99890                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            85859                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          41212                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           15151                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             28398                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            11478                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107964                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14560                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       678158                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       800720                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72716                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72716                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 873436                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162847                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           76                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18952616                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19144659                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21463955                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           129081                       # Total snoops (count)
+system.membus.snoop_fanout::samples            475718                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  326383    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  475718    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              326383                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1567209495                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              475718                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88161999                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy               20500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11789999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12079498                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy             2092500                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         18080219999                       # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4994463970                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        38410223885                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy          1514580499                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         1969894164                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
+system.membus.respLayer3.occupancy           38592409                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    91391                       # number of replacements
-system.l2c.tags.tagsinuse                54779.294121                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     364235                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   156090                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.333493                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   132728                       # number of replacements
+system.l2c.tags.tagsinuse                64199.829322                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     489645                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   197292                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.481829                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    8096.170170                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.060665                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     1.035962                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      869.411373                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     1869.125081                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29277.356218                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     1.888363                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      410.348906                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3214.362362                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11039.535021                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.123538                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.013266                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.028521                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.446737                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000029                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.006261                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.049047                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.168450                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.835866                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        51568                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        13123                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2           28                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         4964                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        46576                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          213                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         1345                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        11561                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.786865                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000122                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.200241                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  4855174                       # Number of tag accesses
-system.l2c.tags.data_accesses                 4855174                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker          111                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker           56                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst               5971                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data              15212                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        88244                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker           87                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker           25                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst               4855                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              12536                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        47744                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 174841                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          208041                       # number of Writeback hits
-system.l2c.Writeback_hits::total               208041                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            3552                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1697                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                5249                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           114                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           201                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               315                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             2350                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             2153                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 4503                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           111                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            56                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst                5971                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               17562                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        88244                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            87                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            25                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                4855                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               14689                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher        47744                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  179344                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          111                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           56                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst               5971                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              17562                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        88244                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker           87                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           25                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst               4855                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              14689                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher        47744                       # number of overall hits
-system.l2c.overall_hits::total                 179344                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             1474                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             3581                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       104062                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              586                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             4041                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher        50971                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               164723                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          7774                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          5401                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             13175                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         1167                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1038                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            2205                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data           4506                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           4295                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total               8801                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              1474                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data              8087                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       104062                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               586                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              8336                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher        50971                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                173524                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             1474                       # number of overall misses
-system.l2c.overall_misses::cpu0.data             8087                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       104062                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              586                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             8336                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher        50971                       # number of overall misses
-system.l2c.overall_misses::total               173524                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       107000                       # number of ReadReq miss cycles
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-system.l2c.ReadReq_miss_latency::cpu0.inst    119004500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    272579750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher   9018021941                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       164250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     50120250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    314939500                       # number of ReadReq miss cycles
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-system.l2c.UpgradeReq_miss_latency::cpu0.data     13917901                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      3379857                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     17297758                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       704472                       # number of SCUpgradeReq miss cycles
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-system.l2c.SCUpgradeReq_miss_latency::total      5065284                       # number of SCUpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::total    638849658                       # number of ReadExReq miss cycles
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-system.l2c.demand_miss_latency::cpu1.data    623712722                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   6107091681                       # number of demand (read+write) miss cycles
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-system.l2c.overall_miss_latency::cpu0.dtb.walker       107000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       298500                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::cpu0.data    602656186                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher   9018021941                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker       164250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     50120250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    623712722                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   6107091681                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    16521177030                       # number of overall miss cycles
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-system.l2c.ReadReq_accesses::cpu0.data          18793                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::cpu1.data          16577                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::total             339564                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       208041                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           208041                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        11326                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         7098                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           18424                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         1281                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         1239                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2520                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data         6856                       # number of ReadExReq accesses(hits+misses)
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-system.l2c.demand_accesses::cpu0.dtb.walker          113                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           60                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst            7445                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           25649                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       192306                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker           89                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst            5441                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           23025                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        98715                       # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu0.dtb.walker          113                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           60                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst           7445                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          25649                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       192306                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           89                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst           5441                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          23025                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        98715                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             352868                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.017699                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.066667                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.197985                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.190550                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.022472                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.107701                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.243771                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.485101                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.686385                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.760919                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.715100                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.911007                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.837772                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.875000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.657235                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.666098                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.661530                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.017699                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.066667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.197985                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.315295                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.022472                       # miss rate for demand accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        53500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74625                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu0.data 76118.332868                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        82125                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85529.436860                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77936.030685                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1790.313995                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   625.783559                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1312.922808                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   603.660668                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4201.167630                       # average SCUpgradeReq miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.inst 85529.436860                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 74821.583733                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 95209.752138                       # average overall miss latency
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+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.043526                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38786.462390                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.540569                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.007801                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      536.338892                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      908.008157                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  8820.200180                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.191875                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000039                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.data       0.013855                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.134586                       # Average percentage of cache occupancy
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+system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::2          202                       # Occupied blocks per task id
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+system.l2c.SCUpgradeReq_accesses::cpu1.data         1446                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2575                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        10307                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data         8026                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            18333                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          134                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker          160                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           13514                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           46458                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       318752                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           66                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           51                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst            4916                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           19762                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        69133                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              472946                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          134                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker          160                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          13514                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          46458                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       318752                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           66                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           51                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst           4916                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          19762                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        69133                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             472946                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.052239                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.006250                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.229022                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.191585                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.060606                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.019608                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.156428                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.120825                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.404471                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.469601                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.805842                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.544668                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.787422                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.905947                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.853981                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.593577                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.689385                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.635521                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.052239                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.006250                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.229022                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.280770                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.060606                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.019608                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.156428                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.351736                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.413428                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.052239                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.006250                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.229022                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.280770                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.060606                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.019608                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.156428                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.351736                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.413428                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 72857.142857                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86781.259774                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 81387.055876                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        82000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        94250                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 91668.400520                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 86197.284908                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 99953.455954                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1045.352652                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2385.826581                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1488.121293                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1322.778403                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1664.051145                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1526.083220                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79314.586466                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73172.363275                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 76397.676251                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 72857.142857                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 86781.259774                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 80415.009890                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        82000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        94250                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 91668.400520                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 75829.439793                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 98549.836086                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 72857.142857                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 86781.259774                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 80415.009890                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        82000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        94250                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 91668.400520                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 75829.439793                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 98549.836086                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -693,183 +722,189 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               67188                       # number of writebacks
-system.l2c.writebacks::total                    67188                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu1.inst             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            4                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         1474                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         3581                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       104062                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst          585                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         4041                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        50971                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          164722                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         7774                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         5401                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        13175                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         1167                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1038                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         2205                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data         4506                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         4295                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total          8801                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker            4                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         1474                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data         8087                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       104062                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          585                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         8336                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        50971                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           173523                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker            4                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         1474                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data         8087                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       104062                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          585                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         8336                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        50971                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          173523                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        82500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       250000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    100663500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    227794750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher   7718948941                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       138750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     42844000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    264712000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   5479054183                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  13834488624                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     78078748                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     54145386                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    132224134                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     11801161                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     10401535                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     22202696                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    273742064                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    254569278                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total    528311342                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        82500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       250000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    100663500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data    501536814                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher   7718948941                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       138750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     42844000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    519281278                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   5479054183                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  14362799966                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        82500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       250000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    100663500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data    501536814                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher   7718948941                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       138750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     42844000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    519281278                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   5479054183                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  14362799966                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    352521750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 156454617998                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5602750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  10840620247                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167653362745                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1361015000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  15491155851                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  16852170851                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    352521750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 157815632998                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5602750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  26331776098                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184505533596                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.017699                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.066667                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.197985                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.190550                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022472                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.107517                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.243771                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.485099                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.686385                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.760919                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.715100                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.911007                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.837772                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.875000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.657235                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.666098                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.661530                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.017699                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.066667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.197985                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.315295                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.022472                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.107517                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.362041                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.491750                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.017699                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.066667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.197985                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.315295                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.022472                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.107517                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.362041                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.491750                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        41250                       # average ReadReq mshr miss latency
+system.l2c.writebacks::writebacks               99890                       # number of writebacks
+system.l2c.writebacks::total                    99890                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadReq MSHR misses
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+system.l2c.ReadReq_mshr_misses::cpu1.inst          769                       # number of ReadReq MSHR misses
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+system.l2c.ReadReq_mshr_misses::total          183878                       # number of ReadReq MSHR misses
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+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4221                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        12779                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          889                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1310                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         2199                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data         6118                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         5533                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         11651                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
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+system.l2c.demand_mshr_misses::total           195529                       # number of demand (read+write) MSHR misses
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+system.l2c.overall_mshr_misses::total          195529                       # number of overall MSHR misses
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+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    104521250                       # number of ReadReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_miss_latency::total  16097880074                       # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     42559203                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    128831216                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      8927886                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     13175305                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     22103191                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    334873814                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total    743645672                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       423500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    230146499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data    886308107                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       278000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        81250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     60929000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    439395064                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   2067966830                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16841525746                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       423500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13155934996                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       278000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        81250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     60929000                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2067966830                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16841525746                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    476853500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4797337250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      9261250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    814340500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6097792500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3540127500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    712608500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4252736000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    476853500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8337464750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      9261250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1526949000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10350528500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.052239                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.006250                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.229022                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.191585                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.060606                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.019608                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.156428                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.120825                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.404471                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.469601                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.805842                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.544668                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.787422                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.905947                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.853981                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.593577                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.689385                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.635521                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.052239                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.006250                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.229022                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.280770                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.060606                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.019608                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.156428                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.351736                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.413428                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.052239                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.006250                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.229022                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.280770                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.060606                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.019608                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.156428                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.351736                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.413428                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        60500                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68292.740841                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63612.049707                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        69375                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73237.606838                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65506.557783                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 83986.890786                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10043.574479                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.066839                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.987400                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10112.391602                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.746628                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.249887                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60750.569019                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59271.077532                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60028.558346                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        41250                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74360.742811                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68948.346665                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        69500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        81250                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79231.469441                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73710.331453                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 87546.525816                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10080.861533                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.729922                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.478676                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.616423                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.484733                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10051.473852                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66814.622099                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60523.009940                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63826.767831                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        60500                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68292.740841                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62017.659701                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        69375                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73237.606838                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62293.819338                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 82771.736116                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        41250                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74360.742811                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67947.570301                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        69500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        81250                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79231.469441                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63213.215940                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 86133.134962                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        60500                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68292.740841                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62017.659701                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        69375                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73237.606838                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62293.819338                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 82771.736116                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74360.742811                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67947.570301                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        69500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        81250                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79231.469441                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63213.215940                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 86133.134962                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -884,158 +919,185 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            1633013                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           1633009                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            769090                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           769090                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           208041                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           61292                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         23072                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          84364                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           39                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           39                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            23321                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           23321                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      2956029                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      2099720                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5055749                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     25795270                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     15582958                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               41378228                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          171942                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           753795                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean                   1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
+system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq             633918                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            633902                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31177                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31177                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           240561                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           96369                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         41588                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         137957                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           77                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           77                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            39943                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           39943                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1258028                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       400059                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1658087                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     37640280                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8288315                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               45928595                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          305065                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1044371                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.034928                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.183598                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 753795    100.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                1007893     96.51%     96.51% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  36478      3.49%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             753795                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2576673570                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            1044371                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1521180751                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2390227339                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1071000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy        2136308825                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1329617427                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         850635338                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq             16716140                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16716140                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8087                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8087                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30962                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8820                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                31019                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31019                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59408                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59440                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq           32                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1044                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          844                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2384390                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     31064064                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     31064064                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                33448454                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        40731                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio        17640                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107964                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180918                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio         2088                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          446                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      2392696                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    124256256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                126648952                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             21726000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162847                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2484103                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4416000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               528000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               503000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy         15532032000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2376303000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         39178496115                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy           326676322                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            84748000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer3.occupancy            36842591                       # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1059,25 +1121,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7131006                       # DTB read hits
-system.cpu0.dtb.read_misses                      3644                       # DTB read misses
-system.cpu0.dtb.write_hits                    6127729                       # DTB write hits
-system.cpu0.dtb.write_misses                      663                       # DTB write misses
-system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1893                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.read_hits                    24353899                       # DTB read hits
+system.cpu0.dtb.read_misses                      6408                       # DTB read misses
+system.cpu0.dtb.write_hits                   18126722                       # DTB write hits
+system.cpu0.dtb.write_misses                     1115                       # DTB write misses
+system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    3404                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   116                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  1442                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7134650                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6128392                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24360307                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18127837                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         13258735                       # DTB hits
-system.cpu0.dtb.misses                           4307                       # DTB misses
-system.cpu0.dtb.accesses                     13263042                       # DTB accesses
+system.cpu0.dtb.hits                         42480621                       # DTB hits
+system.cpu0.dtb.misses                           7523                       # DTB misses
+system.cpu0.dtb.accesses                     42488144                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1099,140 +1161,141 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    31182741                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2176                       # ITB inst misses
+system.cpu0.itb.inst_hits                   115074724                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3350                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1281                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2152                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                31184917                       # ITB inst accesses
-system.cpu0.itb.hits                         31182741                       # DTB hits
-system.cpu0.itb.misses                           2176                       # DTB misses
-system.cpu0.itb.accesses                     31184917                       # DTB accesses
-system.cpu0.numCycles                      5349463018                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               115078074                       # ITB inst accesses
+system.cpu0.itb.hits                        115074724                       # DTB hits
+system.cpu0.itb.misses                           3350                       # DTB misses
+system.cpu0.itb.accesses                    115078074                       # DTB accesses
+system.cpu0.numCycles                      5733858512                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   30507218                       # Number of instructions committed
-system.cpu0.committedOps                     36803230                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             32859018                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5449                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1290775                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      3957686                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    32859018                       # number of integer instructions
-system.cpu0.num_fp_insts                         5449                       # number of float instructions
-system.cpu0.num_int_register_reads           60131579                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          21902535                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4535                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                916                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           133610661                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           14490121                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13795466                       # number of memory refs
-system.cpu0.num_load_insts                    7343231                       # Number of load instructions
-system.cpu0.num_store_insts                   6452235                       # Number of store instructions
-system.cpu0.num_idle_cycles              4898257252.279955                       # Number of idle cycles
-system.cpu0.num_busy_cycles              451205765.720045                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.084346                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.915654                       # Percentage of idle cycles
-system.cpu0.Branches                          5660514                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                16321      0.04%      0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 23591543     62.99%     63.03% # Class of executed instruction
-system.cpu0.op_class::IntMult                   47189      0.13%     63.16% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     63.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              1591      0.00%     63.17% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     63.17% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     63.17% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     63.17% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7343231     19.61%     82.77% # Class of executed instruction
-system.cpu0.op_class::MemWrite                6452235     17.23%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                  111430460                       # Number of instructions committed
+system.cpu0.committedOps                    134719109                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            119427816                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
+system.cpu0.num_func_calls                   12527987                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14980229                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   119427816                       # number of integer instructions
+system.cpu0.num_fp_insts                         9755                       # number of float instructions
+system.cpu0.num_int_register_reads          220379706                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          83050844                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           488414813                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           49991768                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     43590115                       # number of memory refs
+system.cpu0.num_load_insts                   24600281                       # Number of load instructions
+system.cpu0.num_store_insts                  18989834                       # Number of store instructions
+system.cpu0.num_idle_cycles              5477713409.888090                       # Number of idle cycles
+system.cpu0.num_busy_cycles              256145102.111911                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.044672                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.955328                       # Percentage of idle cycles
+system.cpu0.Branches                         28216928                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2272      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 94734127     68.43%     68.43% # Class of executed instruction
+system.cpu0.op_class::IntMult                  104105      0.08%     68.51% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              7381      0.01%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.51% # Class of executed instruction
+system.cpu0.op_class::MemRead                24600281     17.77%     86.28% # Class of executed instruction
+system.cpu0.op_class::MemWrite               18989834     13.72%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  37452110                       # Class of executed instruction
+system.cpu0.op_class::total                 138438000                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   51950                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           369506                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.465010                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           30812705                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           370018                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            83.273530                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10201796750                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.465010                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998955                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998955                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    2074                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements          1061133                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.483144                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          114013070                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1061645                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           107.392838                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      12807152500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.483144                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998991                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998991                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          506                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         62735467                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        62735467                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     30812705                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       30812705                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     30812705                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        30812705                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     30812705                       # number of overall hits
-system.cpu0.icache.overall_hits::total       30812705                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       370019                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       370019                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       370019                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        370019                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       370019                       # number of overall misses
-system.cpu0.icache.overall_misses::total       370019                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   3209345752                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   3209345752                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   3209345752                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   3209345752                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   3209345752                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   3209345752                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     31182724                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     31182724                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     31182724                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     31182724                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     31182724                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     31182724                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011866                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011866                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011866                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011866                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011866                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011866                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8673.462044                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8673.462044                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8673.462044                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8673.462044                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8673.462044                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8673.462044                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        231211102                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       231211102                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    114013070                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      114013070                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    114013070                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       114013070                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    114013070                       # number of overall hits
+system.cpu0.icache.overall_hits::total      114013070                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1061654                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1061654                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1061654                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1061654                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1061654                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1061654                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   9000777256                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   9000777256                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   9000777256                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   9000777256                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   9000777256                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   9000777256                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    115074724                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    115074724                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    115074724                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    115074724                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    115074724                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    115074724                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009226                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.009226                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009226                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.009226                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009226                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.009226                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8478.070309                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8478.070309                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8478.070309                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8478.070309                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8478.070309                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8478.070309                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1241,364 +1304,360 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       370019                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       370019                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       370019                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       370019                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       370019                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       370019                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   2653955748                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   2653955748                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   2653955748                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   2653955748                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   2653955748                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   2653955748                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    531257750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    531257750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    531257750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    531257750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011866                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011866                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011866                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.011866                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011866                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.011866                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7172.485056                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7172.485056                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7172.485056                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  7172.485056                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7172.485056                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  7172.485056                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1061654                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1061654                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1061654                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1061654                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1061654                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1061654                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   7407609744                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   7407609744                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   7407609744                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   7407609744                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   7407609744                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   7407609744                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    719278000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    719278000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    719278000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    719278000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009226                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009226                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009226                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6977.423665                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6977.423665                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6977.423665                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  6977.423665                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6977.423665                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  6977.423665                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified      4129417                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       113341                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      3763718                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          300                       # number of hwpf that were already in the prefetch queue
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified      9923568                       # number of hwpf identified
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       227909                       # number of hwpf that were already in mshr
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      9246862                       # number of hwpf that were already in the cache
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          529                       # number of hwpf that were already in the prefetch queue
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           22                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       252036                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       312183                       # number of hwpf spanning a virtual page
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           49                       # number of hwpf removed because MSHR allocated
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       448219                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       778472                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements          213190                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16168.240053                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs            848978                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          228702                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            3.712158                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      7921739000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  4749.054127                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     3.517230                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.260718                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   821.211493                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1542.145038                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9052.051448                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.289859                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000215                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.050123                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.094125                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.552493                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.986831                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8284                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7219                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         1260                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         1944                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         5080                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         1775                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         1943                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3501                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.505615                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.440613                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        17864213                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       17864213                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         4737                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         2374                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst       361048                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data       184302                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        552461                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       286361                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       286361                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data         5612                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total         5612                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data          831                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total          831                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       133749                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       133749                       # number of ReadExReq hits
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-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         2374                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst       361048                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       318051                       # number of demand (read+write) hits
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-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         2374                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst       361048                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       318051                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total        686210                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          225                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          146                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst         8693                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data        48360                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        57424                       # number of ReadReq misses
-system.cpu0.l2cache.Writeback_misses::writebacks            2                       # number of Writeback misses
-system.cpu0.l2cache.Writeback_misses::total            2                       # number of Writeback misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        18405                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        18405                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        10323                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        10323                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        24100                       # number of ReadExReq misses
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-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          146                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst         8693                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data        72460                       # number of demand (read+write) misses
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-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          225                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          146                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst         8693                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data        72460                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total        81524                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      4897000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3307000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst    300815745                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   1253383203                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   1562402948                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    288253128                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    288253128                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    204026156                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    204026156                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1056000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1056000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data    855610215                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total    855610215                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      4897000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3307000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst    300815745                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   2108993418                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   2418013163                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      4897000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3307000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst    300815745                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   2108993418                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   2418013163                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         4962                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         2520                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.l2cache.ReadReq_accesses::cpu0.data       232662                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       609885                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       286363                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       286363                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        24017                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        24017                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        11154                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        11154                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       157849                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       157849                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         4962                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         2520                       # number of demand (read+write) accesses
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-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         4962                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         2520                       # number of overall (read+write) accesses
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-system.cpu0.l2cache.overall_accesses::cpu0.data       390511                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total       767734                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.045345                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.057937                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.023511                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.207855                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.094155                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000007                       # miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_miss_rate::total     0.000007                       # miss rate for Writeback accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.766332                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.766332                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.925498                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.925498                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.replacements          358131                       # number of replacements
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+system.cpu0.l2cache.tags.total_refs           1936015                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          374364                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            5.171477                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  6748.405331                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     2.298352                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.117074                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   799.968206                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1087.232896                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  7475.818663                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.411890                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000140                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000007                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.048826                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.066359                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.456288                       # Average percentage of cache occupancy
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+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024         8291                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           41                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          127                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         1966                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4890                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          915                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          150                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2895                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4675                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          536                       # Occupied blocks per task id
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+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.506042                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        38026831                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       38026831                       # Number of data accesses
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+system.cpu0.l2cache.ReadReq_hits::total       1428909                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       483936                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       483936                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        10087                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        10087                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2033                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         2033                       # number of SCUpgradeReq hits
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+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         6990                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3189                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1045942                       # number of demand (read+write) hits
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+system.cpu0.l2cache.overall_hits::cpu0.inst      1045942                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       585593                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1641714                       # number of overall hits
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+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        29878                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        29878                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19321                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        19321                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            7                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44921                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        44921                       # number of ReadExReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          263                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          219                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        15712                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       128498                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       144692                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          263                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          219                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        15712                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       128498                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       144692                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      6061000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4899500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst    598206723                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2260687668                       # number of ReadReq miss cycles
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+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    524614292                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    524614292                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    377658880                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    377658880                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1333497                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1333497                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   1506710587                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   1506710587                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      6061000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4899500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst    598206723                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   3767398255                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   4376565478                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      6061000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4899500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst    598206723                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   3767398255                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   4376565478                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         7253                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3408                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1061654                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.data       456365                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total      1528680                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       483936                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       483936                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        39965                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        39965                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21354                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        21354                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       257726                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       257726                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         7253                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         7253                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3408                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1061654                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       714091                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      1786406                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.036261                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.064261                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.014800                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.183136                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.065266                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.747604                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.747604                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.904795                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.904795                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.152678                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.152678                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.045345                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.057937                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.023511                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.185552                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.106188                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.045345                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.057937                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.023511                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.185552                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.106188                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21764.444444                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22650.684932                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 34604.365006                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25917.766811                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27208.187308                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15661.674980                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15661.674980                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19764.230941                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19764.230941                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       528000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       528000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 35502.498548                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35502.498548                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21764.444444                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22650.684932                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34604.365006                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29105.622661                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 29660.138892                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21764.444444                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22650.684932                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34604.365006                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29105.622661                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 29660.138892                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs         1020                       # number of cycles access was blocked
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+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.174298                       # miss rate for ReadExReq accesses
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+system.cpu0.l2cache.overall_miss_rate::total     0.080996                       # miss rate for overall accesses
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17558.547828                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19546.549350                       # average SCUpgradeReq miss latency
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+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33541.341177                       # average ReadExReq miss latency
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+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29318.730681                       # average overall miss latency
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+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29318.730681                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 30247.459970                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs         5815                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs              31                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs              76                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    32.903226                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    76.513158                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       141584                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          141584                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         1192                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          751                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total         1943                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data          493                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total          493                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         1192                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1244                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         2436                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         1192                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1244                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         2436                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          225                       # number of ReadReq MSHR misses
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-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst         7501                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        47609                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        55481                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::writebacks            2                       # number of Writeback MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::total            2                       # number of Writeback MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       252027                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       252027                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        18405                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        18405                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        10323                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        10323                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        23607                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        23607                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          225                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          146                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst         7501                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data        71216                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst         7501                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data        71216                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total       331115                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3322000                       # number of ReadReq MSHR miss cycles
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst    227161754                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data    910924475                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1143693229                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  10450561115                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  10450561115                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    330354697                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    330354697                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    150011322                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    150011322                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       888000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       888000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data    642746273                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total    642746273                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3322000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst    227161754                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   1553670748                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   1786439502                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3322000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2285000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst    227161754                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   1553670748                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  10450561115                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  12237000617                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    478295250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 176453658508                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 176931953758                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   1575154999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   1575154999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    478295250                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 178028813507                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 178507108757                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.045345                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.057937                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.020287                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.204627                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.090970                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000007                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000007                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.writebacks::writebacks       205462                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          205462                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         2206                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         2737                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total         4943                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1219                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         1219                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         2206                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3956                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         6162                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         2206                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3956                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         6162                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          263                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          219                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        13506                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        80840                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        94828                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       448214                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       448214                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        29878                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        29878                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19321                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19321                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43702                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        43702                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          263                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          219                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        13506                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       124542                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       138530                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          263                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          219                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        13506                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       124542                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       448214                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       586744                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4219000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3366500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst    457538021                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   1656533968                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2121657489                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17785493022                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  17785493022                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    490939499                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    490939499                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    261550596                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    261550596                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1060497                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1060497                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1074359119                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1074359119                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      4219000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3366500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst    457538021                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   2730893087                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   3196016608                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      4219000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3366500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst    457538021                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   2730893087                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17785493022                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  20981509630                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    647388500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5328873750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5976262250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3987021005                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3987021005                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    647388500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9315894755                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9963283255                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.036261                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.064261                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.012722                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.177139                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.062033                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.766332                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.766332                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.925498                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.925498                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.747604                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.747604                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.904795                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.904795                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.149554                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.149554                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.045345                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.057937                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.020287                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.182366                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.103015                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.045345                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.057937                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.020287                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.182366                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.169568                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.169568                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.036261                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.064261                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.012722                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.174406                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.077547                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.036261                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.064261                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.012722                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.174406                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.431289                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30284.195974                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 19133.451133                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20614.142301                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41466.037825                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17949.182124                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17949.182124                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14531.756466                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14531.756466                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       444000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       444000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 27226.935782                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27226.935782                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30284.195974                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21816.315828                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22587.996940                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30284.195974                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21816.315828                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36956.950356                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.328449                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 33876.648971                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20491.513706                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22373.744980                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39680.806539                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16431.471283                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16431.471283                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13537.114849                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13537.114849                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 151499.571429                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 151499.571429                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24583.751750                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24583.751750                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33876.648971                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21927.487008                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23070.934873                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33876.648971                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21927.487008                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35759.223154                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1608,104 +1667,106 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           355829                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          496.967445                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11721464                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           356159                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            32.910762                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        767187000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.967445                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970640                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.970640                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          330                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          330                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.644531                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         24668842                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        24668842                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5548461                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5548461                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5771889                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5771889                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        62661                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        62661                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       153118                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       153118                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       152372                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       152372                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11320350                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11320350                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11383011                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11383011                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       178532                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       178532                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       183693                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       183693                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        66756                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total        66756                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10498                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        10498                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        11173                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        11173                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       362225                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        362225                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       428981                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       428981                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2139066005                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   2139066005                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   2832298001                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   2832298001                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    176126000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    176126000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    261398841                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    261398841                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1128000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1128000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   4971364006                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total   4971364006                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   4971364006                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total   4971364006                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5726993                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      5726993                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5955582                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5955582                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       129417                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       129417                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       163616                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       163616                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       163545                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       163545                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     11682575                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     11682575                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11811992                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     11811992                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031174                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.031174                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.030844                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.030844                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.515821                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.515821                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064162                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064162                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.068318                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.068318                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.031006                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.031006                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036317                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.036317                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11981.415124                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11981.415124                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15418.649600                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15418.649600                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16777.100400                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16777.100400                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23395.582297                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23395.582297                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.replacements           658799                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          485.164758                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           41683742                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           659311                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            63.223186                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       1016179000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.164758                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.947587                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.947587                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          315                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           91                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         85573160                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        85573160                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     23155425                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       23155425                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     17431620                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      17431620                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       323179                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       323179                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       358328                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       358328                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       353864                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       353864                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     40587045                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        40587045                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     40910224                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       40910224                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       360428                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       360428                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       297691                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       297691                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       106192                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       106192                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21416                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21416                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21370                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        21370                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       658119                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        658119                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       764311                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       764311                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   4473033768                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   4473033768                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4445222415                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   4445222415                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    335592501                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    335592501                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    473344116                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    473344116                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1450500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1450500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8918256183                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   8918256183                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8918256183                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   8918256183                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     23515853                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     23515853                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     17729311                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17729311                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       429371                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       429371                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       379744                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       379744                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       375234                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       375234                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     41245164                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     41245164                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     41674535                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     41674535                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.015327                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.015327                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016791                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.016791                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.247320                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.247320                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056396                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056396                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056951                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056951                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.015956                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.015956                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018340                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.018340                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12410.339286                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12410.339286                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14932.337273                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 14932.337273                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15670.176550                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15670.176550                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22149.935236                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22149.935236                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13724.519307                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13724.519307                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11588.774342                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11588.774342                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13551.130089                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13551.130089                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11668.360370                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 11668.360370                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1714,82 +1775,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       286365                       # number of writebacks
-system.cpu0.dcache.writebacks::total           286365                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         3418                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total         3418                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         2438                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total         2438                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data         5856                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total         5856                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data         5856                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total         5856                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       175114                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       175114                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       181255                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       181255                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        47050                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        47050                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        10498                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        10498                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        11156                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        11156                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       356369                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       356369                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       403419                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       403419                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   1737360745                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   1737360745                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   2335118999                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2335118999                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    699675494                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    699675494                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    155125000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    155125000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    237977159                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    237977159                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1080000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1080000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   4072479744                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   4072479744                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   4772155238                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   4772155238                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 185341734990                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 185341734990                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1669232496                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1669232496                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 187010967486                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 187010967486                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030577                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030577                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.030434                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.030434                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.363553                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.363553                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064162                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064162                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.068214                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.068214                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.030504                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.030504                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.034153                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.034153                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data  9921.312659                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total  9921.312659                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12883.059772                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12883.059772                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14870.892540                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14870.892540                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14776.624119                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14776.624119                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21331.763984                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21331.763984                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       483937                       # number of writebacks
+system.cpu0.dcache.writebacks::total           483937                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         7364                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total         7364                       # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15075                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15075                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data         7364                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total         7364                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data         7364                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total         7364                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       353064                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       353064                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       297691                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       297691                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        96960                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        96960                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6341                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6341                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21361                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        21361                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       650755                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       650755                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       747715                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       747715                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3674066732                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3674066732                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   3839615585                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3839615585                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1190903244                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1190903244                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     89864249                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     89864249                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    429815884                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    429815884                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1372500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1372500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7513682317                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7513682317                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8704585561                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   8704585561                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5564939750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5564939750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4183945995                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4183945995                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   9748885745                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   9748885745                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015014                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015014                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016791                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.016791                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225819                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225819                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016698                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016698                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056927                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056927                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015778                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015778                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.017942                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.017942                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10406.234371                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10406.234371                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12897.990148                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12897.990148                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12282.417946                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12282.417946                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14171.936445                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14171.936445                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20121.524460                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20121.524460                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11427.704834                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11427.704834                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11829.277347                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11829.277347                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11546.100018                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11546.100018                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11641.582101                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11641.582101                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1797,56 +1858,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       1907557                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1767698                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        12543                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        12543                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       286363                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       331583                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        53089                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        23925                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp        60027                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           17                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           39                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       171374                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       163301                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side       753056                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      3449820                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         6852                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        13348                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          4223076                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     23690016                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     48159078                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        19848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total          71879022                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     631972                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      1656253                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.339000                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.473370                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq       1734717                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1628862                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        26256                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        26256                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       483936                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       598763                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        81012                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43653                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       101651                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           77                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       279403                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       269117                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2141354                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2250253                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         9809                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        20976                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          4422392                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     67981948                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80932636                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        29012                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         148957228                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     991588                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      3219253                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.272771                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.445384                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5           1094784     66.10%     66.10% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6            561469     33.90%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5           2341135     72.72%     72.72% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6            878118     27.28%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       1656253                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    1405252745                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3219253                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    1700320883                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy     72604500                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    115643997                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy    563408502                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1726182117                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      4332000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1603955756                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy   1150860061                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy      6401000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy      8386000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     13723500                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -1871,25 +1933,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     6599972                       # DTB read hits
-system.cpu1.dtb.read_misses                      3720                       # DTB read misses
-system.cpu1.dtb.write_hits                    5539858                       # DTB write hits
-system.cpu1.dtb.write_misses                     1581                       # DTB write misses
-system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1672                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.read_hits                     4827395                       # DTB read hits
+system.cpu1.dtb.read_misses                      2744                       # DTB read misses
+system.cpu1.dtb.write_hits                    4131070                       # DTB write hits
+system.cpu1.dtb.write_misses                      524                       # DTB write misses
+system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    2012                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   123                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   437                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 6603692                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5541439                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 4830139                       # DTB read accesses
+system.cpu1.dtb.write_accesses                4131594                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         12139830                       # DTB hits
-system.cpu1.dtb.misses                           5301                       # DTB misses
-system.cpu1.dtb.accesses                     12145131                       # DTB accesses
+system.cpu1.dtb.hits                          8958465                       # DTB hits
+system.cpu1.dtb.misses                           3268                       # DTB misses
+system.cpu1.dtb.accesses                      8961733                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1911,142 +1973,141 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    32728613                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2200                       # ITB inst misses
+system.cpu1.itb.inst_hits                    20889672                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1747                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1176                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    1149                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                32730813                       # ITB inst accesses
-system.cpu1.itb.hits                         32728613                       # DTB hits
-system.cpu1.itb.misses                           2200                       # DTB misses
-system.cpu1.itb.accesses                     32730813                       # DTB accesses
-system.cpu1.numCycles                      5350361558                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                20891419                       # ITB inst accesses
+system.cpu1.itb.hits                         20889672                       # DTB hits
+system.cpu1.itb.misses                           1747                       # DTB misses
+system.cpu1.itb.accesses                     20891419                       # DTB accesses
+system.cpu1.numCycles                      5732950771                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   32086754                       # Number of instructions committed
-system.cpu1.committedOps                     37934299                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             33961237                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  4436                       # Number of float alu accesses
-system.cpu1.num_func_calls                     973285                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3888456                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    33961237                       # number of integer instructions
-system.cpu1.num_fp_insts                         4436                       # number of float instructions
-system.cpu1.num_int_register_reads           60527961                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          22681940                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3022                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1416                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           134686779                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           15567897                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     12531559                       # number of memory refs
-system.cpu1.num_load_insts                    6744563                       # Number of load instructions
-system.cpu1.num_store_insts                   5786996                       # Number of store instructions
-system.cpu1.num_idle_cycles              5182201093.372063                       # Number of idle cycles
-system.cpu1.num_busy_cycles              168160464.627937                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031430                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968570                       # Percentage of idle cycles
-system.cpu1.Branches                          5094014                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                12501      0.03%      0.03% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 25826807     67.22%     67.25% # Class of executed instruction
-system.cpu1.op_class::IntMult                   50699      0.13%     67.38% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc               745      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.38% # Class of executed instruction
-system.cpu1.op_class::MemRead                 6744563     17.55%     84.94% # Class of executed instruction
-system.cpu1.op_class::MemWrite                5786996     15.06%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   20508829                       # Number of instructions committed
+system.cpu1.committedOps                     24874782                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             22190598                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1209607                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2572400                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    22190598                       # number of integer instructions
+system.cpu1.num_fp_insts                         1792                       # number of float instructions
+system.cpu1.num_int_register_reads           39855869                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          15449003                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            90462747                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            8862782                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      9247846                       # number of memory refs
+system.cpu1.num_load_insts                    4946569                       # Number of load instructions
+system.cpu1.num_store_insts                   4301277                       # Number of store instructions
+system.cpu1.num_idle_cycles              5671538888.273010                       # Number of idle cycles
+system.cpu1.num_busy_cycles              61411882.726990                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.010712                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.989288                       # Percentage of idle cycles
+system.cpu1.Branches                          3892747                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                   67      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 16017837     63.30%     63.30% # Class of executed instruction
+system.cpu1.op_class::IntMult                   33571      0.13%     63.44% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              4039      0.02%     63.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.45% # Class of executed instruction
+system.cpu1.op_class::MemRead                 4946569     19.55%     83.00% # Class of executed instruction
+system.cpu1.op_class::MemWrite                4301277     17.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  38422311                       # Class of executed instruction
+system.cpu1.op_class::total                  25303360                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   40934                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements           375227                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.528279                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           32352870                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           375739                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            86.104636                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      79843888000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.528279                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973688                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973688                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                    2751                       # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements           565233                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.685358                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           20323921                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           565745                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            35.924173                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     115078716000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.685358                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973995                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.973995                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          400                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3          109                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         65832957                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        65832957                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     32352870                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       32352870                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     32352870                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        32352870                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     32352870                       # number of overall hits
-system.cpu1.icache.overall_hits::total       32352870                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       375739                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       375739                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       375739                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        375739                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       375739                       # number of overall misses
-system.cpu1.icache.overall_misses::total       375739                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3159151510                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   3159151510                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   3159151510                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   3159151510                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   3159151510                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   3159151510                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     32728609                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     32728609                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     32728609                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     32728609                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     32728609                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     32728609                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011480                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.011480                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011480                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.011480                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011480                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.011480                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8407.834987                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8407.834987                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8407.834987                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8407.834987                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8407.834987                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8407.834987                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         42345080                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        42345080                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     20323921                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       20323921                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     20323921                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        20323921                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     20323921                       # number of overall hits
+system.cpu1.icache.overall_hits::total       20323921                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       565746                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       565746                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       565746                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        565746                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       565746                       # number of overall misses
+system.cpu1.icache.overall_misses::total       565746                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4684636281                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4684636281                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4684636281                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4684636281                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4684636281                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4684636281                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     20889667                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     20889667                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     20889667                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     20889667                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     20889667                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     20889667                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.027083                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.027083                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.027083                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.027083                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.027083                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.027083                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8280.458511                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8280.458511                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8280.458511                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8280.458511                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8280.458511                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8280.458511                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2055,361 +2116,356 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       375739                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       375739                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       375739                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       375739                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       375739                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       375739                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2595414990                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   2595414990                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2595414990                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   2595414990                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2595414990                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   2595414990                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8511750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8511750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8511750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8511750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011480                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011480                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011480                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.011480                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011480                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.011480                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6907.494271                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6907.494271                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6907.494271                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  6907.494271                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6907.494271                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  6907.494271                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       565746                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       565746                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       565746                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       565746                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       565746                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       565746                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3835844219                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3835844219                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3835844219                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3835844219                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3835844219                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3835844219                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14025750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14025750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14025750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     14025750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027083                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027083                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027083                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.027083                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027083                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.027083                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6780.152611                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6780.152611                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6780.152611                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  6780.152611                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6780.152611                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  6780.152611                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      3539349                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       109722                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      3291325                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          217                       # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      4613211                       # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        23452                       # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      4471751                       # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          253                       # number of hwpf that were already in the prefetch queue
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           15                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       138070                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       329563                       # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           21                       # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       117734                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       522133                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements          122650                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15477.303394                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            769651                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs          138796                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            5.545196                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    2606454315500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5482.269126                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    12.040765                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.187836                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   603.787912                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2723.851785                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6655.165971                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.334611                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000735                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000011                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.036852                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.166251                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.406199                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.944660                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         7087                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.replacements           85099                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15602.150946                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs            830949                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs          100297                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            8.284884                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    2855978416500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  4730.109881                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     5.755019                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.314200                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   871.040386                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1529.848587                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  8465.082873                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.288703                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000351                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000019                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.053164                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.093375                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.516668                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.952280                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9308                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         9051                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           22                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           39                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          481                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         4215                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         2330                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1744                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5747                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1414                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.432556                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5882                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           64                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         1130                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         8114                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1134                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4474                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.568115                       # Percentage of cache occupancy per task id
 system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.552429                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        16022455                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       16022455                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         6174                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2268                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst       369218                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data       169436                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        547096                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       225255                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       225255                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1340                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1340                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          885                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total          885                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        86607                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        86607                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         6174                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2268                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       369218                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       256043                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         633703                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         6174                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2268                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       369218                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       256043                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        633703                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          268                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          169                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst         6377                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data        56923                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        63737                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        20417                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        20417                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        12784                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        12784                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
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-system.cpu1.l2cache.ReadExReq_misses::total        23524                       # number of ReadExReq misses
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-system.cpu1.l2cache.UpgradeReq_miss_latency::total    341145571                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    259918262                       # number of SCUpgradeReq miss cycles
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-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      5694000                       # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      5694000                       # number of overall miss cycles
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-system.cpu1.l2cache.Writeback_accesses::writebacks       225255                       # number of Writeback accesses(hits+misses)
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-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        21757                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.041602                       # miss rate for ReadReq accesses
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-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.016978                       # miss rate for ReadReq accesses
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-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.938411                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.938411                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.935255                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.935255                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.359009                       # Percentage of cache occupancy per task id
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.103274                       # miss rate for ReadReq accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.009897                       # miss rate for ReadReq accesses
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+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.950585                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.950585                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.961719                       # miss rate for SCUpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.213600                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.213600                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.041602                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.069348                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.016978                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.239077                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.121034                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.041602                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.069348                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.016978                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.239077                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.121034                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21246.268657                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19934.911243                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29968.165281                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 25701.200622                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 26094.096569                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16708.898026                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16708.898026                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20331.528630                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20331.528630                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 239499.500000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 239499.500000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37960.214802                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37960.214802                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21246.268657                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19934.911243                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29968.165281                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29285.934044                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 29292.989148                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21246.268657                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19934.911243                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29968.165281                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29285.934044                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 29292.989148                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          579                       # number of cycles access was blocked
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+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.142352                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.009897                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.389742                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.131387                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.103274                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.142352                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.009897                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.389742                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.131387                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20932.276657                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.326241                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34171.542954                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22040.114059                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22915.800287                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18249.290874                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18249.290874                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19546.098952                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.098952                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       565500                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       565500                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 32075.682925                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 32075.682925                       # average ReadExReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20932.276657                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.326241                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34171.542954                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25279.047333                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 25704.767053                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20932.276657                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.326241                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34171.542954                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25279.047333                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 25704.767053                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs         1025                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs              19                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs              35                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    30.473684                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    29.285714                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        66455                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           66455                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          767                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           80                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          847                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1344                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         1344                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst          767                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1424                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         2191                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst          767                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1424                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         2191                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          268                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          169                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst         5610                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        56843                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        62890                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       138069                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       138069                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        20417                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        20417                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        12784                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        12784                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        22180                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        22180                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          268                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          169                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         5610                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data        79023                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total        85070                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          268                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          169                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         5610                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data        79023                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       138069                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       223139                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      3817500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      2186000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    137414260                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1062900207                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1206317967                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   7048181570                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   7048181570                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    332046976                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    332046976                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    180785968                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    180785968                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       373999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       373999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    591403879                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    591403879                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      3817500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      2186000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    137414260                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   1654304086                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   1797721846                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      3817500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      2186000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    137414260                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   1654304086                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   7048181570                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   8845903416                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7648750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data  12231230753                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total  12238879503                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data  28539732155                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total  28539732155                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7648750                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data  40770962908                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total  40778611658                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.041602                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.069348                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.014936                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.251119                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.102958                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.writebacks::writebacks        35099                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           35099                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          685                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.ReadExReq_mshr_hits::total          214                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst          685                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          310                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          995                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst          685                       # number of overall MSHR hits
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+system.cpu1.l2cache.overall_mshr_hits::total          995                       # number of overall MSHR hits
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+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       117733                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       117733                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29432                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29432                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22334                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22334                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33286                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        33286                       # number of ReadExReq MSHR misses
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+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103487                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         4914                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103487                       # number of overall MSHR misses
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+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4833500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3713250                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    143751774                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1055636432                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1207934956                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3298666709                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3298666709                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    431077198                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    431077198                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    306544179                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    306544179                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1430500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1430500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    820609092                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    820609092                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4833500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3713250                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    143751774                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   1876245524                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   2028544048                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4833500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3713250                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    143751774                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   1876245524                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   3298666709                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   5327210757                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12612250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    916010500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    928622750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    796474001                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    796474001                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12612250                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1712484501                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1725096751                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.103274                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.142352                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.008686                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.362736                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.099061                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.938411                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.938411                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.935255                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.935255                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.950585                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.950585                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.961719                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.961719                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.201397                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.201397                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.041602                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.069348                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.014936                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234845                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.117995                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.041602                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.069348                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.014936                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234845                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.457288                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.457288                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.103274                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.142352                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.008686                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.388578                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.130199                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.103274                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.142352                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.008686                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.388578                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.309501                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24494.520499                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 18698.875974                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 19181.395564                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51048.255365                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16263.259832                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16263.259832                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14141.580726                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14141.580726                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186999.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186999.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 26663.835843                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26663.835843                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24494.520499                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20934.463207                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21132.265734                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24494.520499                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20934.463207                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39643.018101                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.270791                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29253.515263                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15037.341804                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15947.599229                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28018.199732                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14646.547907                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14646.547907                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13725.449046                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13725.449046                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 476833.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 476833.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24653.280418                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24653.280418                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29253.515263                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18130.253307                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18605.375108                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29253.515263                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18130.253307                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23492.416122                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2419,106 +2475,105 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           313601                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          474.302028                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           10949850                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           314113                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            34.859589                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      76456711000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   474.302028                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.926371                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.926371                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          287                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          105                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         22948274                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        22948274                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      6183420                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        6183420                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4558750                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4558750                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        19290                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        19290                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        77402                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        77402                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        75753                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        75753                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     10742170                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        10742170                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     10761460                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       10761460                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       187243                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       187243                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       134937                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       134937                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        43327                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        43327                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        12089                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        12089                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        13673                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        13673                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       322180                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        322180                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       365507                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       365507                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2299329756                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2299329756                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2509975628                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2509975628                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    218034000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    218034000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    317344970                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    317344970                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       524000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       524000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   4809305384                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   4809305384                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   4809305384                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   4809305384                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      6370663                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      6370663                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4693687                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4693687                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        62617                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        62617                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        89491                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        89491                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        89426                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        89426                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     11064350                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     11064350                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     11126967                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     11126967                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.029391                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.029391                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028749                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.028749                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.691937                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.691937                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.135086                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.135086                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.152897                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.152897                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029119                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.029119                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.032849                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.032849                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12279.923714                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12279.923714                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18601.092569                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18601.092569                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18035.734966                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18035.734966                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23209.607987                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23209.607987                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.replacements           218932                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          479.958616                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            8645395                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           219287                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            39.425023                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     104115576500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   479.958616                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.937419                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.937419                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          355                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          298                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           57                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.693359                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         18161929                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        18161929                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      4463105                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        4463105                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      3919326                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       3919326                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        64192                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        64192                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        87200                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        87200                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79632                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        79632                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      8382431                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         8382431                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      8446623                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        8446623                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       155171                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       155171                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       103752                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       103752                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        34196                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        34196                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17931                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17931                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23276                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23276                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       258923                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        258923                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       293119                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       293119                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2220270266                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2220270266                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2272762314                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2272762314                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    325809000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    325809000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    538454705                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    538454705                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1810500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1810500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   4493032580                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   4493032580                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   4493032580                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   4493032580                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      4618276                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      4618276                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4023078                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4023078                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        98388                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        98388                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105131                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       105131                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102908                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       102908                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      8641354                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      8641354                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      8739742                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      8739742                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.033599                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.033599                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.025789                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.025789                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.347563                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.347563                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.170559                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.170559                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.226183                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.226183                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029963                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.029963                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033539                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.033539                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14308.538748                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14308.538748                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21905.720507                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21905.720507                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18170.152250                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18170.152250                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23133.472461                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23133.472461                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14927.386504                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14927.386504                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13157.902267                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 13157.902267                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17352.775072                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17352.775072                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15328.356674                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15328.356674                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2527,82 +2582,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       225255                       # number of writebacks
-system.cpu1.dcache.writebacks::total           225255                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          794                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          794                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data         3242                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total         3242                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data         4036                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total         4036                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data         4036                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total         4036                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       186449                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       186449                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       131695                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       131695                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        27821                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        27821                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12089                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12089                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        13671                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        13671                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       318144                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       318144                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       345965                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       345965                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1916001744                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1916001744                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2027549872                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2027549872                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    596503999                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    596503999                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    193851000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    193851000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    289002030                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    289002030                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       494000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       494000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3943551616                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3943551616                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4540055615                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4540055615                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  12848996742                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total  12848996742                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  34213847345                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  34213847345                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data  47062844087                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total  47062844087                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.029267                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.029267                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028058                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028058                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.444304                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.444304                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.135086                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.135086                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.152875                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.152875                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028754                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028754                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031092                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031092                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10276.277931                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10276.277931                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15395.799932                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15395.799932                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21440.782107                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21440.782107                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16035.321367                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16035.321367                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21139.787141                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21139.787141                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       134926                       # number of writebacks
+system.cpu1.dcache.writebacks::total           134926                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          299                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          299                       # number of ReadReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12328                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12328                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          299                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          299                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          299                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          299                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       154872                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       154872                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       103752                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       103752                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33057                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        33057                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5603                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5603                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23226                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23226                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       258624                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       258624                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       291681                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       291681                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1901749734                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1901749734                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2059007686                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2059007686                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    496678249                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    496678249                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     84335500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     84335500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    490783295                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    490783295                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1734500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1734500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3960757420                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   3960757420                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4457435669                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4457435669                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    961034499                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    961034499                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    833382499                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    833382499                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1794416998                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1794416998                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033535                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033535                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025789                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025789                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.335986                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.335986                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.053295                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.053295                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225697                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225697                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029929                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.029929                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033374                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033374                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12279.493608                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12279.493608                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19845.474651                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19845.474651                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15024.903924                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15024.903924                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15051.847225                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15051.847225                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21130.771334                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21130.771334                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12395.492657                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12395.492657                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13122.875479                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13122.875479                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15314.732662                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15314.732662                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15281.885584                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15281.885584                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2610,81 +2665,146 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq        957719                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       715905                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq       756547                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp       756547                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       225255                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       189199                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        53977                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        23970                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        50977                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           26                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           39                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq       119927                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp       111476                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side       751552                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      2675268                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6827                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        16819                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          3450466                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     24038516                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     40612602                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         9748                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        25768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          64686634                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     549743                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1492746                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.338347                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.473147                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq       1206103                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       816776                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         4921                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         4921                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       134926                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       169865                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        86284                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42512                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        89712                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           42                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           77                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        91056                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        78188                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1131848                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       880488                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5306                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9281                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2026923                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     36208456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     28775795                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7924                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          65005615                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     818131                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1761210                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.414931                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.492710                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5            987680     66.17%     66.17% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6            505066     33.83%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5           1030430     58.51%     58.51% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6            730780     41.49%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1492746                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1514414783                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     42402999                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1761210                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy     658102724                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     89600499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    563804260                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    848922781                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    984220768                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    438669538                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      4390000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      3325250                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     10377250                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy      5921500                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                    0                       # number of replacements
-system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
+system.iocache.tags.replacements                36443                       # number of replacements
+system.iocache.tags.tagsinuse               14.446814                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
-system.iocache.tags.data_accesses                   0                       # Number of data accesses
+system.iocache.tags.sampled_refs                36459                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         277160524000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.446814                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.902926                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.902926                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               328549                       # Number of tag accesses
+system.iocache.tags.data_accesses              328549                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide          253                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              253                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide           32                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total           32                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ide          253                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               253                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          253                       # number of overall misses
+system.iocache.overall_misses::total              253                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     31609377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31609377                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31609377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31609377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31609377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31609377                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          253                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            253                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36256                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36256                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide          253                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             253                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          253                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            253                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000883                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total     0.000883                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124938.249012                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124938.249012                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124938.249012                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124938.249012                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124938.249012                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      36224                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1782387791115                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1782387791115                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1782387791115                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1782387791115                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide          253                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          253                       # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          253                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          253                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          253                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          253                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18452377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18452377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2247085536                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2247085536                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18452377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18452377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18452377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18452377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72934.296443                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72934.296443                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
index 69edb0827..cc9c3e898 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 2c07f27f5..f074dc56c 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
 have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.vram system.realview.nvmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -53,14 +53,14 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
 
 [system.bridge]
 type=Bridge
 clk_domain=system.clk_domain
 delay=50000
 eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -274,6 +274,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -340,7 +341,7 @@ tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
 
 [system.cpu.l2cache.tags]
 type=LRU
@@ -394,15 +395,16 @@ type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
-use_default_range=false
+use_default_range=true
 width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
 type=BaseCache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
 eventq_index=0
@@ -421,8 +423,8 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
 type=LRU
@@ -445,8 +447,8 @@ system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -502,6 +504,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
@@ -511,7 +514,7 @@ mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
 page_policy=open_adaptive
-range=0:134217727
+range=2147483648:2415919103
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -540,46 +543,37 @@ tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
 write_low_thresh_perc=50
-port=system.membus.master[6]
+port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
 pci_cfg_gen_offsets=false
 pci_io_base=0
 system=system
 
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
 pio_latency=100000
 system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
 
 [system.realview.cf_ctrl]
 type=IdeController
-BAR0=402653184
+BAR0=471465984
 BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
 BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
 BAR2=1
 BAR2LegacyIO=false
 BAR2Size=8
@@ -649,18 +643,18 @@ VendorID=32902
 clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
-disks=system.cf0
+disks=
 eventq_index=0
-io_shift=1
+io_shift=2
 pci_bus=2
-pci_dev=7
+pci_dev=0
 pci_func=0
 pio_latency=30000
 platform=system.realview
 system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.clcd]
 type=Pl111
@@ -669,8 +663,8 @@ clk_domain=system.clk_domain
 enable_capture=true
 eventq_index=0
 gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
 pio_latency=10000
 pixel_clock=41667
 system=system
@@ -678,51 +672,129 @@ vnc=system.vncserver
 dma=system.iobus.slave[1]
 pio=system.iobus.master[4]
 
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
 clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
 eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
 pio_latency=100000
 system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
 
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
 clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
 eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
 system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
 pio=system.iobus.master[25]
 
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
 eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
 system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
 clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
 cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
@@ -732,38 +804,111 @@ platform=system.realview
 system=system
 pio=system.membus.master[2]
 
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
 clk_domain=system.clk_domain
+enable_capture=true
 eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
 system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
 
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
 clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
 eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
 system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
 
 [system.realview.kmi0]
 type=Pl050
@@ -772,13 +917,13 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=52
+int_num=44
 is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.kmi1]
 type=Pl050
@@ -787,20 +932,20 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=53
+int_num=45
 is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.l2x0_fake]
 type=IsaFake
 clk_domain=system.clk_domain
 eventq_index=0
 fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
 pio_latency=100000
 pio_size=4095
 ret_bad_addr=false
@@ -811,7 +956,25 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
@@ -820,10 +983,10 @@ eventq_index=0
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -831,10 +994,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
 pio_latency=100000
 system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
 
 [system.realview.nvmem]
 type=SimpleMemory
@@ -846,18 +1009,30 @@ in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=2147483648:2214592511
+range=0:67108863
 port=system.membus.master[1]
 
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
 [system.realview.realview_io]
 type=RealViewCtrl
 clk_domain=system.clk_domain
 eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
 pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
 system=system
 pio=system.iobus.master[1]
 
@@ -868,34 +1043,12 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
 pio_latency=100000
 system=system
 time=Thu Jan  1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -903,21 +1056,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
 pio_latency=100000
 system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
 
 [system.realview.timer0]
 type=Sp804
@@ -927,9 +1069,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
 pio_latency=100000
 system=system
 pio=system.iobus.master[2]
@@ -942,9 +1084,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
 pio_latency=100000
 system=system
 pio=system.iobus.master[3]
@@ -956,8 +1098,8 @@ end_on_eot=false
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
 pio_latency=100000
 platform=system.realview
 system=system
@@ -970,10 +1112,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
 pio_latency=100000
 system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -981,10 +1123,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
 pio_latency=100000
 system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -992,10 +1134,54 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
 pio_latency=100000
 system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -1003,10 +1189,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
 pio_latency=100000
 system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
 
 [system.terminal]
 type=Terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
index 9dee17aa2..dd544abce 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
@@ -1,13 +1,33 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index a3076394e..7ca64b9c1 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,14 +1,31 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:08:28
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 15:58:15
 gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
-      0: system.cpu.isa: ISA system set to: 0x6b2c800 0x6b2c800
-info: Using bootloader at address 0x80000000
-info: Using kernel entry physical address at 0x8000
+info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+      0: system.cpu.isa: ISA system set to: 0x56b5b00 0x56b5b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2616536483000 because m5_exit instruction encountered
+info: Read CNTFREQ_EL0 frequency
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+Exiting @ tick 2902619131000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index a50c29900..f83b43588 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,134 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.614572                       # Number of seconds simulated
-sim_ticks                                2614571564500                       # Number of ticks simulated
-final_tick                               2614571564500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.902619                       # Number of seconds simulated
+sim_ticks                                2902619131000                       # Number of ticks simulated
+final_tick                               2902619131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 393660                       # Simulator instruction rate (inst/s)
-host_op_rate                                   470163                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            17100811132                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 408168                       # Number of bytes of host memory used
-host_seconds                                   152.89                       # Real time elapsed on the host
-sim_insts                                    60187274                       # Number of instructions simulated
-sim_ops                                      71883961                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 744858                       # Simulator instruction rate (inst/s)
+host_op_rate                                   898074                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            19216925045                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 553548                       # Number of bytes of host memory used
+host_seconds                                   151.05                       # Real time elapsed on the host
+sim_insts                                   112506996                       # Number of instructions simulated
+sim_ops                                     135649573                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            704648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9109336                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132497824                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       704648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          704648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3720832                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6736904                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst           1190564                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9003364                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10195464                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1190564                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1190564                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5259520                       # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7595380                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17222                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142359                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15495012                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           58138                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               812156                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46922943                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            122                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               269508                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3484065                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50676687                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          269508                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             269508                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1423113                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1153563                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2576676                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1423113                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46922943                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           122                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              269508                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4637627                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53253363                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15495012                       # Number of read requests accepted
-system.physmem.writeReqs                       812156                       # Number of write requests accepted
-system.physmem.readBursts                    15495012                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     812156                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                991563904                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    116864                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6748800                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 132497824                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6736904                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1826                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  706685                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4511                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              968097                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              967810                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              967673                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              967915                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              974446                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              968066                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              967653                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              967482                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              968460                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              968209                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             967967                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             967960                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             967930                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             967880                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             967953                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             967685                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6670                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6386                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6320                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6360                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6634                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6864                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6659                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6574                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7028                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6769                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6571                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6645                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6565                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6383                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6560                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6462                       # Per bank write bursts
+system.physmem.num_reads::cpu.inst              27056                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141197                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                168277                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           82180                       # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               122785                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide              331                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               410169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3101807                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3512505                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          410169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             410169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1811991                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide          798705                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6037                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2616733                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1811991                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide          799036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              410169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3107844                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6129238                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        168277                       # Number of read requests accepted
+system.physmem.writeReqs                       122785                       # Number of write requests accepted
+system.physmem.readBursts                      168277                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     122785                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10758080                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     11648                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7609472                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10195464                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7595380                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      182                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3868                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4505                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9709                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9253                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10215                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10266                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18988                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10225                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10580                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10353                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9698                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                9938                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9924                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8855                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9985                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10410                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9933                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9763                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7210                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6831                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8029                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7890                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7400                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7418                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7750                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7625                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7363                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7566                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7503                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6751                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7436                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7741                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7101                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2614567301000                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2902618699500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                    6644                       # Read request sizes (log2)
-system.physmem.readPktSize::3                15335434                       # Read request sizes (log2)
+system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
+system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  152934                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  158705                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
+system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  58138                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1126447                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    970731                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    976234                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1093523                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    987097                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1054685                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2721121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2624601                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3412795                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    139881                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                   116829                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                   107818                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                   104436                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19578                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    18770                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18545                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       95                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 118404                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    167256                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       571                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       256                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -159,313 +162,360 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3703                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1027284                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      971.798163                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     905.747967                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     203.998959                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22800      2.22%      2.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22532      2.19%      4.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8422      0.82%      5.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2556      0.25%      5.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2545      0.25%      5.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1785      0.17%      5.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8607      0.84%      6.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          981      0.10%      6.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       957056     93.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1027284                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6124                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2529.911822                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    116281.505657                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287         6119     99.92%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-1.04858e+06            3      0.05%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6124                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6124                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.219138                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.190607                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.983110                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2397     39.14%     39.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 24      0.39%     39.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3669     59.91%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 32      0.52%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6124                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   400730693500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              691227931000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  77465930000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25864.96                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2070                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6016                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6817                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7034                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8864                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6957                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6255                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6074                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        58554                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      313.684599                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     183.647731                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.576547                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21465     36.66%     36.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14645     25.01%     61.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5517      9.42%     71.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3471      5.93%     77.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2275      3.89%     80.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1576      2.69%     83.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1002      1.71%     85.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1065      1.82%     87.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7538     12.87%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          58554                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5863                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.669452                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      558.899894                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5861     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5863                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5863                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.279379                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.638132                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.466375                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5064     86.37%     86.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              42      0.72%     87.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              33      0.56%     87.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             216      3.68%     91.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             215      3.67%     95.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              12      0.20%     95.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              16      0.27%     95.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               7      0.12%     95.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              25      0.43%     96.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               3      0.05%     96.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.10%     96.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               4      0.07%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             164      2.80%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.07%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.05%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               2      0.03%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              13      0.22%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.03%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               5      0.09%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             3      0.05%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             3      0.05%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.03%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.14%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             3      0.05%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5863                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1491787750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4643569000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    840475000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8874.67                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44614.96                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         379.25                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.58                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       50.68                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.58                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27624.67                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.71                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.62                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.62                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.98                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.96                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         6.80                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        28.13                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14482679                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     88673                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  84.07                       # Row buffer hit rate for writes
-system.physmem.avgGap                       160332.39                       # Average gap between requests
-system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2239359524750                       # Time in different power states
-system.physmem.memoryStateTime::REF       87306180000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        27.72                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     138438                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     90000                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.36                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9972509.98                       # Average gap between requests
+system.physmem.pageHitRate                      79.59                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2755208941000                       # Time in different power states
+system.physmem.memoryStateTime::REF       96924620000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      287902801500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       50485479500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                3884796720                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                3881470320                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                2119680750                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                2117865750                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0              60443307600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1              60403543200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               339986160                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               343329840                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          170770888080                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          170770888080                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          155970246555                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          156681731385                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1431925089750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1431300980250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1825453995615                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1825499808825                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             698.185571                       # Core power per rank (mW)
-system.physmem.averagePower::1             698.203093                       # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.physmem.actEnergy::0                 226724400                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 215943840                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 123708750                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 117826500                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                698794200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                612339000                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               389791440                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               380667600                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          189584556720                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          189584556720                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           86731413750                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           85564066005                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1665487627500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1666511616750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1943242616760                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1942987016415                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.480430                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.392372                       # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu.inst           24                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            24                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           24                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           24                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            6                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              6                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq            16546657                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16546657                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763381                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763381                       # Transaction distribution
-system.membus.trans_dist::Writeback             58138                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4511                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4511                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            132459                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           132459                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383082                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3840                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1894372                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4281306                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30670848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     30670848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34952154                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390530                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7680                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16551336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18949570                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               141632962                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            215583                       # Request fanout histogram
+system.membus.trans_dist::ReadReq               70650                       # Transaction distribution
+system.membus.trans_dist::ReadResp              70650                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27618                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27618                       # Transaction distribution
+system.membus.trans_dist::Writeback             82180                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4503                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4505                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            128451                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           128451                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           12                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2122                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       436476                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       544160                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72697                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72697                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 616857                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           24                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4244                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15471548                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15635013                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17954309                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              219                       # Total snoops (count)
+system.membus.snoop_fanout::samples            281834                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  215583    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  281834    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              215583                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1204828500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              281834                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            86774000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy                6000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3334000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1752500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17917176000                       # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4952454428                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37912905250                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy          1264018000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         1594856745                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
+system.membus.respLayer3.occupancy           38339991                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq             16518783                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16518783                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8182                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8182                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7942                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          532                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1040                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
+system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq                30195                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30195                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59038                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2383082                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30670848                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     30670848                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                33053930                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio        15884                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio         1064                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio         2080                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       105550                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178466                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67959                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      2390530                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                125073922                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       159197                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480301                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             38529000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3976000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               532000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               526000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy         15335424000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374900000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         38695381750                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy           326584349                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer3.occupancy            36805009                       # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -490,25 +540,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     13160242                       # DTB read hits
-system.cpu.dtb.read_misses                       7329                       # DTB read misses
-system.cpu.dtb.write_hits                    11228050                       # DTB write hits
-system.cpu.dtb.write_misses                      2212                       # DTB write misses
-system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3401                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.read_hits                     24532668                       # DTB read hits
+system.cpu.dtb.read_misses                       8148                       # DTB read misses
+system.cpu.dtb.write_hits                    19614514                       # DTB write hits
+system.cpu.dtb.write_misses                      1410                       # DTB write misses
+system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                     4272                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    189                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   1630                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 13167571                       # DTB read accesses
-system.cpu.dtb.write_accesses                11230262                       # DTB write accesses
+system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24540816                       # DTB read accesses
+system.cpu.dtb.write_accesses                19615924                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          24388292                       # DTB hits
-system.cpu.dtb.misses                            9541                       # DTB misses
-system.cpu.dtb.accesses                      24397833                       # DTB accesses
+system.cpu.dtb.hits                          44147182                       # DTB hits
+system.cpu.dtb.misses                            9558                       # DTB misses
+system.cpu.dtb.accesses                      44156740                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -530,142 +580,142 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     61481095                       # ITB inst hits
-system.cpu.itb.inst_misses                       4471                       # ITB inst misses
+system.cpu.itb.inst_hits                    115605897                       # ITB inst hits
+system.cpu.itb.inst_misses                       4762                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2370                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                     2913                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61485566                       # ITB inst accesses
-system.cpu.itb.hits                          61481095                       # DTB hits
-system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61485566                       # DTB accesses
-system.cpu.numCycles                       5229143129                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                115610659                       # ITB inst accesses
+system.cpu.itb.hits                         115605897                       # DTB hits
+system.cpu.itb.misses                            4762                       # DTB misses
+system.cpu.itb.accesses                     115610659                       # DTB accesses
+system.cpu.numCycles                       5805238262                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60187274                       # Number of instructions committed
-system.cpu.committedOps                      71883961                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              64248492                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2139801                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7549047                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     64248492                       # number of integer instructions
-system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           116110622                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           42863098                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            257769006                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            28995258                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      25244235                       # number of memory refs
-system.cpu.num_load_insts                    13512788                       # Number of load instructions
-system.cpu.num_store_insts                   11731447                       # Number of store instructions
-system.cpu.num_idle_cycles               4584209782.584247                       # Number of idle cycles
-system.cpu.num_busy_cycles               644933346.415753                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.123334                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.876666                       # Percentage of idle cycles
-system.cpu.Branches                          10306630                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                 28518      0.04%      0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu                  47577014     65.23%     65.27% # Class of executed instruction
-system.cpu.op_class::IntMult                    87551      0.12%     65.39% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc               2109      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.39% # Class of executed instruction
-system.cpu.op_class::MemRead                 13512788     18.53%     83.92% # Class of executed instruction
-system.cpu.op_class::MemWrite                11731447     16.08%    100.00% # Class of executed instruction
+system.cpu.committedInsts                   112506996                       # Number of instructions committed
+system.cpu.committedOps                     135649573                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             119948924                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                  11161                       # Number of float alu accesses
+system.cpu.num_func_calls                     9898964                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15236398                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    119948924                       # number of integer instructions
+system.cpu.num_fp_insts                         11161                       # number of float instructions
+system.cpu.num_int_register_reads           218165442                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           82686636                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                 8449                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            489970612                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            51914328                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      45428231                       # number of memory refs
+system.cpu.num_load_insts                    24855392                       # Number of load instructions
+system.cpu.num_store_insts                   20572839                       # Number of store instructions
+system.cpu.num_idle_cycles               5386456122.024144                       # Number of idle cycles
+system.cpu.num_busy_cycles               418782139.975856                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.072139                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.927861                       # Percentage of idle cycles
+system.cpu.Branches                          25929456                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  93218055     67.17%     67.18% # Class of executed instruction
+system.cpu.op_class::IntMult                   114528      0.08%     67.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               8475      0.01%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.26% # Class of executed instruction
+system.cpu.op_class::MemRead                 24855392     17.91%     85.18% # Class of executed instruction
+system.cpu.op_class::MemWrite                20572839     14.82%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   72939427                       # Class of executed instruction
+system.cpu.op_class::total                  138771626                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    83004                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            855897                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.877214                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            60624686                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            856409                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.789408                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       19623933250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.877214                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997807                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997807                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                     3032                       # number of quiesce instructions executed
+system.cpu.icache.tags.replacements           1699818                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.781939                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           113905561                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1700330                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             66.990267                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       25181626250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.781939                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997621                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997621                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          266                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          62337504                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         62337504                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     60624686                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        60624686                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      60624686                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         60624686                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     60624686                       # number of overall hits
-system.cpu.icache.overall_hits::total        60624686                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       856409                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        856409                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       856409                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         856409                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       856409                       # number of overall misses
-system.cpu.icache.overall_misses::total        856409                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11766778500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11766778500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11766778500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11766778500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11766778500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11766778500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     61481095                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     61481095                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     61481095                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     61481095                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     61481095                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     61481095                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013930                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013930                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013930                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013930                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013930                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013930                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13739.671699                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13739.671699                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13739.671699                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13739.671699                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13739.671699                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13739.671699                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         117306233                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        117306233                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    113905561                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       113905561                       # number of ReadReq hits
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+system.cpu.icache.overall_misses::cpu.inst      1700336                       # number of overall misses
+system.cpu.icache.overall_misses::total       1700336                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  23243215000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  23243215000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  23243215000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  23243215000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  23243215000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  23243215000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    115605897                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    115605897                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    115605897                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    115605897                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    115605897                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    115605897                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014708                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014708                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014708                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014708                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014708                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014708                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.777620                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13669.777620                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.777620                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13669.777620                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.777620                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13669.777620                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -674,186 +724,196 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856409                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       856409                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       856409                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       856409                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       856409                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       856409                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10049953500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  10049953500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10049953500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  10049953500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10049953500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  10049953500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    440846250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    440846250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    440846250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    440846250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013930                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013930                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013930                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013930                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013930                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013930                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11734.992860                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11734.992860                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11734.992860                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11734.992860                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11734.992860                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11734.992860                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1700336                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1700336                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1700336                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1700336                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1700336                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1700336                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19835992000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  19835992000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19835992000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  19835992000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19835992000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  19835992000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    598490500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    598490500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    598490500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    598490500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014708                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014708                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014708                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014708                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014708                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014708                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.924852                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.924852                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.924852                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.924852                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.924852                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.924852                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            62827                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        50749.017881                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1679035                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           128209                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            13.096077                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2564785024500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37681.898715                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884636                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000702                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6996.424673                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6066.809153                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.574980                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000059                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            88869                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64932.369340                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2760846                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           154135                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            17.911869                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822165                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.809354                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.012212                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9580.724019                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4674.001590                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.773221                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000058                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.106757                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.092572                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.774369                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65378                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2139                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7027                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56159                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997589                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         17118836                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        17118836                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7538                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3114                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       844199                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       368983                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1223834                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       595027                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       595027                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       113476                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       113476                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         7538                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         3114                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       844199                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       482459                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1337310                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         7538                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         3114                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       844199                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       482459                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1337310                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.146190                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.071320                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.990789                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65261                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2131                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6951                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56138                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995804                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         26241966                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        26241966                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7097                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3700                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1682273                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_hits::total        2207892                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       686231                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       686231                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           23                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           23                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       166049                       # number of ReadExReq hits
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+system.cpu.l2cache.demand_hits::cpu.itb.walker         3700                       # number of demand (read+write) hits
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+system.cpu.l2cache.demand_hits::total         2373941                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::cpu.itb.walker         3700                       # number of overall hits
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-system.cpu.l2cache.ReadReq_misses::cpu.inst        10596                       # number of ReadReq misses
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-system.cpu.l2cache.UpgradeReq_misses::total         2895                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       134075                       # number of ReadExReq misses
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 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
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-system.cpu.l2cache.overall_misses::total       154550                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       305250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       150000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    749772500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    732753250                       # number of ReadReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       150000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    749772500                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.inst    749772500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10067261884                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10817489634                       # number of overall miss cycles
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-system.cpu.l2cache.Writeback_accesses::total       595027                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2921                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012396                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026057                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016455                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991099                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991099                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541606                       # miss rate for ReadExReq accesses
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+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       567750                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991612                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81107.142857                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74750                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72780.253894                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75357.968994                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73821.530143                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   172.114748                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   172.114748                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        23499                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        23499                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -862,92 +922,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        58138                       # number of writebacks
-system.cpu.l2cache.writebacks::total            58138                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10596                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10596                       # number of overall MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
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 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    349507750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166662160750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167011668500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16705919061                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16705919061                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    349507750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183368079811                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183717587561                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000663                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000642                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012396                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026057                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016455                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991099                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991099                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541606                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541606                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000663                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000642                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012396                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229798                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.103596                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000663                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000642                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012396                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229798                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.103596                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1087047500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8119492534                       # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5385176750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5859967250                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000985                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991612                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991612                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.439561                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.439561                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000985                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000540                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010609                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172995                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.063318                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000985                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000540                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010609                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172995                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.063318                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58237.400906                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61751.696718                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59929.865690                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.036269                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.036269                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57111.511214                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57111.511214                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60260.962359                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.122467                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61317.776712                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58237.400906                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57429.738834                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57484.890754                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58237.400906                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57429.738834                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57484.890754                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -957,166 +1025,183 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            625894                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.875658                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            21786154                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            626406                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             34.779606                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         668864250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.875658                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999757                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999757                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            822747                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.850534                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            43252597                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            823259                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             52.538262                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         876905250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.850534                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999708                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999708                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          321                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          113                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           82                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          90404594                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         90404594                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     11249411                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11249411                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9965441                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9965441                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        84252                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         84252                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236461                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236461                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247668                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247668                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21214852                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21214852                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21299104                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21299104                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       294699                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        294699                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       255299                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       255299                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       100108                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       100108                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11208                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11208                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       549998                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         549998                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       650106                       # number of overall misses
-system.cpu.dcache.overall_misses::total        650106                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   4039018749                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4039018749                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11552022511                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11552022511                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    154983250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    154983250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  15591041260                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  15591041260                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  15591041260                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  15591041260                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     11544110                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     11544110                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10220740                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10220740                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       184360                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       184360                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247669                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247669                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247668                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247668                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21764850                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21764850                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21949210                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21949210                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025528                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.025528                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024979                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024979                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.543003                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.543003                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045254                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045254                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025270                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025270                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.029619                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.029619                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13705.573310                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13705.573310                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45248.992401                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45248.992401                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13827.913098                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13827.913098                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28347.450827                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28347.450827                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23982.306362                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23982.306362                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses         177194873                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        177194873                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23122385                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23122385                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18831357                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18831357                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       392121                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        392121                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443546                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443546                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460444                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460444                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41953742                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41953742                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42345863                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42345863                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       402167                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        402167                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       299026                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       299026                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       119155                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       119155                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22691                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22691                       # number of LoadLockedReq misses
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+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
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+system.cpu.dcache.overall_misses::cpu.data       820348                       # number of overall misses
+system.cpu.dcache.overall_misses::total        820348                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5900820250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5900820250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11658401753                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11658401753                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    279152000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    279152000                       # number of LoadLockedReq miss cycles
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+system.cpu.dcache.StoreCondReq_miss_latency::total        53002                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  17559222003                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  17559222003                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  17559222003                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  17559222003                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23524552                       # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.overall_accesses::total     43166211                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017096                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.017096                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015631                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015631                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.233054                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.233054                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048668                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048668                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016439                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016439                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.019004                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.019004                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        26501                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        26501                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25041.924268                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21404.601465                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs           58                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                33                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     1.757576                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       595027                       # number of writebacks
-system.cpu.dcache.writebacks::total            595027                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          533                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          533                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         4827                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         4827                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         5360                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         5360                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         5360                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         5360                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       294166                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       294166                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250472                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250472                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        73481                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        73481                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11208                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        11208                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       544638                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       544638                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       618119                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       618119                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3444363000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3444363000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10784804239                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10784804239                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1224587250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1224587250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    132510750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    132510750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14229167239                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  14229167239                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15453754489                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15453754489                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182056011250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182056011250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26242438939                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26242438939                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208298450189                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208298450189                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.025482                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.025482                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024506                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024506                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.398573                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.398573                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.045254                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.045254                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025024                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025024                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028161                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028161                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11708.909255                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11708.909255                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43057.923596                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43057.923596                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16665.359072                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16665.359072                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11822.872056                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.872056                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26125.917103                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26125.917103                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25001.261066                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25001.261066                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       686231                       # number of writebacks
+system.cpu.dcache.writebacks::total            686231                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          627                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          627                       # number of ReadReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14222                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14222                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          627                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          627                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          627                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          627                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       401540                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       401540                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299026                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299026                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       117004                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       117004                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8469                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8469                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       700566                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       700566                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       817570                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       817570                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5083703250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5083703250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11002851247                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11002851247                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1411190000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1411190000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data     99471250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total     99471250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        48998                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        48998                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16086554497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  16086554497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17497744497                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17497744497                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5790648000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5790648000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4429678000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4429678000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10220326000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10220326000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017069                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017069                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015631                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015631                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228847                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228847                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018165                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018165                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016424                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016424                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018940                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.018940                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        24499                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        24499                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1124,75 +1209,139 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2453657                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2453657                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq        763381                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp       763381                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       595027                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2921                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2921                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       247551                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       247551                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1724466                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5748697                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12042                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        26252                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7511457                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54733404                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83586150                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        30172                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          138362190                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       18590                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2108398                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        2294827                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2294812                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       686231                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2742                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2744                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296284                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296284                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3418694                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2456076                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12917                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        24956                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5912643                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108856060                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96807049                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14808                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        28416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          205706333                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       52963                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3276134                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.011129                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.104904                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            2108398    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            3239675     98.89%     98.89% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6              36459      1.11%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2108398                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3007986500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        3276134                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2353775000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1294797750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2533255572                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy       8926000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       328500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    2564913000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    1311853505                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy       9215000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      18709500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      17852250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                    0                       # number of replacements
-system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
+system.iocache.tags.replacements                36424                       # number of replacements
+system.iocache.tags.tagsinuse                1.133398                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
-system.iocache.tags.data_accesses                   0                       # Number of data accesses
+system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         298397241000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.133398                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.070837                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.070837                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
+system.iocache.tags.data_accesses              328122                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
+system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          234                       # number of overall misses
+system.iocache.overall_misses::total              234                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     28038377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28038377                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28038377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28038377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28038377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28038377                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119822.123932                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119822.123932                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 119822.123932                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119822.123932                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 119822.123932                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119822.123932                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      36224                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760318460750                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1760318460750                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760318460750                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1760318460750                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     15869377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     15869377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2206856981                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2206856981                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     15869377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     15869377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     15869377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     15869377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67817.850427                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67817.850427                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67817.850427                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
index ca0537849..b3be0ec54 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index 3b28bd981..c44b0a7f7 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+atags_addr=134217728
+boot_loader=/dist/binaries/boot_emm.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=
+dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
-flags_addr=268435504
-gic_cpu_addr=520093952
+flags_addr=469827632
+gic_cpu_addr=738205696
 have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
-load_offset=0
-machine_type=RealView_PBX
+load_offset=2147483648
+machine_type=VExpress_EMM
 mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -53,14 +53,14 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[0]
+system_port=system.membus.slave[1]
 
 [system.bridge]
 type=Bridge
 clk_domain=system.clk_domain
 delay=50000
 eventq_index=0
-ranges=268435456:520093695 1073741824:1610612735
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -278,6 +278,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu0.istage2_mmu]
@@ -428,6 +429,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu1.istage2_mmu]
@@ -499,15 +501,16 @@ type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
-use_default_range=false
+use_default_range=true
 width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
 type=BaseCache
 children=tags
-addr_ranges=0:134217727
+addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
 eventq_index=0
@@ -526,8 +529,8 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.master[26]
-mem_side=system.membus.slave[2]
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
 type=LRU
@@ -562,7 +565,7 @@ tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
 
 [system.l2c.tags]
 type=LRU
@@ -585,8 +588,8 @@ system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -616,47 +619,38 @@ in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=0:134217727
-port=system.membus.master[6]
+range=2147483648:2415919103
+port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=0
+pci_cfg_base=805306368
 pci_cfg_gen_offsets=false
 pci_io_base=0
 system=system
 
-[system.realview.a9scu]
-type=A9SCU
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=520093696
-pio_latency=100000
-system=system
-pio=system.membus.master[4]
-
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268451840
+pio_addr=470024192
 pio_latency=100000
 system=system
-pio=system.iobus.master[21]
+pio=system.iobus.master[18]
 
 [system.realview.cf_ctrl]
 type=IdeController
-BAR0=402653184
+BAR0=471465984
 BAR0LegacyIO=true
-BAR0Size=16
-BAR1=402653440
+BAR0Size=256
+BAR1=471466240
 BAR1LegacyIO=true
-BAR1Size=1
+BAR1Size=4096
 BAR2=1
 BAR2LegacyIO=false
 BAR2Size=8
@@ -726,18 +720,18 @@ VendorID=32902
 clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
-disks=system.cf0
+disks=
 eventq_index=0
-io_shift=1
+io_shift=2
 pci_bus=2
-pci_dev=7
+pci_dev=0
 pci_func=0
 pio_latency=30000
 platform=system.realview
 system=system
-config=system.iobus.master[8]
+config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.clcd]
 type=Pl111
@@ -746,8 +740,8 @@ clk_domain=system.clk_domain
 enable_capture=true
 eventq_index=0
 gic=system.realview.gic
-int_num=55
-pio_addr=268566528
+int_num=46
+pio_addr=471793664
 pio_latency=10000
 pixel_clock=41667
 system=system
@@ -755,51 +749,129 @@ vnc=system.vncserver
 dma=system.iobus.slave[1]
 pio=system.iobus.master[4]
 
-[system.realview.dmac_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.energy_ctrl]
+type=EnergyCtrl
 clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
 eventq_index=0
-ignore_access=false
-pio_addr=268632064
+pio_addr=470286336
 pio_latency=100000
 system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[22]
 
-[system.realview.energy_ctrl]
-type=EnergyCtrl
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
 clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
+config_latency=20000
 eventq_index=0
-pio_addr=268496896
-pio_latency=100000
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
 system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
 pio=system.iobus.master[25]
 
-[system.realview.flash_fake]
-type=IsaFake
-clk_domain=system.clk_domain
+[system.realview.generic_timer]
+type=GenericTimer
 eventq_index=0
-fake_mem=true
-pio_addr=1073741824
-pio_latency=100000
-pio_size=536870912
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
+gic=system.realview.gic
+int_num=29
 system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
 clk_domain=system.clk_domain
-cpu_addr=520093952
+cpu_addr=738205696
 cpu_pio_delay=10000
-dist_addr=520097792
+dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
@@ -809,38 +881,111 @@ platform=system.realview
 system=system
 pio=system.membus.master[2]
 
-[system.realview.gpio0_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268513280
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.gpio1_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
 clk_domain=system.clk_domain
+enable_capture=true
 eventq_index=0
-ignore_access=false
-pio_addr=268517376
-pio_latency=100000
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
 system=system
-pio=system.iobus.master[17]
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
 
-[system.realview.gpio2_fake]
-type=AmbaFake
-amba_id=0
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
 clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
 eventq_index=0
-ignore_access=false
-pio_addr=268521472
-pio_latency=100000
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
 system=system
-pio=system.iobus.master[18]
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
 
 [system.realview.kmi0]
 type=Pl050
@@ -849,13 +994,13 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=52
+int_num=44
 is_mouse=false
-pio_addr=268460032
+pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.kmi1]
 type=Pl050
@@ -864,20 +1009,20 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
-int_num=53
+int_num=45
 is_mouse=true
-pio_addr=268464128
+pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.l2x0_fake]
 type=IsaFake
 clk_domain=system.clk_domain
 eventq_index=0
 fake_mem=false
-pio_addr=520101888
+pio_addr=739246080
 pio_latency=100000
 pio_size=4095
 ret_bad_addr=false
@@ -888,7 +1033,25 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[3]
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
@@ -897,10 +1060,10 @@ eventq_index=0
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
-pio_addr=520095232
+pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[3]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -908,10 +1071,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268455936
+pio_addr=470089728
 pio_latency=100000
 system=system
-pio=system.iobus.master[22]
+pio=system.iobus.master[21]
 
 [system.realview.nvmem]
 type=SimpleMemory
@@ -923,18 +1086,30 @@ in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=2147483648:2214592511
+range=0:67108863
 port=system.membus.master[1]
 
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
 [system.realview.realview_io]
 type=RealViewCtrl
 clk_domain=system.clk_domain
 eventq_index=0
-idreg=0
-pio_addr=268435456
+idreg=35979264
+pio_addr=469827584
 pio_latency=100000
-proc_id0=201326592
-proc_id1=201327138
+proc_id0=335544320
+proc_id1=335544320
 system=system
 pio=system.iobus.master[1]
 
@@ -945,34 +1120,12 @@ clk_domain=system.clk_domain
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=42
-pio_addr=268529664
+int_num=36
+pio_addr=471269376
 pio_latency=100000
 system=system
 time=Thu Jan  1 00:00:00 2009
-pio=system.iobus.master[23]
-
-[system.realview.sci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268492800
-pio_latency=100000
-system=system
-pio=system.iobus.master[20]
-
-[system.realview.smc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=269357056
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
+pio=system.iobus.master[10]
 
 [system.realview.sp810_fake]
 type=AmbaFake
@@ -980,21 +1133,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=true
-pio_addr=268439552
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.ssp_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=268488704
+pio_addr=469893120
 pio_latency=100000
 system=system
-pio=system.iobus.master[19]
+pio=system.iobus.master[16]
 
 [system.realview.timer0]
 type=Sp804
@@ -1004,9 +1146,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=36
-int_num1=36
-pio_addr=268505088
+int_num0=34
+int_num1=34
+pio_addr=470876160
 pio_latency=100000
 system=system
 pio=system.iobus.master[2]
@@ -1019,9 +1161,9 @@ clock0=1000000
 clock1=1000000
 eventq_index=0
 gic=system.realview.gic
-int_num0=37
-int_num1=37
-pio_addr=268509184
+int_num0=35
+int_num1=35
+pio_addr=470941696
 pio_latency=100000
 system=system
 pio=system.iobus.master[3]
@@ -1033,8 +1175,8 @@ end_on_eot=false
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
-int_num=44
-pio_addr=268472320
+int_num=37
+pio_addr=470351872
 pio_latency=100000
 platform=system.realview
 system=system
@@ -1047,10 +1189,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268476416
+pio_addr=470417408
 pio_latency=100000
 system=system
-pio=system.iobus.master[10]
+pio=system.iobus.master[13]
 
 [system.realview.uart2_fake]
 type=AmbaFake
@@ -1058,10 +1200,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268480512
+pio_addr=470482944
 pio_latency=100000
 system=system
-pio=system.iobus.master[11]
+pio=system.iobus.master[14]
 
 [system.realview.uart3_fake]
 type=AmbaFake
@@ -1069,10 +1211,54 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268484608
+pio_addr=470548480
 pio_latency=100000
 system=system
-pio=system.iobus.master[12]
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
@@ -1080,10 +1266,10 @@ amba_id=0
 clk_domain=system.clk_domain
 eventq_index=0
 ignore_access=false
-pio_addr=268500992
+pio_addr=470745088
 pio_latency=100000
 system=system
-pio=system.iobus.master[15]
+pio=system.iobus.master[17]
 
 [system.terminal]
 type=Terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
index 08406cf3a..cf30e237d 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
@@ -1,16 +1,35 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: Not doing anything for miscreg ACTLR
+warn: Not doing anything for write of miscreg ACTLR
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: LCD dual screen mode not supported
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
+warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
+warn: Returning zero for read from miscreg pmcr
+warn: Ignoring write to miscreg pmcntenclr
+warn: Ignoring write to miscreg pmintenclr
+warn: Ignoring write to miscreg pmovsr
+warn: Ignoring write to miscreg pmcr
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
index f0d337e74..0605672c9 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:10:38
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:00:04
 gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu0.isa: ISA system set to: 0x56d2400 0x56d2400
-      0: system.cpu1.isa: ISA system set to: 0x56d2400 0x56d2400
+      0: system.cpu0.isa: ISA system set to: 0x50c1b00 0x50c1b00
+      0: system.cpu1.isa: ISA system set to: 0x50c1b00 0x50c1b00
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index 5818937f9..863689702 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -1,278 +1,300 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.321335                       # Number of seconds simulated
-sim_ticks                                2321335404000                       # Number of ticks simulated
-final_tick                               2321335404000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.783853                       # Number of seconds simulated
+sim_ticks                                2783853461500                       # Number of ticks simulated
+final_tick                               2783853461500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1185543                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1427641                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            45558461303                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 457752                       # Number of bytes of host memory used
-host_seconds                                    50.95                       # Real time elapsed on the host
-sim_insts                                    60406834                       # Number of instructions simulated
-sim_ops                                      72742429                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1402368                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1707157                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            27344724772                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 555568                       # Number of bytes of host memory used
+host_seconds                                   101.81                       # Real time elapsed on the host
+sim_insts                                   142769281                       # Number of instructions simulated
+sim_ops                                     173798567                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.clcd    110100480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           508104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5777624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           197312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          3294400                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            119878240                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       508104                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       197312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          705416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3703808                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1461532                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1554284                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6719624                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      13762560                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             14151                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             90301                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3083                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             51475                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              13921575                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57872                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           365383                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           388571                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811826                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47429803                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker            55                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            83                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              218884                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             2488923                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               84999                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1419183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51641930                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         218884                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          84999                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             303884                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1595551                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             629608                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             669565                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2894723                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1595551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47429803                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker           55                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           83                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             218884                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3118531                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              84999                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2088748                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54536653                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           727076                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4668128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           483904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5677444                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11558024                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       727076                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       483904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1210980                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6521088                       # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8856948                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             19814                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73458                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              7561                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             88711                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                189567                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          101892                       # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142497                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              261176                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1676858                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker            46                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              173825                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             2039419                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4151808                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         261176                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         173825                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             435001                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2342468                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide          832779                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6292                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3181542                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2342468                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide          833124                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          115                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             261176                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1683150                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             173825                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2039422                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7333350                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst           24                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            24                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           24                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           24                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            6                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              6                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu0.inst            9                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            9                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq            14973628                       # Transaction distribution
-system.membus.trans_dist::ReadResp           14973628                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763122                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763122                       # Transaction distribution
-system.membus.trans_dist::Writeback             57872                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4519                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4519                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131877                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131877                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382824                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3360                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1892848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4279044                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     27525120                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     27525120                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               31804164                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      2390127                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         6720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16497384                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18894255                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port    110100480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total    110100480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               128994735                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               74230                       # Transaction distribution
+system.membus.trans_dist::ReadResp              74230                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27560                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27560                       # Transaction distribution
+system.membus.trans_dist::Writeback            101892                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            146085                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           146085                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105446                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           12                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       498776                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       606180                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72928                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72928                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 679108                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159103                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           24                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18095676                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18258695                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2333696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2333696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20592391                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            214752                       # Request fanout histogram
+system.membus.snoop_fanout::samples            322845                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  214752    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  322845    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              214752                       # Request fanout histogram
+system.membus.snoop_fanout::total              322845                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    62250                       # number of replacements
-system.l2c.tags.tagsinuse                50005.858036                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1678527                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   127635                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.150993                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             2306275686000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36902.743708                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.993864                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.993972                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4873.119904                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3553.057866                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2141.364810                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2533.583912                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.563091                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.074358                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.054215                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.032675                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.038659                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.763029                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023            2                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65383                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
+system.l2c.tags.replacements                   110021                       # number of replacements
+system.l2c.tags.tagsinuse                65155.315266                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2731077                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   175302                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    15.579269                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   48893.451407                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.924325                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000096                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5044.249806                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4729.238472                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.978702                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4020.297746                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2464.174711                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.746055                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.076969                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.072162                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.061345                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.037600                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.994191                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65277                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3672                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         9282                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52127                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000031                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.997665                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 17105211                       # Number of tag accesses
-system.l2c.tags.data_accesses                17105211                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         8799                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         3276                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu0.data             189163                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5176                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         2130                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu1.data             177603                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1224929                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          592674                       # number of Writeback hits
-system.l2c.Writeback_hits::total               592674                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              16                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              10                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            62080                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            51632                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               113712                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          8799                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          3276                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              451004                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              251243                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5176                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          2130                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              387778                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              229235                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1338641                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         8799                       # number of overall hits
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-system.l2c.overall_hits::cpu1.inst             387778                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             229235                       # number of overall hits
-system.l2c.overall_hits::total                1338641                       # number of overall hits
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-system.l2c.ReadReq_misses::cpu0.data             6105                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.data             3766                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20484                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1505                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1412                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2917                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          85002                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          48477                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133479                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7525                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             91107                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3083                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             52243                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153963                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker            2                       # number of overall misses
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-system.l2c.overall_misses::cpu0.inst             7525                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            91107                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3083                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            52243                       # number of overall misses
-system.l2c.overall_misses::total               153963                       # number of overall misses
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-system.l2c.ReadReq_accesses::cpu0.inst         458529                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         195268                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::cpu1.inst         390861                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         181369                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1245413                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       592674                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           592674                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1521                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1422                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2943                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       147082                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       100109                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247191                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         8801                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         3279                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu0.data          342350                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         5176                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         2130                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          390861                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          281478                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1492604                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         8801                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         3279                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         458529                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         342350                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         5176                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu1.inst         390861                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         281478                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1492604                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000227                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000915                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.016411                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.031265                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.007888                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.020764                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016448                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989481                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992968                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.991165                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.577923                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.484242                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.539983                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000227                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000915                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.016411                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.266122                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.007888                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.185602                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.103151                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000227                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000915                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.016411                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.266122                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.007888                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.185602                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.103151                       # miss rate for overall accesses
+system.l2c.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3716                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        10700                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        50641                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.996048                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 26229754                       # Number of tag accesses
+system.l2c.tags.data_accesses                26229754                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         4715                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         2286                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::total                2201051                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          682262                       # number of Writeback hits
+system.l2c.Writeback_hits::total               682262                       # number of Writeback hits
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+system.l2c.UpgradeReq_hits::total                  28                       # number of UpgradeReq hits
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+system.l2c.ReadExReq_hits::cpu1.data            78732                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               151041                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          4715                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu0.data              319080                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.data              337457                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2352092                       # number of demand (read+write) hits
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+system.l2c.overall_hits::total                2352092                       # number of overall hits
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+system.l2c.ReadReq_misses::cpu1.data             5778                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                33895                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1248                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::total              2728                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
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+system.l2c.demand_misses::cpu1.data             89676                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                181759                       # number of demand (read+write) misses
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001059                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu1.data      0.021845                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.015166                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990476                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.989305                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.989840                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.469389                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.515883                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.494686                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001059                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.012790                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.187672                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000401                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.008840                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.209949                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.071732                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001059                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.012790                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.187672                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000401                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.008840                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.209949                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.071732                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -281,108 +303,137 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57872                       # number of writebacks
-system.l2c.writebacks::total                    57872                       # number of writebacks
+system.l2c.writebacks::writebacks              101892                       # number of writebacks
+system.l2c.writebacks::total                   101892                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            2455233                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2455233                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            763122                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           763122                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           592674                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2943                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2943                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           247191                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          247191                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1715294                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5740366                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        22916                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        51076                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7529652                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54491548                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     83268947                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        45832                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       102152                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              137908479                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                               0                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          2107457                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean                   5                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
+system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq            2291806                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2291806                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             27560                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            27560                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           682262                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2756                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2758                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           298905                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          298905                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3417070                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2444902                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20772                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        41576                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5924320                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108804860                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96323083                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41544                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        83152                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              205252639                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           36632                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3272100                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.011144                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.104975                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                2107457    100.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                3235636     98.89%     98.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                  36464      1.11%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              5                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2107457                       # Request fanout histogram
-system.iobus.trans_dist::ReadReq             14945841                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            14945841                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8131                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8131                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7900                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          476                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          984                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            3272100                       # Request fanout histogram
+system.iobus.trans_dist::ReadReq                30171                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30171                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59016                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22792                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54158                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          732                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          834                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382824                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     27525120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     27525120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                29907944                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        39247                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio        15800                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio          952                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio         1968                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       105446                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72928                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72928                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178374                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67875                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          390                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          441                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      2390127                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    110100480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.clcd.dma::total    110100480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                112490607                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       159103                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321152                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480255                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -406,25 +457,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     6816435                       # DTB read hits
-system.cpu0.dtb.read_misses                      6211                       # DTB read misses
-system.cpu0.dtb.write_hits                    6254825                       # DTB write hits
-system.cpu0.dtb.write_misses                     2049                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        2324                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                758                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    5541                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.read_hits                    15997245                       # DTB read hits
+system.cpu0.dtb.read_misses                      4798                       # DTB read misses
+system.cpu0.dtb.write_hits                   11281299                       # DTB write hits
+system.cpu0.dtb.write_misses                      897                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        2812                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     403                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    3224                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   120                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   779                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      232                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 6822646                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6256874                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      202                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                16002043                       # DTB read accesses
+system.cpu0.dtb.write_accesses               11282196                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         13071260                       # DTB hits
-system.cpu0.dtb.misses                           8260                       # DTB misses
-system.cpu0.dtb.accesses                     13079520                       # DTB accesses
+system.cpu0.dtb.hits                         27278544                       # DTB hits
+system.cpu0.dtb.misses                           5695                       # DTB misses
+system.cpu0.dtb.accesses                     27284239                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -446,144 +497,144 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    32152502                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3598                       # ITB inst misses
+system.cpu0.itb.inst_hits                    74797989                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2590                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        2324                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                758                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2674                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb                        2812                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     403                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    1905                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                32156100                       # ITB inst accesses
-system.cpu0.itb.hits                         32152502                       # DTB hits
-system.cpu0.itb.misses                           3598                       # DTB misses
-system.cpu0.itb.accesses                     32156100                       # DTB accesses
-system.cpu0.numCycles                      4610022066                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                74800579                       # ITB inst accesses
+system.cpu0.itb.hits                         74797989                       # DTB hits
+system.cpu0.itb.misses                           2590                       # DTB misses
+system.cpu0.itb.accesses                     74800579                       # DTB accesses
+system.cpu0.numCycles                      5536445370                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31655881                       # Number of instructions committed
-system.cpu0.committedOps                     38589756                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             34002307                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5498                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1192858                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4013764                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    34002307                       # number of integer instructions
-system.cpu0.num_fp_insts                         5498                       # number of float instructions
-system.cpu0.num_int_register_reads           62271464                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          22558612                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3941                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1558                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           115497170                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           15275707                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13519126                       # number of memory refs
-system.cpu0.num_load_insts                    6992673                       # Number of load instructions
-system.cpu0.num_store_insts                   6526453                       # Number of store instructions
-system.cpu0.num_idle_cycles              4538759726.926458                       # Number of idle cycles
-system.cpu0.num_busy_cycles              71262339.073542                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.015458                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.984542                       # Percentage of idle cycles
-system.cpu0.Branches                          5545179                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                16079      0.04%      0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 25081623     64.87%     64.91% # Class of executed instruction
-system.cpu0.op_class::IntMult                   45922      0.12%     65.03% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              1365      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     65.03% # Class of executed instruction
-system.cpu0.op_class::MemRead                 6992673     18.09%     83.12% # Class of executed instruction
-system.cpu0.op_class::MemWrite                6526453     16.88%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   72639024                       # Number of instructions committed
+system.cpu0.committedOps                     87981151                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             77491342                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5273                       # Number of float alu accesses
+system.cpu0.num_func_calls                    8694279                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      9459647                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    77491342                       # number of integer instructions
+system.cpu0.num_fp_insts                         5273                       # number of float instructions
+system.cpu0.num_int_register_reads          144069707                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          54447285                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4051                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1224                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           268877072                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           31833969                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     27909499                       # number of memory refs
+system.cpu0.num_load_insts                   16164843                       # Number of load instructions
+system.cpu0.num_store_insts                  11744656                       # Number of store instructions
+system.cpu0.num_idle_cycles              5353619097.982533                       # Number of idle cycles
+system.cpu0.num_busy_cycles              182826272.017466                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.033022                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.966978                       # Percentage of idle cycles
+system.cpu0.Branches                         18600717                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2187      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 61776214     68.83%     68.83% # Class of executed instruction
+system.cpu0.op_class::IntMult                   59687      0.07%     68.90% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              4413      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::MemRead                16164843     18.01%     86.91% # Class of executed instruction
+system.cpu0.op_class::MemWrite               11744656     13.09%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  38664115                       # Class of executed instruction
+system.cpu0.op_class::total                  89752000                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   82781                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           850504                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.689630                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           60581751                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           851016                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            71.187558                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       5451547500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   446.338382                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    65.351248                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.871755                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.127639                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999394                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    3080                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements          1698994                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.663679                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          145339246                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1699506                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            85.518525                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       7831492000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   455.122338                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    56.541342                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.888911                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.110432                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999343                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           61                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          249                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         62283783                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        62283783                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     31695864                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     28885887                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       60581751                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     31695864                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     28885887                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        60581751                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     31695864                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     28885887                       # number of overall hits
-system.cpu0.icache.overall_hits::total       60581751                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       459362                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       391654                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       851016                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       459362                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       391654                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        851016                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       459362                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       391654                       # number of overall misses
-system.cpu0.icache.overall_misses::total       851016                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     32155226                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     29277541                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     61432767                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     32155226                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     29277541                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     61432767                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     32155226                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     29277541                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     61432767                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014286                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.013377                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.013853                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014286                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.013377                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.013853                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014286                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.013377                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.013853                       # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses        148738270                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       148738270                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     73955669                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     71383577                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      145339246                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     73955669                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     71383577                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       145339246                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     73955669                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     71383577                       # number of overall hits
+system.cpu0.icache.overall_hits::total      145339246                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       844195                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       855317                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1699512                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       844195                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       855317                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1699512                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       844195                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       855317                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1699512                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     74799864                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     72238894                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    147038758                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     74799864                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     72238894                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    147038758                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     74799864                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     72238894                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    147038758                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011286                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011840                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011558                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011286                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011840                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011558                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011286                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011840                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011558                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -593,102 +644,106 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           623316                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997018                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           21798519                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           623828                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            34.943156                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         21757000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   453.972290                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    58.024728                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.886665                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.113330                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           819402                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.997174                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           53782968                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           819914                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            65.595865                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         23054000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   475.832873                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    36.164301                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.929361                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.070633                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          291                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          286                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         90313216                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        90313216                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5840103                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      5400119                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11240222                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5597078                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      4364227                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       9961305                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        52143                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        58700                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       110843                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       136250                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        99760                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       236010                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       142749                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       104447                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247196                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11437181                       # number of demand (read+write) hits
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-system.cpu0.dcache.demand_hits::total        21201527                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11489324                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      9823046                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       21312370                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       155804                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       136229                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       292033                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       148603                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       101531                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       250134                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        32964                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        40453                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total        73417                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6500                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         4687                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        11187                       # number of LoadLockedReq misses
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-system.cpu0.dcache.overall_misses::cpu0.data       337371                       # number of overall misses
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-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5745681                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      4465758                       # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data        85107                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        99153                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       184260                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       142750                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       104447                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       247197                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       142749                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       104447                       # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.demand_accesses::cpu0.data     11741588                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     10002106                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21743694                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11826695                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     10101259                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21927954                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025985                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.024606                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.025323                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025863                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.022735                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.387324                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.407986                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.398442                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.045534                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044874                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.045255                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025926                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023771                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.024934                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028526                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027542                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.028073                       # miss rate for overall accesses
+system.cpu0.dcache.tags.tag_accesses        219231522                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       219231522                       # Number of data accesses
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+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       222317                       # number of LoadLockedReq hits
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.012739                       # miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.226452                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227661                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.227093                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.019461                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.017522                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.018519                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.012626                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013629                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.013129                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.014543                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.015786                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.015166                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -697,8 +752,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       592674                       # number of writebacks
-system.cpu0.dcache.writebacks::total           592674                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       682262                       # number of writebacks
+system.cpu0.dcache.writebacks::total           682262                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -723,25 +778,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     6322311                       # DTB read hits
-system.cpu1.dtb.read_misses                      4545                       # DTB read misses
-system.cpu1.dtb.write_hits                    4960387                       # DTB write hits
-system.cpu1.dtb.write_misses                     1127                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        2320                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                681                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3056                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.read_hits                    15526476                       # DTB read hits
+system.cpu1.dtb.read_misses                      5406                       # DTB read misses
+system.cpu1.dtb.write_hits                   11842298                       # DTB write hits
+system.cpu1.dtb.write_misses                      791                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        2818                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     514                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    3194                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                    92                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   917                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      220                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 6326856                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4961514                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      243                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                15531882                       # DTB read accesses
+system.cpu1.dtb.write_accesses               11843089                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         11282698                       # DTB hits
-system.cpu1.dtb.misses                           5672                       # DTB misses
-system.cpu1.dtb.accesses                     11288370                       # DTB accesses
+system.cpu1.dtb.hits                         27368774                       # DTB hits
+system.cpu1.dtb.misses                           6197                       # DTB misses
+system.cpu1.dtb.accesses                     27374971                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -763,104 +818,132 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    29275767                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2611                       # ITB inst misses
+system.cpu1.itb.inst_hits                    72236782                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3052                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        2320                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                681                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1680                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb                        2818                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     514                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    2023                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                29278378                       # ITB inst accesses
-system.cpu1.itb.hits                         29275767                       # DTB hits
-system.cpu1.itb.misses                           2611                       # DTB misses
-system.cpu1.itb.accesses                     29278378                       # DTB accesses
-system.cpu1.numCycles                       143033518                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                72239834                       # ITB inst accesses
+system.cpu1.itb.hits                         72236782                       # DTB hits
+system.cpu1.itb.misses                           3052                       # DTB misses
+system.cpu1.itb.accesses                     72239834                       # DTB accesses
+system.cpu1.numCycles                        88012648                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   28750953                       # Number of instructions committed
-system.cpu1.committedOps                     34152673                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             30189123                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  4771                       # Number of float alu accesses
-system.cpu1.num_func_calls                     942904                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3531220                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    30189123                       # number of integer instructions
-system.cpu1.num_fp_insts                         4771                       # number of float instructions
-system.cpu1.num_int_register_reads           54155883                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          20259495                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3552                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1222                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           102072834                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           13702034                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     11702148                       # number of memory refs
-system.cpu1.num_load_insts                    6507264                       # Number of load instructions
-system.cpu1.num_store_insts                   5194884                       # Number of store instructions
-system.cpu1.num_idle_cycles              140979209.208319                       # Number of idle cycles
-system.cpu1.num_busy_cycles              2054308.791681                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.014362                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.985638                       # Percentage of idle cycles
-system.cpu1.Branches                          4753338                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                12439      0.04%      0.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 22454409     65.63%     65.67% # Class of executed instruction
-system.cpu1.op_class::IntMult                   41849      0.12%     65.79% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc               748      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.79% # Class of executed instruction
-system.cpu1.op_class::MemRead                 6507264     19.02%     84.82% # Class of executed instruction
-system.cpu1.op_class::MemWrite                5194884     15.18%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   70130257                       # Number of instructions committed
+system.cpu1.committedOps                     85817416                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             75667160                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  6211                       # Number of float alu accesses
+system.cpu1.num_func_calls                    8179026                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      9270368                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    75667160                       # number of integer instructions
+system.cpu1.num_fp_insts                         6211                       # number of float instructions
+system.cpu1.num_int_register_reads          140982352                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          52729123                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4721                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1492                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           261962982                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           30529174                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     28028313                       # number of memory refs
+system.cpu1.num_load_insts                   15690218                       # Number of load instructions
+system.cpu1.num_store_insts                  12338095                       # Number of store instructions
+system.cpu1.num_idle_cycles              85358107.940046                       # Number of idle cycles
+system.cpu1.num_busy_cycles              2654540.059954                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.030161                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.969839                       # Percentage of idle cycles
+system.cpu1.Branches                         17795350                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                  150      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 59373450     67.88%     67.88% # Class of executed instruction
+system.cpu1.op_class::IntMult                   57194      0.07%     67.95% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              4156      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::MemRead                15690218     17.94%     85.89% # Class of executed instruction
+system.cpu1.op_class::MemWrite               12338095     14.11%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  34211593                       # Class of executed instruction
+system.cpu1.op_class::total                  87463263                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.iocache.tags.replacements                    0                       # number of replacements
-system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
+system.iocache.tags.replacements                36430                       # number of replacements
+system.iocache.tags.tagsinuse                0.909886                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
-system.iocache.tags.data_accesses                   0                       # Number of data accesses
+system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         227409698009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     0.909886                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.056868                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.056868                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               328176                       # Number of tag accesses
+system.iocache.tags.data_accesses              328176                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
+system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          240                       # number of overall misses
+system.iocache.overall_misses::total              240                       # number of overall misses
+system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.fast_writes                      36224                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/system.terminal
index d321164ca..b3be0ec54 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 2bc3edd20..b395adf7f 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -28,7 +28,7 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -1180,7 +1180,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1203,7 +1203,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1427,6 +1427,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
index bb1874a4f..f30c0bc17 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
@@ -1,3 +1,4 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index f1feb2eac..a4565b1b8 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 17:30:19
+gem5 compiled Oct 29 2014 09:18:07
+gem5 started Oct 29 2014 09:26:24
 gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5196390180000 because m5_exit instruction encountered
+Exiting @ tick 5194410635000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 89c62f3e3..8675b3331 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.194411                       # Nu
 sim_ticks                                5194410635000                       # Number of ticks simulated
 final_tick                               5194410635000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 693425                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1336696                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            28047460404                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 637768                       # Number of bytes of host memory used
-host_seconds                                   185.20                       # Real time elapsed on the host
+host_inst_rate                                1079720                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2081347                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            43672253601                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 589096                       # Number of bytes of host memory used
+host_seconds                                   118.94                       # Real time elapsed on the host
 sim_insts                                   128422722                       # Number of instructions simulated
 sim_ops                                     247557000                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -424,8 +424,6 @@ system.iocache.fast_writes                      46720                       # nu
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          847                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          847                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::pc.south_bridge.ide          847                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          847                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::pc.south_bridge.ide          847                       # number of overall MSHR misses
@@ -440,16 +438,14 @@ system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97471186
 system.iocache.overall_mshr_miss_latency::total     97471186                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.999979                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.999979                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60522.456336                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60522.456336                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 115078.141677                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average overall mshr miss latency