diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/quick/fs | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/quick/fs')
12 files changed, 4243 insertions, 4149 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 6b719babe..a5d2b415b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -197,7 +197,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -440,8 +440,8 @@ system.cpu0.num_fp_register_writes 150767 # nu system.cpu0.num_mem_refs 15124548 # number of memory refs system.cpu0.num_load_insts 9178366 # Number of load instructions system.cpu0.num_store_insts 5946182 # Number of store instructions -system.cpu0.num_idle_cycles 3683454681.836560 # Number of idle cycles -system.cpu0.num_busy_cycles 57196201.163440 # Number of busy cycles +system.cpu0.num_idle_cycles 3683454681.064560 # Number of idle cycles +system.cpu0.num_busy_cycles 57196201.935440 # Number of busy cycles system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 2435d9264..178493c15 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -187,7 +187,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -302,8 +302,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115688 # number of memory refs system.cpu.num_load_insts 9747503 # Number of load instructions system.cpu.num_store_insts 6368185 # Number of store instructions -system.cpu.num_idle_cycles 3598606250.520791 # Number of idle cycles -system.cpu.num_busy_cycles 60054827.479209 # Number of busy cycles +system.cpu.num_idle_cycles 3598606249.772791 # Number of idle cycles +system.cpu.num_busy_cycles 60054828.227209 # Number of busy cycles system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983586 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -608,5 +608,69 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2042707 # number of replacements +system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits +system.cpu.dcache.overall_hits::total 13655968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks +system.cpu.dcache.writebacks::total 833491 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 0e2cc710f..e93e66fed 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.950814 # Number of seconds simulated -sim_ticks 1950813955500 # Number of ticks simulated -final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.952724 # Number of seconds simulated +sim_ticks 1952724269500 # Number of ticks simulated +final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 720692 # Simulator instruction rate (inst/s) -host_op_rate 720692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23054537293 # Simulator tick rate (ticks/s) -host_mem_usage 378432 # Number of bytes of host memory used -host_seconds 84.62 # Real time elapsed on the host -sim_insts 60983017 # Number of instructions simulated -sim_ops 60983017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory +host_inst_rate 1678586 # Simulator instruction rate (inst/s) +host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53851852439 # Simulator tick rate (ticks/s) +host_mem_usage 333452 # Number of bytes of host memory used +host_seconds 36.26 # Real time elapsed on the host +sim_insts 60867235 # Number of instructions simulated +sim_ops 60867235 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory -system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory -system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory +system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory +system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448191 # Total number of read requests seen -system.physmem.writeReqs 120414 # Total number of write requests seen -system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28684224 # Total number of bytes read from memory -system.physmem.bytesWritten 7706496 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis +system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448125 # Total number of read requests seen +system.physmem.writeReqs 120294 # Total number of write requests seen +system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28680000 # Total number of bytes read from memory +system.physmem.bytesWritten 7698816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry -system.physmem.totGap 1950760240000 # Total gap between requests +system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry +system.physmem.totGap 1952670553500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448191 # Categorize read packet sizes +system.physmem.readPktSize::6 448125 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 120944 # categorize write packet sizes +system.physmem.writePktSize::6 121700 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,30 +116,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes +system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 409750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests -system.physmem.totBusLat 1792536000 # Total cycles spent in databus access -system.physmem.totBankLat 6288996000 # Total cycles spent in bank access -system.physmem.avgQLat 6509.40 # Average queueing delay per request -system.physmem.avgBankLat 14033.74 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24543.14 # Average memory access latency -system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.totQLat 4798545467 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13448530467 # Sum of mem lat for all requests +system.physmem.totBusLat 2240285000 # Total cycles spent in databus access +system.physmem.totBankLat 6409700000 # Total cycles spent in bank access +system.physmem.avgQLat 10709.68 # Average queueing delay per request +system.physmem.avgBankLat 14305.55 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30015.22 # Average memory access latency +system.physmem.avgRdBW 14.69 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.94 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.51 # Average write queue length over time -system.physmem.readRowHits 428061 # Number of row buffer hits during reads -system.physmem.writeRowHits 76773 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes -system.physmem.avgGap 3430782.78 # Average gap between requests -system.l2c.replacements 341335 # number of replacements -system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use -system.l2c.total_refs 2438054 # Total number of references to valid blocks. -system.l2c.sampled_refs 406311 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.000463 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55545.332470 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4807.217204 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4686.652945 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 164.376424 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 43.456861 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.847555 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 674205 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 658217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 328581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 113535 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774538 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 791470 # number of Writeback hits -system.l2c.Writeback_hits::total 791470 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 738 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 123887 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48972 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172859 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 674205 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 782104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 328581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 162507 # number of demand (read+write) hits -system.l2c.demand_hits::total 1947397 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 674205 # number of overall hits -system.l2c.overall_hits::cpu0.data 782104 # number of overall hits -system.l2c.overall_hits::cpu1.inst 328581 # number of overall hits -system.l2c.overall_hits::cpu1.data 162507 # number of overall hits -system.l2c.overall_hits::total 1947397 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12926 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271631 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 612 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 247 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285416 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2969 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1806 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4775 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 939 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 944 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1883 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115505 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6644 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122149 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12926 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387136 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 612 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6891 # number of demand (read+write) misses -system.l2c.demand_misses::total 407565 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12926 # number of overall misses -system.l2c.overall_misses::cpu0.data 387136 # number of overall misses -system.l2c.overall_misses::cpu1.inst 612 # number of overall misses -system.l2c.overall_misses::cpu1.data 6891 # number of overall misses -system.l2c.overall_misses::total 407565 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 706675500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11506519500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 33342000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 15821000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 12262358000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1244500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10405997 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11650497 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 840000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1022000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5700012000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 427427500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6127439500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 706675500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 17206531500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 33342000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 443248500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 18389797500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 706675500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 17206531500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 33342000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 443248500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 18389797500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 687131 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 929848 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 329193 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 113782 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2059954 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 791470 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 791470 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3143 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2370 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5513 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 975 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 968 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1943 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 239392 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 55616 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295008 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 687131 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1169240 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 329193 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 169398 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2354962 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 687131 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1169240 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 329193 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 169398 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2354962 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018812 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.292124 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.001859 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002171 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138555 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944639 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.762025 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.866135 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963077 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975207 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.969120 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.482493 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.119462 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.414053 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018812 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.331101 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.001859 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.040679 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173066 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018812 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.331101 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.001859 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.040679 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173066 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 54670.857187 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 42360.847989 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54480.392157 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 64052.631579 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 42963.106483 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 419.164702 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5761.903101 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2439.894660 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 894.568690 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 192.796610 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 542.750929 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49348.616943 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64332.856713 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 50163.648495 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 54670.857187 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 44445.702544 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 54480.392157 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 64322.812364 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 45121.140186 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 54670.857187 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 44445.702544 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 54480.392157 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 64322.812364 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 45121.140186 # average overall miss latency +system.physmem.avgWrQLen 10.11 # Average write queue length over time +system.physmem.readRowHits 419119 # Number of row buffer hits during reads +system.physmem.writeRowHits 92373 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.79 # Row buffer hit rate for writes +system.physmem.avgGap 3435266.16 # Average gap between requests +system.l2c.replacements 341268 # number of replacements +system.l2c.tagsinuse 65240.270273 # Cycle average of tags in use +system.l2c.total_refs 2443367 # Total number of references to valid blocks. +system.l2c.sampled_refs 406244 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.014531 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6941595752 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55425.253207 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4870.495631 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4790.652765 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 116.277662 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 37.591009 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.845722 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.074318 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.073100 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001774 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000574 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.995488 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 687318 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 665852 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 314877 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 108330 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1776377 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 794206 # number of Writeback hits +system.l2c.Writeback_hits::total 794206 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 530 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 702 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 62 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 126888 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 47007 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 173895 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 687318 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 792740 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 314877 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 155337 # number of demand (read+write) hits +system.l2c.demand_hits::total 1950272 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 687318 # number of overall hits +system.l2c.overall_hits::cpu0.data 792740 # number of overall hits +system.l2c.overall_hits::cpu1.inst 314877 # number of overall hits +system.l2c.overall_hits::cpu1.data 155337 # number of overall hits +system.l2c.overall_hits::total 1950272 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 12972 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271609 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 561 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 240 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285382 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2946 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1731 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4677 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 877 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 894 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1771 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115472 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6625 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122097 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 12972 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387081 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 561 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6865 # number of demand (read+write) misses +system.l2c.demand_misses::total 407479 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12972 # number of overall misses +system.l2c.overall_misses::cpu0.data 387081 # number of overall misses +system.l2c.overall_misses::cpu1.inst 561 # number of overall misses +system.l2c.overall_misses::cpu1.data 6865 # number of overall misses +system.l2c.overall_misses::total 407479 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 816098500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11712193000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 36330000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 18796500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 12583418000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1197000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 9651997 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 10848997 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 863000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1045500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5538652000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 375096499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5913748499 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 816098500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 17250845000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 36330000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 393892999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 18497166499 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 816098500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 17250845000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 36330000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 393892999 # number of overall miss cycles +system.l2c.overall_miss_latency::total 18497166499 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 700290 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 937461 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 315438 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 108570 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2061759 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 794206 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 794206 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3118 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2261 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5379 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 917 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 916 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1833 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 242360 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 53632 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295992 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 700290 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1179821 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 315438 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 162202 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2357751 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 700290 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1179821 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 315438 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 162202 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2357751 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018524 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.289728 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.001778 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.002211 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.138417 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944836 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.765590 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.869492 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.956379 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975983 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.966176 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.476448 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.123527 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.412501 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018524 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.328085 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001778 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.042324 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172825 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018524 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.328085 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001778 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.042324 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172825 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 62912.311132 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 43121.520274 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64759.358289 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78318.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 44093.243442 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 406.313646 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5575.965916 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2319.648706 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 984.036488 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 204.138702 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 590.344438 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47965.324927 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 56618.339472 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 48434.838686 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 62912.311132 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 44566.499002 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 64759.358289 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 57376.984559 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 45394.158960 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 62912.311132 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 44566.499002 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 64759.358289 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 57376.984559 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 45394.158960 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,119 +379,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 78894 # number of writebacks -system.l2c.writebacks::total 78894 # number of writebacks +system.l2c.writebacks::writebacks 78774 # number of writebacks +system.l2c.writebacks::total 78774 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12926 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271631 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 601 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 247 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285405 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2969 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1806 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4775 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 939 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 944 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1883 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 115505 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6644 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122149 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12926 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387136 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 601 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6891 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407554 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12926 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387136 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 601 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6891 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407554 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 543164896 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7977851486 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 25213167 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12672975 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 8558902524 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29845964 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18081803 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 47927767 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9405923 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9440944 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 18846867 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207932893 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 343549452 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4551482345 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 543164896 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 12185784379 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 25213167 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 356222427 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 13110384869 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 543164896 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 12185784379 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 25213167 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 356222427 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 13110384869 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373080000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18172000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1391252000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2155311500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 683999000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2839310500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3528391500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 702171000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4230562500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292124 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002171 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.138549 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944639 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.762025 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.866135 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.963077 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975207 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969120 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482493 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119462 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.414053 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173062 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173062 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29370.180451 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 51307.591093 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 29988.621517 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.530818 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.072536 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.228691 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.957401 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 12972 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271609 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 550 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 240 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285371 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2946 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1731 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4677 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 877 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 894 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1771 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115472 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6625 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122097 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12972 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387081 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 550 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6865 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407468 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12972 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387081 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 550 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6865 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407468 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 652870719 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8377504856 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 28860821 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15792455 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 9075028851 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29675441 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17410227 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47085668 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8897310 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 8940894 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 17838204 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4112913546 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 291507382 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4404420928 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 652870719 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12490418402 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 28860821 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 307299837 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 13479449779 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 652870719 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12490418402 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 28860821 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 307299837 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 13479449779 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372964000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1391135500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2145152500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 673668500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2818821000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3518116500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 691840000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4209956500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.289728 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002211 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138411 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944836 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.765590 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.869492 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.956379 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975983 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966176 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476448 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.123527 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412501 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172821 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172821 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30843.988439 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65801.895833 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 31800.809651 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.130007 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.901213 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10067.493693 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10145.165336 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.957515 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36430.742332 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51708.225768 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37261.724165 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10072.390740 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35618.275824 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44001.114264 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 36073.129790 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -503,14 +503,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.562950 # Cycle average of tags in use +system.iocache.tagsinuse 0.569993 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.562950 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1746698431000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.569993 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035625 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035625 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -521,12 +521,12 @@ system.iocache.overall_misses::tsunami.ide 41728 # system.iocache.overall_misses::total 41728 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10634917806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10634917806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10656186804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10656186804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10656186804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10656186804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -545,17 +545,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255942.380776 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 255942.380776 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255372.574866 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255372.574866 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 284837 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -569,14 +569,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41728 system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -585,14 +585,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -610,22 +610,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7424685 # DTB read hits +system.cpu0.dtb.read_hits 7490982 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5011105 # DTB write hits +system.cpu0.dtb.write_hits 5068153 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12435790 # DTB hits +system.cpu0.dtb.data_hits 12559135 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3481701 # ITB hits +system.cpu0.itb.fetch_hits 3503456 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3485572 # ITB accesses +system.cpu0.itb.fetch_accesses 3507327 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,55 +638,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3900399041 # number of cpu cycles simulated +system.cpu0.numCycles 3904305293 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47350784 # Number of instructions committed -system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses -system.cpu0.num_func_calls 1188579 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43919786 # number of integer instructions -system.cpu0.num_fp_insts 206365 # number of float instructions -system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written -system.cpu0.num_mem_refs 12475691 # number of memory refs -system.cpu0.num_load_insts 7451626 # Number of load instructions -system.cpu0.num_store_insts 5024065 # Number of store instructions -system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles -system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles +system.cpu0.committedInsts 47706703 # Number of instructions committed +system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses +system.cpu0.num_func_calls 1201591 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44241786 # number of integer instructions +system.cpu0.num_fp_insts 211423 # number of float instructions +system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599388 # number of memory refs +system.cpu0.num_load_insts 7518173 # Number of load instructions +system.cpu0.num_store_insts 5081215 # Number of store instructions +system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles +system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles +system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -718,37 +718,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed -system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed +system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147588 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches +system.cpu0.kern.callpal::total 149953 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3025 # number of times the context was actually changed +system.cpu0.kern.swap_context 3075 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -780,51 +780,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 686544 # number of replacements -system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use -system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 46672235 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46672235 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46672235 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46672235 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46672235 # number of overall hits -system.cpu0.icache.overall_hits::total 46672235 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687149 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687149 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687149 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687149 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687149 # number of overall misses -system.cpu0.icache.overall_misses::total 687149 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9571696500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9571696500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9571696500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9571696500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9571696500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9571696500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359384 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47359384 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47359384 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47359384 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47359384 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47359384 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014509 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014509 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014509 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014509 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014509 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014509 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13929.579320 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13929.579320 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13929.579320 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13929.579320 # average overall miss latency +system.cpu0.icache.replacements 699703 # number of replacements +system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use +system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits +system.cpu0.icache.overall_hits::total 47014995 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses +system.cpu0.icache.overall_misses::total 700308 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9851397000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47715303 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,112 +833,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687149 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687149 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687149 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687149 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687149 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687149 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8197398500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8197398500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8197398500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8197398500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8197398500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8197398500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014509 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014509 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014509 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11929.579320 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700308 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 700308 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 700308 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 700308 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 700308 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 700308 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8450781000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8450781000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8450781000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8450781000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8450781000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8450781000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014677 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014677 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014677 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.234702 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1171731 # number of replacements -system.cpu0.dcache.tagsinuse 505.264467 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11253773 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1172148 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.600983 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.264467 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6351999 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6351999 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4607371 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4607371 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138396 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138396 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10959370 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10959370 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10959370 # number of overall hits -system.cpu0.dcache.overall_hits::total 10959370 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 933038 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 933038 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249274 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249274 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13435 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13435 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1182312 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1182312 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1182312 # number of overall misses -system.cpu0.dcache.overall_misses::total 1182312 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20824713000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 20824713000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7766651000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7766651000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144248500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 144248500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43490500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 43490500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 28591364000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28591364000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 28591364000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28591364000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285037 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7285037 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4856645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151831 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151831 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12141682 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12141682 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12141682 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12141682 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051326 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051326 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088487 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088487 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097376 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097376 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097376 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097376 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22319.254950 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22319.254950 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31157.084172 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31157.084172 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10736.769632 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10736.769632 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7588.640726 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7588.640726 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24182.588014 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24182.588014 # average overall miss latency +system.cpu0.dcache.replacements 1182211 # number of replacements +system.cpu0.dcache.tagsinuse 505.184188 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11367781 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1182629 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.612297 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.184188 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.986688 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.986688 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6409561 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6409561 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4659572 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4659572 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140562 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140562 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148239 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148239 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11069133 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11069133 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11069133 # number of overall hits +system.cpu0.dcache.overall_hits::total 11069133 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 939643 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 939643 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251886 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251886 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13649 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13649 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5418 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5418 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1191529 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1191529 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1191529 # number of overall misses +system.cpu0.dcache.overall_misses::total 1191529 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 21121102500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 21121102500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7642676000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7642676000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149168500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 149168500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 41236000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 41236000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 28763778500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 28763778500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 28763778500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 28763778500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7349204 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7349204 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4911458 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4911458 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154211 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154211 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153657 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153657 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12260662 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12260662 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12260662 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12260662 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127856 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127856 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051285 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051285 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088509 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088509 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035260 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035260 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097183 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097183 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097183 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097183 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22477.794758 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22477.794758 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30341.805420 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30341.805420 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10928.895890 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10928.895890 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7610.926541 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7610.926541 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24140.225290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24140.225290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,62 +947,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672345 # number of writebacks -system.cpu0.dcache.writebacks::total 672345 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933038 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 933038 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249274 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249274 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182312 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1182312 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182312 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks +system.cpu0.dcache.writebacks::total 680601 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13649 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5418 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5418 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191529 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1191529 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191529 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1191529 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19241816500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19241816500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7138904000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7138904000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1014,22 +1014,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2500361 # DTB read hits +system.cpu1.dtb.read_hits 2417694 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1820984 # DTB write hits +system.cpu1.dtb.write_hits 1754404 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4321345 # DTB hits +system.cpu1.dtb.data_hits 4172098 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1990033 # ITB hits +system.cpu1.itb.fetch_hits 1961503 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991249 # ITB accesses +system.cpu1.itb.fetch_accesses 1962719 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1042,51 +1042,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3901627911 # number of cpu cycles simulated +system.cpu1.numCycles 3905448539 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13632233 # Number of instructions committed -system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses -system.cpu1.num_func_calls 426713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12571690 # number of integer instructions -system.cpu1.num_fp_insts 180459 # number of float instructions -system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written -system.cpu1.num_mem_refs 4345653 # number of memory refs -system.cpu1.num_load_insts 2515108 # Number of load instructions -system.cpu1.num_store_insts 1830545 # Number of store instructions -system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles +system.cpu1.committedInsts 13160532 # Number of instructions committed +system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses +system.cpu1.num_func_calls 411397 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12141335 # number of integer instructions +system.cpu1.num_fp_insts 171917 # number of float instructions +system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written +system.cpu1.num_mem_refs 4195541 # number of memory refs +system.cpu1.num_load_insts 2431931 # Number of load instructions +system.cpu1.num_store_insts 1763610 # Number of store instructions +system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -1102,81 +1102,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed -system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed -system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed +system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed +system.cpu1.kern.callpal::rdps 2168 3.04% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3763 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73828 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches +system.cpu1.kern.callpal::total 71284 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2048 # number of protection mode switches system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 915 +system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 889 system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 450 -system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 424 +system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2086 # number of times the context was actually changed -system.cpu1.icache.replacements 328646 # number of replacements -system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use -system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 13306402 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13306402 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13306402 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13306402 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13306402 # number of overall hits -system.cpu1.icache.overall_hits::total 13306402 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 329194 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 329194 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 329194 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 329194 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 329194 # number of overall misses -system.cpu1.icache.overall_misses::total 329194 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4346536000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4346536000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4346536000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4346536000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4346536000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4346536000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635596 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13635596 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13635596 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13635596 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13635596 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13635596 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024142 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024142 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024142 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024142 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024142 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024142 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13203.569931 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13203.569931 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13203.569931 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.147427 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329931 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17784732000 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1713538500 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1933225237500 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1984 # number of times the context was actually changed +system.cpu1.icache.replacements 314891 # number of replacements +system.cpu1.icache.tagsinuse 448.025093 # Cycle average of tags in use +system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 448.025093 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.875049 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12848456 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12848456 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12848456 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12848456 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12848456 # number of overall hits +system.cpu1.icache.overall_hits::total 12848456 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 315439 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 315439 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 315439 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 315439 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 315439 # number of overall misses +system.cpu1.icache.overall_misses::total 315439 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4168917000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4168917000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13163895 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13163895 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13163895 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13163895 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13163895 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13163895 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023962 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023962 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,112 +1185,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329194 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 329194 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 329194 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 329194 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 329194 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 329194 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688148000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688148000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688148000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3688148000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688148000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3688148000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024142 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024142 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024142 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11203.569931 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315439 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 315439 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 315439 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 315439 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 315439 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 315439 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3538039000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3538039000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023962 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023962 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11216.238322 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 172801 # number of replacements -system.cpu1.dcache.tagsinuse 487.450819 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4146327 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 173313 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 23.923924 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 62292445000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.450819 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.952052 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.952052 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2329216 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2329216 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1699225 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1699225 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50220 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52927 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 52927 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4028441 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4028441 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4028441 # number of overall hits -system.cpu1.dcache.overall_hits::total 4028441 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123241 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123241 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 64769 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 64769 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9346 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9346 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6142 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6142 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 188010 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 188010 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 188010 # number of overall misses -system.cpu1.dcache.overall_misses::total 188010 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1494406500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1494406500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166606000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1166606000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85391000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 85391000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44592000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 44592000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2661012500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2661012500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2661012500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2661012500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2452457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763994 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1763994 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59566 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59566 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59069 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59069 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4216451 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4216451 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4216451 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4216451 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050252 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050252 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036717 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036717 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156902 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156902 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103980 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103980 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044590 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044590 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044590 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044590 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12125.887489 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12125.887489 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.795766 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.795766 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9136.635994 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9136.635994 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7260.175838 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7260.175838 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14153.568959 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14153.568959 # average overall miss latency +system.cpu1.dcache.replacements 165415 # number of replacements +system.cpu1.dcache.tagsinuse 486.567196 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4004380 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 165927 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.133384 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 486.567196 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.950327 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.950327 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2254351 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2254351 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1637565 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1637565 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47962 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47962 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50536 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50536 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3891916 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3891916 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3891916 # number of overall hits +system.cpu1.dcache.overall_hits::total 3891916 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 117672 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 117672 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62334 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62334 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8861 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8861 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5817 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5817 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 180006 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 180006 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 180006 # number of overall misses +system.cpu1.dcache.overall_misses::total 180006 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427906500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1427906500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1084822000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1084822000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81394000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 81394000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 42192000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 42192000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2512728500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2512728500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2512728500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2512728500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2372023 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2372023 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1699899 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1699899 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56823 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 56823 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56353 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56353 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4071922 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4071922 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4071922 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4071922 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049608 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049608 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036669 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036669 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155940 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155940 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044207 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044207 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044207 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044207 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12134.632708 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12134.632708 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17403.375365 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17403.375365 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.644961 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.644961 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7253.223311 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7253.223311 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13959.137473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13959.137473 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1299,62 +1299,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119125 # number of writebacks -system.cpu1.dcache.writebacks::total 119125 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123241 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123241 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64769 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 64769 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9346 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9346 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6142 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6142 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 188010 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 188010 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 188010 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 188010 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks +system.cpu1.dcache.writebacks::total 113605 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 117672 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62334 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5817 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5817 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 180006 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 180006 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 180006 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 180006 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1192562500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1192562500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 960154000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 960154000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63672000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63672000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30558000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30558000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2152716500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2152716500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2152716500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2152716500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 712390500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index e3ca77030..37fa2c1e1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.910582 # Number of seconds simulated -sim_ticks 1910582068000 # Number of ticks simulated -final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.910548 # Number of seconds simulated +sim_ticks 1910547559000 # Number of ticks simulated +final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 951839 # Simulator instruction rate (inst/s) -host_op_rate 951839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32401800424 # Simulator tick rate (ticks/s) -host_mem_usage 374212 # Number of bytes of host memory used -host_seconds 58.97 # Real time elapsed on the host -sim_insts 56125446 # Number of instructions simulated -sim_ops 56125446 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +host_inst_rate 1284259 # Simulator instruction rate (inst/s) +host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43720523895 # Simulator tick rate (ticks/s) +host_mem_usage 330356 # Number of bytes of host memory used +host_seconds 43.70 # Real time elapsed on the host +sim_insts 56120911 # Number of instructions simulated +sim_ops 56120911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory -system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442975 # Total number of read requests seen -system.physmem.writeReqs 115503 # Total number of write requests seen -system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28350400 # Total number of bytes read from memory -system.physmem.bytesWritten 7392192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q +system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443146 # Total number of read requests seen +system.physmem.writeReqs 115693 # Total number of write requests seen +system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28361344 # Total number of bytes read from memory +system.physmem.bytesWritten 7404352 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27656 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7244 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7584 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7257 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7126 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7126 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27733 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27564 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7067 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7113 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 404 # Number of times wr buffer was full causing retry -system.physmem.totGap 1910570168000 # Total gap between requests +system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry +system.physmem.totGap 1910535659000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 442975 # Categorize read packet sizes +system.physmem.readPktSize::6 443146 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 115907 # categorize write packet sizes +system.physmem.writePktSize::6 117758 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -109,27 +109,27 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 130 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 404639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 402456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -142,69 +142,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2804911869 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10779125869 # Sum of mem lat for all requests -system.physmem.totBusLat 1771696000 # Total cycles spent in databus access -system.physmem.totBankLat 6202518000 # Total cycles spent in bank access -system.physmem.avgQLat 6332.72 # Average queueing delay per request -system.physmem.avgBankLat 14003.57 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24336.29 # Average memory access latency +system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests +system.physmem.totBusLat 2215505000 # Total cycles spent in databus access +system.physmem.totBankLat 6296675000 # Total cycles spent in bank access +system.physmem.avgQLat 10647.84 # Average queueing delay per request +system.physmem.avgBankLat 14210.47 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29858.31 # Average memory access latency system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.48 # Average write queue length over time -system.physmem.readRowHits 423327 # Number of row buffer hits during reads -system.physmem.writeRowHits 74914 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.86 # Row buffer hit rate for writes -system.physmem.avgGap 3421030.31 # Average gap between requests +system.physmem.avgWrQLen 11.47 # Average write queue length over time +system.physmem.readRowHits 415807 # Number of row buffer hits during reads +system.physmem.writeRowHits 89941 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes +system.physmem.avgGap 3418758.64 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.342666 # Cycle average of tags in use +system.iocache.tagsinuse 1.342284 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745691885000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.342666 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083917 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083917 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083893 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083893 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9475235806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9475235806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9496163804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9496163804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9496163804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9496163804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10644331806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10644331806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10665259804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10665259804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10665259804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10665259804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228033.206729 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228033.206729 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 189601 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256168.940268 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23064 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27152 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.220647 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.497496 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7324399500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7324399500 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8494267359 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8494267359 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175983.550732 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 175983.550732 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9055970 # DTB read hits +system.cpu.dtb.read_hits 9055197 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6351685 # DTB write hits +system.cpu.dtb.write_hits 6350929 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15407655 # DTB hits +system.cpu.dtb.data_hits 15406126 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974178 # ITB hits +system.cpu.itb.fetch_hits 4974131 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979184 # ITB accesses +system.cpu.itb.fetch_accesses 4979137 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,51 +332,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3821164136 # number of cpu cycles simulated +system.cpu.numCycles 3821095118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56125446 # Number of instructions committed -system.cpu.committedOps 56125446 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51999916 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1482010 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6463546 # number of instructions that are conditional controls -system.cpu.num_int_insts 51999916 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read -system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15460271 # number of memory refs -system.cpu.num_load_insts 9092827 # Number of load instructions -system.cpu.num_store_insts 6367444 # Number of store instructions -system.cpu.num_idle_cycles 3587332264.998123 # Number of idle cycles -system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles -system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.938806 # Percentage of idle cycles +system.cpu.committedInsts 56120911 # Number of instructions committed +system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1481756 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls +system.cpu.num_int_insts 51995405 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read +system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15458726 # number of memory refs +system.cpu.num_load_insts 9092044 # Number of load instructions +system.cpu.num_store_insts 6366682 # Number of store instructions +system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles +system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles +system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.938773 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211969 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149111 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91164500 0.00% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736454000 0.04% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 53835630000 2.82% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1910581334000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -412,10 +412,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175936 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -424,21 +424,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192878 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323843 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192879 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches +system.cpu.kern.mode_switch::user 1744 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 +system.cpu.kern.mode_good::user 1744 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.324237 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392483 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45587423000 2.39% 2.39% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5075517000 0.27% 2.65% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392853 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45393996500 2.38% 2.38% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5132973000 0.27% 2.64% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1860019853500 97.36% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -470,51 +470,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927460 # number of replacements -system.cpu.icache.tagsinuse 509.121498 # Cycle average of tags in use -system.cpu.icache.total_refs 55209154 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 927971 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.494482 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 32120759000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.121498 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.994378 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.994378 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55209154 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55209154 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55209154 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55209154 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55209154 # number of overall hits -system.cpu.icache.overall_hits::total 55209154 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928131 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928131 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928131 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928131 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928131 # number of overall misses -system.cpu.icache.overall_misses::total 928131 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12666318500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12666318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12666318500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12666318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12666318500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12666318500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56137285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56137285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56137285 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56137285 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56137285 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56137285 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016533 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016533 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016533 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016533 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13647.123628 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13647.123628 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13647.123628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13647.123628 # average overall miss latency +system.cpu.icache.replacements 927816 # number of replacements +system.cpu.icache.tagsinuse 509.100001 # Cycle average of tags in use +system.cpu.icache.total_refs 55204264 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 928327 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.466399 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 32331359000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.100001 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.994336 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.994336 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55204264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55204264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55204264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55204264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55204264 # number of overall hits +system.cpu.icache.overall_hits::total 55204264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928486 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928486 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928486 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928486 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928486 # number of overall misses +system.cpu.icache.overall_misses::total 928486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12769098000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12769098000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12769098000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12769098000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12769098000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12769098000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56132750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56132750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56132750 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56132750 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56132750 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56132750 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016541 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016541 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016541 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016541 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016541 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016541 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13752.601547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13752.601547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13752.601547 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,126 +523,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928131 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928131 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928131 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928131 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928131 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928131 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10810056500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10810056500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10810056500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10810056500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10810056500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10810056500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016533 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016533 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016533 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11647.123628 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11647.123628 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928486 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928486 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928486 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928486 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928486 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928486 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10912126000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10912126000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10912126000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10912126000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10912126000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10912126000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016541 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016541 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016541 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11752.601547 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11752.601547 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11752.601547 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11752.601547 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11752.601547 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11752.601547 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 336061 # number of replacements -system.cpu.l2cache.tagsinuse 65323.847661 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2445310 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401224 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.094625 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 5214408002 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55704.521339 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4784.646064 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4834.680258 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.849984 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073008 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.073771 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.996763 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 914821 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814177 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1728998 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 834403 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834403 # number of Writeback hits +system.cpu.l2cache.replacements 336232 # number of replacements +system.cpu.l2cache.tagsinuse 65320.349460 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2445455 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 401395 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.092390 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 5253905752 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 55746.369541 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4781.447334 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4792.532585 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.850622 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.072959 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.073128 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.996709 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 915175 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 814009 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1729184 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 834499 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 834499 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187505 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187505 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 914821 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001682 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1916503 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 914821 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1001682 # number of overall hits -system.cpu.l2cache.overall_hits::total 1916503 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271922 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285212 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187516 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187516 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 915175 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1001525 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1916700 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 915175 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1001525 # number of overall hits +system.cpu.l2cache.overall_hits::total 1916700 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 271961 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 285252 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116710 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116710 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388632 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 401922 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388632 # number of overall misses -system.cpu.l2cache.overall_misses::total 401922 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 733695500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11538737000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12272432500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 116841 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116841 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13291 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388802 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 402093 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13291 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388802 # number of overall misses +system.cpu.l2cache.overall_misses::total 402093 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831870000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11715487000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12547357000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 189500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 189500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5810363500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5810363500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 733695500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17349100500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18082796000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 733695500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17349100500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18082796000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 928111 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1086099 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2014210 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 834403 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 834403 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5599308500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5599308500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 831870000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17314795500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18146665500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 831870000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17314795500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18146665500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 928466 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1085970 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2014436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 834499 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 834499 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304215 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304215 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 928111 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390314 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2318425 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 928111 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390314 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2318425 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014319 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250366 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141600 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304357 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304357 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 928466 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390327 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2318793 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 928466 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390327 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2318793 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014315 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250431 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141604 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383643 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383643 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014319 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279528 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173360 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014319 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279528 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173360 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55206.583898 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 42433.995778 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 43029.159012 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383895 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383895 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014315 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279648 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173406 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014315 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279648 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173406 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62588.969980 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43077.819982 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 43986.920337 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49784.624282 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49784.624282 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55206.583898 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44641.461588 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 44990.809162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55206.583898 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44641.461588 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 44990.809162 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47922.463005 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47922.463005 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62588.969980 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44533.709960 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 45130.518313 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62588.969980 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44533.709960 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 45130.518313 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -651,66 +651,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 73991 # number of writebacks -system.cpu.l2cache.writebacks::total 73991 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271922 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285212 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks +system.cpu.l2cache.writebacks::total 74181 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271961 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285252 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116710 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116710 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388632 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401922 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388632 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401922 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 561273079 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8004831581 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8566104660 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116841 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116841 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388802 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388802 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402093 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666952085 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8376868075 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9043820160 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4294420630 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4294420630 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 561273079 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12299252211 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12860525290 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 561273079 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229367500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229367500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4162858124 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4162858124 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666952085 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12539726199 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13206678284 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666952085 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12539726199 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13206678284 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229366500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229366500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250431 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141604 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279528 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173360 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279528 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173360 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42232.737321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29437.969642 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30034.166374 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173406 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173406 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50180.730193 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30801.725523 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31704.668714 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36795.652729 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36795.652729 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42232.737321 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31647.554013 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31997.564926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42232.737321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31647.554013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31997.564926 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35628.402051 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35628.402051 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50180.730193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32252.216293 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32844.835110 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50180.730193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32252.216293 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32844.835110 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -718,79 +718,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1389800 # number of replacements -system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use -system.cpu.dcache.total_refs 14036386 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1390312 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.095853 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.980808 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1389814 # number of replacements +system.cpu.dcache.tagsinuse 511.980842 # Cycle average of tags in use +system.cpu.dcache.total_refs 14034828 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1390326 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.094631 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.980842 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5847887 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183020 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183020 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13654126 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13654126 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13654126 # number of overall hits -system.cpu.dcache.overall_hits::total 13654126 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1068876 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1068876 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304232 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304232 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17223 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373108 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373108 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373108 # number of overall misses -system.cpu.dcache.overall_misses::total 1373108 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22711107000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22711107000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8598536500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8598536500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227697000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 227697000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31309643500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31309643500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31309643500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31309643500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8875115 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8875115 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152119 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152119 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15027234 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15027234 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15027234 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15027234 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120435 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120435 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049452 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049452 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086010 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086010 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091375 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091375 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091375 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091375 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21247.653610 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28263.090339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13220.519073 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22802.025405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22802.025405 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 7805620 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7805620 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5846988 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5846988 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182985 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182985 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199218 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199218 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13652608 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13652608 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13652608 # number of overall hits +system.cpu.dcache.overall_hits::total 13652608 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1068716 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1068716 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304374 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304374 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17254 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17254 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373090 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373090 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373090 # number of overall misses +system.cpu.dcache.overall_misses::total 1373090 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22883646000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22883646000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8388017500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8388017500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229841000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229841000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31271663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31271663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31271663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31271663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8874336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8874336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15025698 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15025698 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15025698 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15025698 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120428 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120428 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049481 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049481 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21412.279782 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21412.279782 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27558.258918 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27558.258918 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13321.027008 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22774.664079 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,54 +799,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks -system.cpu.dcache.writebacks::total 834403 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373108 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373108 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20573355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20573355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7990072500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7990072500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193251000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193251000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28563427500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28563427500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks +system.cpu.dcache.writebacks::total 834499 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304374 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304374 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17254 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17254 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373090 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373090 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373090 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373090 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20746214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20746214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7779269500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7779269500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195333000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195333000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28525483500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28525483500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28525483500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28525483500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 5fe42fc21..839e0acab 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -215,7 +215,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index bc1e2b029..9811be55f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -198,7 +198,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index ebe1b98fa..13c85b6d1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.182882 # Number of seconds simulated -sim_ticks 1182882156500 # Number of ticks simulated -final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.183003 # Number of seconds simulated +sim_ticks 1183003114000 # Number of ticks simulated +final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 497131 # Simulator instruction rate (inst/s) -host_op_rate 633435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9569364300 # Simulator tick rate (ticks/s) -host_mem_usage 452888 # Number of bytes of host memory used -host_seconds 123.61 # Real time elapsed on the host -sim_insts 61450993 # Number of instructions simulated -sim_ops 78299715 # Number of ops (including micro ops) simulated +host_inst_rate 673901 # Simulator instruction rate (inst/s) +host_op_rate 858757 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12970235901 # Simulator tick rate (ticks/s) +host_mem_usage 408748 # Number of bytes of host memory used +host_seconds 91.21 # Real time elapsed on the host +sim_insts 61465824 # Number of instructions simulated +sim_ops 78326377 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory -system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory +system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory +system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654451 # Total number of read requests seen -system.physmem.writeReqs 821128 # Total number of write requests seen -system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425884864 # Total number of bytes read from memory -system.physmem.bytesWritten 52552192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654023 # Total number of read requests seen +system.physmem.writeReqs 820738 # Total number of write requests seen +system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425857472 # Total number of bytes read from memory +system.physmem.bytesWritten 52527232 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182877668000 # Total gap between requests +system.physmem.totGap 1182998675500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159562 # Categorize read packet sizes +system.physmem.readPktSize::6 159134 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,7 +125,7 @@ system.physmem.writePktSize::2 756836 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 64292 # categorize write packet sizes +system.physmem.writePktSize::6 63902 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,26 +134,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -170,60 +170,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 123719908904 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 159121708904 # Sum of mem lat for all requests -system.physmem.totBusLat 26617276000 # Total cycles spent in databus access -system.physmem.totBankLat 8784524000 # Total cycles spent in bank access -system.physmem.avgQLat 18592.42 # Average queueing delay per request -system.physmem.avgBankLat 1320.12 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23912.55 # Average memory access latency -system.physmem.avgRdBW 360.04 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.54 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.53 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 15.12 # Average write queue length over time -system.physmem.readRowHits 6628163 # Number of row buffer hits during reads -system.physmem.writeRowHits 789308 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.12 # Row buffer hit rate for writes -system.physmem.avgGap 158232.25 # Average gap between requests +system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests +system.physmem.totBusLat 33269555000 # Total cycles spent in databus access +system.physmem.totBankLat 9041986250 # Total cycles spent in bank access +system.physmem.avgQLat 22090.22 # Average queueing delay per request +system.physmem.avgBankLat 1358.90 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28449.12 # Average memory access latency +system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.16 # Average read queue length over time +system.physmem.avgWrQLen 12.54 # Average write queue length over time +system.physmem.readRowHits 6611960 # Number of row buffer hits during reads +system.physmem.writeRowHits 800133 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.49 # Row buffer hit rate for writes +system.physmem.avgGap 158265.75 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -242,237 +242,237 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69442 # number of replacements -system.l2c.tagsinuse 53039.972087 # Cycle average of tags in use -system.l2c.total_refs 1672967 # Total number of references to valid blocks. -system.l2c.sampled_refs 134589 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.430191 # Average number of references to valid blocks. +system.l2c.replacements 69015 # number of replacements +system.l2c.tagsinuse 53041.665406 # Cycle average of tags in use +system.l2c.total_refs 1678594 # Total number of references to valid blocks. +system.l2c.sampled_refs 134211 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.507127 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40188.045356 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000405 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001414 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3727.182104 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4237.001170 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.742163 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2823.633866 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2061.365608 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613221 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40191.767552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.003100 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3723.993423 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4235.450091 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.742043 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2826.235882 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2061.472909 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.613278 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056872 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064652 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056824 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064628 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031454 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809326 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4055 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1843 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 206158 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5342 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1844 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143311 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1246376 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571308 # number of Writeback hits -system.l2c.Writeback_hits::total 571308 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1277 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1841 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 215 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56678 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52482 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109160 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4055 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1843 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419673 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262836 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5342 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1844 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464150 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 195793 # number of demand (read+write) hits -system.l2c.demand_hits::total 1355536 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4055 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1843 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419673 # number of overall hits -system.l2c.overall_hits::cpu0.data 262836 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5342 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1844 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464150 # number of overall hits -system.l2c.overall_hits::cpu1.data 195793 # number of overall hits -system.l2c.overall_hits::total 1355536 # number of overall hits +system.l2c.occ_percent::cpu1.inst 0.043125 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.031456 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.809352 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 3013 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1662 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 349398 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169915 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6389 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 534803 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 180813 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1247936 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 573205 # number of Writeback hits +system.l2c.Writeback_hits::total 573205 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1121 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 611 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1732 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 229 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 78 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47508 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 62580 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3013 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1662 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 349398 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 217423 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6389 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 534803 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 243393 # number of demand (read+write) hits +system.l2c.demand_hits::total 1358024 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 3013 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1662 # number of overall hits +system.l2c.overall_hits::cpu0.inst 349398 # number of overall hits +system.l2c.overall_hits::cpu0.data 217423 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6389 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits +system.l2c.overall_hits::cpu1.inst 534803 # number of overall hits +system.l2c.overall_hits::cpu1.data 243393 # number of overall hits +system.l2c.overall_hits::total 1358024 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5736 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7863 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5520 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7838 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3621 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22271 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4685 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3595 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8280 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 469 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1033 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67153 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72577 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139730 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 5255 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3644 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22265 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3583 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4723 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8306 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 461 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1032 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63840 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 75452 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139292 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5736 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75016 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5520 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 71678 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76198 # number of demand (read+write) misses -system.l2c.demand_misses::total 162001 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5255 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 79096 # number of demand (read+write) misses +system.l2c.demand_misses::total 161557 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5736 # number of overall misses -system.l2c.overall_misses::cpu0.data 75016 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5520 # number of overall misses +system.l2c.overall_misses::cpu0.data 71678 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses -system.l2c.overall_misses::cpu1.data 76198 # number of overall misses -system.l2c.overall_misses::total 162001 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5255 # number of overall misses +system.l2c.overall_misses::cpu1.data 79096 # number of overall misses +system.l2c.overall_misses::total 161557 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 67500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 282793000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 402090500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 151500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 286631500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 416021500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 256949000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 210391000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1152607500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 12566496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 11726999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24293495 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1712000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2362500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4074500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 2978330461 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3439869494 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6418199955 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 290826000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 222550500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1216497500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 10882997 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 13761999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 24644996 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1755500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2248500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4004000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 2848043983 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3574373499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6422417482 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 67500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 282793000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3380420961 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 151500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 286631500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3264065483 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 256949000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3650260494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7570807455 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 290826000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3796923999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7638914982 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 67500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 282793000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3380420961 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 151500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 286631500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3264065483 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 256949000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3650260494 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7570807455 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4056 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1845 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 425409 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 214021 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5346 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1844 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 469194 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 146932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1268647 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 571308 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 571308 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5962 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4159 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10121 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 573 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1352 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123831 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 125059 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 248890 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4056 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 425409 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337852 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5346 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1844 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 469194 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 271991 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1517537 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4056 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1845 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 425409 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337852 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5346 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1844 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 469194 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 271991 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1517537 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000247 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001084 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013483 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036739 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000748 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024644 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017555 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785810 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.864390 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.818101 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.724005 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.818499 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.764053 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.542296 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.580342 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.561413 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000247 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001084 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013483 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.222038 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000748 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.280149 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.106753 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000247 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001084 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013483 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.222038 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000748 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.280149 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.106753 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.inst 290826000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3796923999 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7638914982 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 3014 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1665 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 354918 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 177753 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 6393 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1943 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 540058 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 184457 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1270201 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 573205 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 573205 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 4704 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5334 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10038 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 800 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 539 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1339 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111348 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 138032 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249380 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 3014 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1665 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 354918 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 289101 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 6393 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1943 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 540058 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 322489 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1519581 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 3014 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1665 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 354918 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 289101 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 6393 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1943 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 540058 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 322489 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1519581 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001802 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015553 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.044095 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009730 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.019755 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017529 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.761692 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.885452 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.827456 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.713750 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.855288 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.770724 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.573338 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.546627 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.558553 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001802 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015553 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.247934 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009730 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.245267 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.106317 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001802 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015553 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.247934 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009730 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.245267 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.106317 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 33750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49301.429568 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 51137.034211 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 50500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51925.996377 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 53077.507017 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 50941.514671 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 58103.010218 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 51753.738045 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2682.283031 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3262.030320 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2933.996981 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3035.460993 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5037.313433 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3944.336883 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44351.413355 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47396.137812 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 45932.870214 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55342.721218 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 61073.133919 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 54637.210869 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3037.397991 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2913.825746 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2967.131712 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3074.430823 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4877.440347 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3879.844961 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44612.217779 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47372.813166 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 46107.583221 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 49301.429568 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 45062.666111 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 50941.514671 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 47904.938371 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 46733.090876 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 47283.095019 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 49301.429568 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 45062.666111 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 50941.514671 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 47904.938371 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 46733.090876 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 47283.095019 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,8 +481,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64292 # number of writebacks -system.l2c.writebacks::total 64292 # number of writebacks +system.l2c.writebacks::writebacks 63902 # number of writebacks +system.l2c.writebacks::total 63902 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -490,150 +490,150 @@ system.l2c.demand_mshr_hits::total 1 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5735 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7863 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5519 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7838 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3621 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22270 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4685 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3595 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8280 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 469 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1033 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67153 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72577 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139730 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5255 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3644 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22264 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 3583 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4723 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8306 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 571 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 461 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1032 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63840 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 75452 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139292 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5735 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75016 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5519 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 71678 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 76198 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162000 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5255 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 79096 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 161556 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5735 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75016 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5519 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 71678 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 76198 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162000 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 42004 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 209968387 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 301307132 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 196008 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 192920490 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 164158147 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 868648170 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47014106 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36048563 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 83062669 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5661057 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4707461 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10368518 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2133484234 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2513381312 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4646865546 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 42004 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 209968387 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2434791366 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 196008 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 192920490 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2677539459 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5515513716 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 42004 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 209968387 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2434791366 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 196008 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 192920490 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2677539459 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5515513716 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 197971583 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12453767609 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3031674 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154319820043 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166974590909 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000478250 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214527645 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9215005895 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 197971583 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13454245859 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3031674 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162534347688 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 176189596804 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036739 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024644 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017554 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785810 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.864390 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818101 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.818499 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764053 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542296 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.580342 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561413 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222038 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.280149 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.106752 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222038 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.280149 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.106752 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38319.614905 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45335.030931 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39005.306242 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.027962 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.416690 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.723309 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.335106 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.230277 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10037.287512 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31770.497729 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34630.548411 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33256.033393 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu1.inst 5255 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 79096 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 161556 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56252 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 113756 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 217401709 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 318301323 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 197508 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 225003397 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 176993433 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 938067378 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 35910048 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47375165 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 83285213 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5731560 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4624957 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10356517 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2039757737 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2629528179 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4669285916 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 113756 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 217401709 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2358059060 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197508 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 225003397 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2806521612 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5607353294 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56252 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 113756 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 217401709 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2358059060 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197508 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 225003397 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2806521612 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5607353294 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209640082 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11218408858 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3082174 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155565109792 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166996240906 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 994820748 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214915040 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9209735788 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209640082 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12213229606 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082174 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 163780024832 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176205976694 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044095 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019755 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017528 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.761692 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.885452 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.827456 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.713750 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.855288 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770724 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573338 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.546627 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.558553 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106316 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106316 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40610.018244 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48571.194566 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42133.820428 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.341055 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.735761 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.114496 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.758319 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.444685 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.384690 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31951.092372 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34850.344312 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33521.565603 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -656,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070111 # DTB read hits -system.cpu0.dtb.read_misses 3764 # DTB read misses -system.cpu0.dtb.write_hits 5656042 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses +system.cpu0.dtb.read_hits 5883553 # DTB read hits +system.cpu0.dtb.read_misses 2148 # DTB read misses +system.cpu0.dtb.write_hits 4842455 # DTB write hits +system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073875 # DTB read accesses -system.cpu0.dtb.write_accesses 5656846 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 5885701 # DTB read accesses +system.cpu0.dtb.write_accesses 4842860 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12726153 # DTB hits -system.cpu0.dtb.misses 4568 # DTB misses -system.cpu0.dtb.accesses 12730721 # DTB accesses -system.cpu0.itb.inst_hits 29570310 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.dtb.hits 10726008 # DTB hits +system.cpu0.dtb.misses 2553 # DTB misses +system.cpu0.dtb.accesses 10728561 # DTB accesses +system.cpu0.itb.inst_hits 24779849 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -685,86 +685,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses -system.cpu0.itb.hits 29570310 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29572515 # DTB accesses -system.cpu0.numCycles 2365764313 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses +system.cpu0.itb.hits 24779849 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 24781199 # DTB accesses +system.cpu0.numCycles 2364565551 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28872367 # Number of instructions committed -system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33098187 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241715 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373222 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33098187 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13394441 # number of memory refs -system.cpu0.num_load_insts 7407672 # Number of load instructions -system.cpu0.num_store_insts 5986769 # Number of store instructions -system.cpu0.num_idle_cycles 2224997657.358119 # Number of idle cycles -system.cpu0.num_busy_cycles 140766655.641881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059502 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940498 # Percentage of idle cycles +system.cpu0.committedInsts 24381823 # Number of instructions committed +system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses +system.cpu0.num_func_calls 1070639 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28075203 # number of integer instructions +system.cpu0.num_fp_insts 4364 # number of float instructions +system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read +system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written +system.cpu0.num_mem_refs 11318426 # number of memory refs +system.cpu0.num_load_insts 6163151 # Number of load instructions +system.cpu0.num_store_insts 5155275 # Number of store instructions +system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles +system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed -system.cpu0.icache.replacements 425445 # number of replacements -system.cpu0.icache.tagsinuse 509.616014 # Cycle average of tags in use -system.cpu0.icache.total_refs 29144335 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 425957 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.420838 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995344 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29144335 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29144335 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29144335 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29144335 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29144335 # number of overall hits -system.cpu0.icache.overall_hits::total 29144335 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses -system.cpu0.icache.overall_misses::total 425958 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5792188000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5792188000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5792188000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5792188000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5792188000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5792188000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570293 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29570293 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29570293 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29570293 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29570293 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29570293 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.026096 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13598.026096 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13598.026096 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13598.026096 # average overall miss latency +system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed +system.cpu0.icache.replacements 354669 # number of replacements +system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use +system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits +system.cpu0.icache.overall_hits::total 24424650 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses +system.cpu0.icache.overall_misses::total 355182 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,120 +773,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425958 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425958 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425958 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425958 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425958 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425958 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4940272000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4940272000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4940272000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4940272000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4940272000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4940272000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288882000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 288882000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11598.026096 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355182 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 355182 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 355182 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 355182 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 355182 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 355182 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4166869500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4166869500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4166869500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4166869500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4166869500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4166869500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014334 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014334 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014334 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11731.646029 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330355 # number of replacements -system.cpu0.dcache.tagsinuse 453.331528 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12270860 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 330867 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.086987 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 453.331528 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.885413 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.885413 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6599943 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6599943 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5351121 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5351121 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147941 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147941 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149661 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149661 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11951064 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11951064 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11951064 # number of overall hits -system.cpu0.dcache.overall_hits::total 11951064 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227863 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227863 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141515 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141515 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9301 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9301 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369378 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369378 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369378 # number of overall misses -system.cpu0.dcache.overall_misses::total 369378 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3130112000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3130112000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4103795500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4103795500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87984000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 87984000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44508500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44508500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 7233907500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7233907500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7233907500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7233907500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827806 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6827806 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5492636 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5492636 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157242 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157242 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157153 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157153 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12320442 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12320442 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12320442 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12320442 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033373 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033373 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047673 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047673 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029981 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029981 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029981 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029981 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13736.815543 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13736.815543 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28999.014239 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 28999.014239 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9459.627997 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9459.627997 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5940.803524 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5940.803524 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19584.023683 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19584.023683 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19584.023683 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19584.023683 # average overall miss latency +system.cpu0.dcache.replacements 279602 # number of replacements +system.cpu0.dcache.tagsinuse 452.516720 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10326636 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 279931 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 130225 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10049347 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10049347 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10049347 # number of overall hits +system.cpu0.dcache.overall_hits::total 10049347 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 191756 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 191756 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 126522 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 126522 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8645 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8645 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7703 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7703 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 318278 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 318278 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 318278 # number of overall misses +system.cpu0.dcache.overall_misses::total 318278 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2678719000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 2678719000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3810145000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 3810145000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 78655500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 78655500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45606000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45606000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 6488864000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 6488864000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6488864000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 6488864000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5669311 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5669311 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4698314 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4698314 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138005 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 138005 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137928 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 137928 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10367625 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10367625 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10367625 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10367625 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033824 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033824 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062643 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062643 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.055848 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.055848 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030699 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030699 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030699 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030699 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13969.414256 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13969.414256 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30114.486018 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30114.486018 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306206 # number of writebacks -system.cpu0.dcache.writebacks::total 306206 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227863 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227863 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141515 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141515 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9301 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9301 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369378 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369378 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369378 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369378 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2674386000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2674386000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3820765500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3820765500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69382000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69382000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29532500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks +system.cpu0.dcache.writebacks::total 257540 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6495151500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6495151500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6495151500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6495151500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,27 +964,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8310545 # DTB read hits -system.cpu1.dtb.read_misses 3643 # DTB read misses -system.cpu1.dtb.write_hits 5827351 # DTB write hits -system.cpu1.dtb.write_misses 1434 # DTB write misses +system.cpu1.dtb.read_hits 9504194 # DTB read hits +system.cpu1.dtb.read_misses 5263 # DTB read misses +system.cpu1.dtb.write_hits 6646220 # DTB write hits +system.cpu1.dtb.write_misses 1833 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8314188 # DTB read accesses -system.cpu1.dtb.write_accesses 5828785 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 9509457 # DTB read accesses +system.cpu1.dtb.write_accesses 6648053 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14137896 # DTB hits -system.cpu1.dtb.misses 5077 # DTB misses -system.cpu1.dtb.accesses 14142973 # DTB accesses -system.cpu1.itb.inst_hits 33189113 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.dtb.hits 16150414 # DTB hits +system.cpu1.dtb.misses 7096 # DTB misses +system.cpu1.dtb.accesses 16157510 # DTB accesses +system.cpu1.itb.inst_hits 37994467 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -993,86 +993,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses -system.cpu1.itb.hits 33189113 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33191284 # DTB accesses -system.cpu1.numCycles 2364318212 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses +system.cpu1.itb.hits 37994467 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 37997484 # DTB accesses +system.cpu1.numCycles 2366006228 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32578626 # Number of instructions committed -system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962009 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37313171 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14675641 # number of memory refs -system.cpu1.num_load_insts 8632449 # Number of load instructions -system.cpu1.num_store_insts 6043192 # Number of store instructions -system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles -system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles -system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles +system.cpu1.committedInsts 37084001 # Number of instructions committed +system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1133542 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls +system.cpu1.num_int_insts 42360540 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read +system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 16764021 # number of memory refs +system.cpu1.num_load_insts 9884261 # Number of load instructions +system.cpu1.num_store_insts 6879760 # Number of store instructions +system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles +system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles +system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed -system.cpu1.icache.replacements 469194 # number of replacements -system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use -system.cpu1.icache.total_refs 32719403 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.783096 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32719403 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32719403 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32719403 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32719403 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32719403 # number of overall hits -system.cpu1.icache.overall_hits::total 32719403 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469706 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469706 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469706 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469706 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469706 # number of overall misses -system.cpu1.icache.overall_misses::total 469706 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6343605000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6343605000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6343605000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6343605000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189109 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33189109 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33189109 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33189109 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33189109 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33189109 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014152 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014152 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014152 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014152 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014152 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014152 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13505.480024 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13505.480024 # average overall miss latency +system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed +system.cpu1.icache.replacements 540342 # number of replacements +system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use +system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits +system.cpu1.icache.overall_hits::total 37453609 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses +system.cpu1.icache.overall_misses::total 540854 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,120 +1081,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469706 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 469706 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 469706 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 469706 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 469706 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 469706 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5404193000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5404193000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5404193000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5404193000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5404193000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5404193000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014152 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014152 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014152 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11505.480024 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 540854 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 540854 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 540854 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 540854 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 540854 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 540854 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6219845500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6219845500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6219845500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6219845500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6219845500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6219845500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4396000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4396000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4396000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 4396000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014235 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014235 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014235 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11500.045299 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 292054 # number of replacements -system.cpu1.dcache.tagsinuse 471.972808 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11961234 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292426 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.903456 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 83625409000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 471.972808 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.921822 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.921822 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6946091 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6946091 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4827134 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4827134 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81752 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81752 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82714 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82714 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11773225 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11773225 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11773225 # number of overall hits -system.cpu1.dcache.overall_hits::total 11773225 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170515 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170515 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 149924 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 149924 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11068 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11068 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10031 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10031 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320439 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320439 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320439 # number of overall misses -system.cpu1.dcache.overall_misses::total 320439 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2149232000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2149232000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4527081500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4527081500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92245500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 92245500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51683000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 51683000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6676313500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6676313500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6676313500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6676313500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7116606 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7116606 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977058 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4977058 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92820 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 92820 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92745 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92745 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12093664 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12093664 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12093664 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12093664 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023960 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023960 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030123 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030123 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119242 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119242 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108157 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108157 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026496 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026496 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026496 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026496 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12604.357388 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12604.357388 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30195.842560 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30195.842560 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8334.432598 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8334.432598 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5152.327784 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5152.327784 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20834.896813 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20834.896813 # average overall miss latency +system.cpu1.dcache.replacements 343957 # number of replacements +system.cpu1.dcache.tagsinuse 473.088021 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13916365 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 344469 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 83709904000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 473.088021 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.924000 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.924000 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8074934 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8074934 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5611325 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5611325 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100335 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 100335 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102214 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 102214 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 13686259 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 13686259 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 13686259 # number of overall hits +system.cpu1.dcache.overall_hits::total 13686259 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 207178 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 207178 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 165249 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 165249 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11790 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11790 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9834 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9834 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 372427 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 372427 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 372427 # number of overall misses +system.cpu1.dcache.overall_misses::total 372427 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2639135500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2639135500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4834942000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4834942000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 103120000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 103120000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50505000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50505000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7474077500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7474077500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7474077500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7474077500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8282112 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8282112 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5776574 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5776574 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112125 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 112125 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112048 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 112048 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14058686 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14058686 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14058686 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14058686 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.025015 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.025015 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.105151 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.105151 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087766 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087766 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026491 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026491 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026491 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026491 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12738.492987 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12738.492987 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29258.525014 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 29258.525014 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8746.395250 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8746.395250 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5135.753508 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5135.753508 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20068.570485 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20068.570485 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1203,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks -system.cpu1.dcache.writebacks::total 265102 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10026 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10026 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320439 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320439 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320439 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320439 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1808202000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1808202000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4227233500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4227233500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70109500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70109500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31633000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31633000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks +system.cpu1.dcache.writebacks::total 315665 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b72126c20..73585121b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603635 # Number of seconds simulated -sim_ticks 2603634694000 # Number of ticks simulated -final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603665 # Number of seconds simulated +sim_ticks 2603664815000 # Number of ticks simulated +final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 413538 # Simulator instruction rate (inst/s) -host_op_rate 526220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17886148072 # Simulator tick rate (ticks/s) -host_mem_usage 448796 # Number of bytes of host memory used -host_seconds 145.57 # Real time elapsed on the host -sim_insts 60197457 # Number of instructions simulated -sim_ops 76600355 # Number of ops (including micro ops) simulated +host_inst_rate 536000 # Simulator instruction rate (inst/s) +host_op_rate 682052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23183028791 # Simulator tick rate (ticks/s) +host_mem_usage 404656 # Number of bytes of host memory used +host_seconds 112.31 # Real time elapsed on the host +sim_insts 60197643 # Number of instructions simulated +sim_ops 76600583 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory -system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory +system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494095 # Total number of read requests seen -system.physmem.writeReqs 811481 # Total number of write requests seen -system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991622080 # Total number of bytes read from memory -system.physmem.bytesWritten 51934784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494089 # Total number of read requests seen +system.physmem.writeReqs 811479 # Total number of write requests seen +system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991621696 # Total number of bytes read from memory +system.physmem.bytesWritten 51934656 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603630334000 # Total gap between requests +system.physmem.totGap 2603660455000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.readPktSize::6 152013 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -108,7 +108,7 @@ system.physmem.writePktSize::2 754018 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57463 # categorize write packet sizes +system.physmem.writePktSize::6 57461 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -120,23 +120,23 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -153,14 +153,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see @@ -169,44 +169,44 @@ system.physmem.wrQLenPdf::12 35282 # Wh system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests -system.physmem.totBusLat 61975036000 # Total cycles spent in databus access -system.physmem.totBankLat 16863224000 # Total cycles spent in bank access -system.physmem.avgQLat 18619.82 # Average queueing delay per request -system.physmem.avgBankLat 1088.39 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23708.21 # Average memory access latency +system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests +system.physmem.totBusLat 77468765000 # Total cycles spent in databus access +system.physmem.totBankLat 17445216250 # Total cycles spent in bank access +system.physmem.avgQLat 22041.64 # Average queueing delay per request +system.physmem.avgBankLat 1125.95 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28167.59 # Average memory access latency system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.51 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 12.40 # Average write queue length over time -system.physmem.readRowHits 15451886 # Number of row buffer hits during reads -system.physmem.writeRowHits 785061 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes -system.physmem.avgGap 159677.30 # Average gap between requests +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 12.39 # Average write queue length over time +system.physmem.readRowHits 15418905 # Number of row buffer hits during reads +system.physmem.writeRowHits 794060 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes +system.physmem.avgGap 159679.22 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995645 # DTB read hits -system.cpu.dtb.read_misses 7331 # DTB read misses -system.cpu.dtb.write_hits 11230857 # DTB write hits +system.cpu.dtb.read_hits 14995667 # DTB read hits +system.cpu.dtb.read_misses 7332 # DTB read misses +system.cpu.dtb.write_hits 11230865 # DTB write hits system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002976 # DTB read accesses -system.cpu.dtb.write_accesses 11233060 # DTB write accesses +system.cpu.dtb.read_accesses 15002999 # DTB read accesses +system.cpu.dtb.write_accesses 11233068 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226502 # DTB hits -system.cpu.dtb.misses 9534 # DTB misses -system.cpu.dtb.accesses 26236036 # DTB accesses -system.cpu.itb.inst_hits 61491397 # ITB inst hits +system.cpu.dtb.hits 26226532 # DTB hits +system.cpu.dtb.misses 9535 # DTB misses +system.cpu.dtb.accesses 26236067 # DTB accesses +system.cpu.itb.inst_hits 61491584 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -263,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495868 # ITB inst accesses -system.cpu.itb.hits 61491397 # DTB hits +system.cpu.itb.inst_accesses 61496055 # ITB inst accesses +system.cpu.itb.hits 61491584 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495868 # DTB accesses -system.cpu.numCycles 5207269388 # number of cpu cycles simulated +system.cpu.itb.accesses 61496055 # DTB accesses +system.cpu.numCycles 5207329630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197457 # Number of instructions committed -system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses +system.cpu.committedInsts 60197643 # Number of instructions committed +system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139722 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868122 # number of integer instructions +system.cpu.num_func_calls 2139730 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls +system.cpu.num_int_insts 68868344 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written +system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read +system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393871 # number of memory refs -system.cpu.num_load_insts 15659652 # Number of load instructions -system.cpu.num_store_insts 11734219 # Number of store instructions -system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879373 # Percentage of idle cycles +system.cpu.num_mem_refs 27393912 # number of memory refs +system.cpu.num_load_insts 15659685 # Number of load instructions +system.cpu.num_store_insts 11734227 # Number of store instructions +system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879355 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855485 # number of replacements -system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use -system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635400 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635400 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635400 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635400 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635400 # number of overall hits -system.cpu.icache.overall_hits::total 60635400 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855997 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855997 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855997 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855997 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855997 # number of overall misses -system.cpu.icache.overall_misses::total 855997 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11539684000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11539684000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11539684000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses +system.cpu.icache.replacements 855486 # number of replacements +system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use +system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits +system.cpu.icache.overall_hits::total 60635586 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses +system.cpu.icache.overall_misses::total 855998 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491584 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491584 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13480.986499 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13480.986499 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13480.986499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13480.986499 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13515.573635 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13515.573635 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13515.573635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13515.573635 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,174 +344,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855997 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855997 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855997 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855997 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855997 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855997 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9827690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9827690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9827690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9827690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9827690000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9827690000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855998 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 855998 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 855998 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 855998 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 855998 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 855998 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9857308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9857308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9857308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9857308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9857308000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9857308000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 298856500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 298856500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11480.986499 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11480.986499 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11515.573635 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11515.573635 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 61912 # number of replacements -system.cpu.l2cache.tagsinuse 50893.937876 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1682687 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127293 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.219007 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2553095791000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37868.725267 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6995.530011 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6025.795614 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.577831 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 61906 # number of replacements +system.cpu.l2cache.tagsinuse 50893.814517 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1682715 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127287 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 13.219850 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2553152311000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37867.919206 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885514 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001401 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 6996.279505 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6025.728892 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.577819 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.106743 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.091946 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.776580 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8699 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.106755 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.091945 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8701 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 843755 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370324 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226326 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 596029 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 596029 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 843761 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370335 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226345 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 596039 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 596039 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 114426 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 114426 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8699 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 114427 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 114427 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 8701 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 843755 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484750 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340752 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8699 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 843761 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 484762 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1340772 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 8701 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 843755 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484750 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340752 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 843761 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 484762 # number of overall hits +system.cpu.l2cache.overall_hits::total 1340772 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143042 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153654 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143041 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153648 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143042 # number of overall misses -system.cpu.l2cache.overall_misses::total 153654 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 532505000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1045631500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 461000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 461000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6086440000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6086440000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 532505000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6599142000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7132071500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 532505000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6599142000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7132071500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8704 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143041 # number of overall misses +system.cpu.l2cache.overall_misses::total 153648 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 315500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 151000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 562062000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534519000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1097047500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6075862000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6075862000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 315500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 151000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 562062000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6610381000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7172909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 315500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 151000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 562062000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6610381000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7172909500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8706 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854359 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380183 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1246797 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 596029 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 596029 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 854360 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 380193 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1246810 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 596039 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 596039 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8704 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247610 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247610 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8706 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854359 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627792 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494406 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8704 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 854360 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627803 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494420 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8706 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854359 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627792 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494406 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 854360 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627803 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494420 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012412 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025932 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016419 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012406 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025929 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537876 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.537876 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537874 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.537874 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012412 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.227849 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.102819 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012406 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.227844 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.102814 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012412 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.227849 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.102819 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50217.370803 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52003.448626 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51078.672268 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.347826 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.347826 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45699.826554 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45699.826554 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50217.370803 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46134.296221 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46416.438882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50217.370803 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46134.296221 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46416.438882 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012406 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.227844 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.102814 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 63100 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 50333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53029.719785 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54221.850274 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53606.034693 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45620.402003 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45620.402003 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46684.040795 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46684.040795 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,92 +520,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57463 # number of writebacks -system.cpu.l2cache.writebacks::total 57463 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks +system.cpu.l2cache.writebacks::total 57461 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10604 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10604 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143042 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 153654 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143041 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 153648 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10604 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143042 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 153654 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 394778574 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 384642089 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 779742679 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28851319 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28851319 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4356126157 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4356126157 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 394778574 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4740768246 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5135868836 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 394778574 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4740768246 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5135868836 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166684815565 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166882282116 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9180297506 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9180297506 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175865113071 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176062579622 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143041 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 153648 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253760 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113756 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430665051 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411778800 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 842811367 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28850324 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28850324 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4437954325 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4437954325 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253760 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113756 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430665051 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4849733125 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5280765692 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253760 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113756 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430665051 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4849733125 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5280765692 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209122550 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688445815 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166897568365 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9173753597 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9173753597 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209122550 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175862199412 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176071321962 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025929 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537876 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537876 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537874 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537874 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227849 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.102819 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.102814 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227849 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.102819 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37229.212939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39014.310681 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38090.111817 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10035.241391 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10035.241391 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32707.824249 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32707.824249 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102814 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40632.611661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41771.028606 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41183.062155 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10034.895304 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10034.895304 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33322.228250 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33322.228250 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -615,79 +615,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627280 # number of replacements -system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655026 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627792 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.679719 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195122 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195122 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973048 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973048 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits +system.cpu.dcache.replacements 627291 # number of replacements +system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use +system.cpu.dcache.total_refs 23655046 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627803 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.679090 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195134 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195134 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236278 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236278 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168170 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168170 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168170 # number of overall hits -system.cpu.dcache.overall_hits::total 23168170 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368781 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368781 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619291 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619291 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619291 # number of overall misses -system.cpu.dcache.overall_misses::total 619291 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201704000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5201704000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8045775500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8045775500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154787000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 154787000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13247479500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13247479500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13247479500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13247479500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 23168189 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168189 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168189 # number of overall hits +system.cpu.dcache.overall_hits::total 23168189 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368792 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250511 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250511 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11401 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11401 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619303 # number of overall misses +system.cpu.dcache.overall_misses::total 619303 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027188 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027188 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026034 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026034 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026034 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026034 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.130145 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.130145 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32117.582132 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,54 +696,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596029 # number of writebacks -system.cpu.dcache.writebacks::total 596029 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368781 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368781 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619291 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619291 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619291 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619291 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4464142000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4464142000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7544755500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7544755500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12008897500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12008897500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12008897500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12008897500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182078406500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182078406500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18714752000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18714752000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200793158500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200793158500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks +system.cpu.dcache.writebacks::total 596039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.130145 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.130145 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30117.582132 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30117.582132 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11575.425364 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11575.425364 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 21a80bd51..9d3d17a68 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -211,7 +211,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 175418c2b..4cde41f9a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.112041 # Nu sim_ticks 5112040970500 # Number of ticks simulated final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1071475 # Simulator instruction rate (inst/s) -host_op_rate 2193921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27413112180 # Simulator tick rate (ticks/s) -host_mem_usage 626876 # Number of bytes of host memory used -host_seconds 186.48 # Real time elapsed on the host +host_inst_rate 1816388 # Simulator instruction rate (inst/s) +host_op_rate 3719186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46471341970 # Simulator tick rate (ticks/s) +host_mem_usage 582576 # Number of bytes of host memory used +host_seconds 110.00 # Real time elapsed on the host sim_insts 199810242 # Number of instructions simulated -sim_ops 409125923 # Number of ops (including micro ops) simulated +sim_ops 409125913 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -195,7 +195,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -264,22 +264,22 @@ system.cpu.numCycles 10224081964 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 199810242 # Number of instructions committed -system.cpu.committedOps 409125923 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374289914 # Number of integer alu accesses +system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls -system.cpu.num_int_insts 374289914 # number of integer instructions +system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls +system.cpu.num_int_insts 374289904 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915450706 # number of times the integer registers were read -system.cpu.num_int_register_writes 480322745 # number of times the integer registers were written +system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read +system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 35624590 # number of memory refs system.cpu.num_load_insts 27216588 # Number of load instructions system.cpu.num_store_insts 8408002 # Number of store instructions -system.cpu.num_idle_cycles 9770609597.971960 # Number of idle cycles -system.cpu.num_busy_cycles 453472366.028039 # Number of busy cycles +system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles +system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -331,7 +331,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cy system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102019610500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy @@ -379,7 +379,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cy system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101206386000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy @@ -471,7 +471,7 @@ system.cpu.dcache.writebacks::writebacks 1534848 # nu system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 106558 # number of replacements -system.cpu.l2cache.tagsinuse 64822.149219 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. @@ -479,8 +479,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.994082 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.564951 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 5387a3a4f..da7af1088 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,98 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.191113 # Number of seconds simulated -sim_ticks 5191112864000 # Number of ticks simulated -final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.195162 # Number of seconds simulated +sim_ticks 5195162021000 # Number of ticks simulated +final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 663100 # Simulator instruction rate (inst/s) -host_op_rate 1278245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26841102406 # Simulator tick rate (ticks/s) -host_mem_usage 658020 # Number of bytes of host memory used -host_seconds 193.40 # Real time elapsed on the host -sim_insts 128244620 # Number of instructions simulated -sim_ops 247214608 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory +host_inst_rate 973985 # Simulator instruction rate (inst/s) +host_op_rate 1877578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39447094407 # Simulator tick rate (ticks/s) +host_mem_usage 612564 # Number of bytes of host memory used +host_seconds 131.70 # Real time elapsed on the host +sim_insts 128273348 # Number of instructions simulated +sim_ops 247275973 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9026368 # Number of bytes read from this memory -system.physmem.bytes_read::total 12705024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8129280 # Number of bytes written to this memory -system.physmem.bytes_written::total 8129280 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44568 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9012160 # Number of bytes read from this memory +system.physmem.bytes_read::total 12697600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8123136 # Number of bytes written to this memory +system.physmem.bytes_written::total 8123136 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44708 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141037 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 127020 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127020 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 549468 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140815 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198400 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126924 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126924 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 550765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1738812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2447457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1565999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1565999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1565999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 549468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1734722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2444120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1563596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1563596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1563596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 550765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1738812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4013456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198516 # Total number of read requests seen -system.physmem.writeReqs 127020 # Total number of write requests seen -system.physmem.cpureqs 331314 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 12705024 # Total number of bytes read from memory -system.physmem.bytesWritten 8129280 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12705024 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8129280 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1599 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12411 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 11776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12503 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12788 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 12663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12141 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12474 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12788 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7431 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7966 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7373 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 8083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7719 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 8332 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7712 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7893 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7991 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8281 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 158560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1734722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198400 # Total number of read requests seen +system.physmem.writeReqs 126924 # Total number of write requests seen +system.physmem.cpureqs 331611 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12697600 # Total number of bytes read from memory +system.physmem.bytesWritten 8123136 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 12479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12349 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12500 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12050 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12574 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8012 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 8089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7865 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8084 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 8243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8069 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7980 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 5191112800500 # Total gap between requests +system.physmem.numWrRetry 633 # Number of times wr buffer was full causing retry +system.physmem.totGap 5195161957500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198516 # Categorize read packet sizes +system.physmem.readPktSize::6 198400 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -101,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 127020 # categorize write packet sizes +system.physmem.writePktSize::6 127557 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -110,30 +114,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1599 # categorize neither packet sizes +system.physmem.neitherpktsize::6 1624 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 158090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 155111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -146,93 +150,93 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2876225269 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6438451269 # Sum of mem lat for all requests -system.physmem.totBusLat 793712000 # Total cycles spent in databus access -system.physmem.totBankLat 2768514000 # Total cycles spent in bank access -system.physmem.avgQLat 14495.06 # Average queueing delay per request -system.physmem.avgBankLat 13952.23 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32447.29 # Average memory access latency -system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.totQLat 4076582985 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7872522985 # Sum of mem lat for all requests +system.physmem.totBusLat 991710000 # Total cycles spent in databus access +system.physmem.totBankLat 2804230000 # Total cycles spent in bank access +system.physmem.avgQLat 20553.30 # Average queueing delay per request +system.physmem.avgBankLat 14138.36 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 39691.66 # Average memory access latency +system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.06 # Average write queue length over time -system.physmem.readRowHits 179831 # Number of row buffer hits during reads -system.physmem.writeRowHits 78085 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.47 # Row buffer hit rate for writes -system.physmem.avgGap 15946355.55 # Average gap between requests -system.iocache.replacements 47506 # number of replacements -system.iocache.tagsinuse 0.117830 # Cycle average of tags in use +system.physmem.avgWrQLen 12.66 # Average write queue length over time +system.physmem.readRowHits 175587 # Number of row buffer hits during reads +system.physmem.writeRowHits 94819 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes +system.physmem.avgGap 15969193.66 # Average gap between requests +system.iocache.replacements 47509 # number of replacements +system.iocache.tagsinuse 0.124742 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47522 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47525 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5044498925000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.117830 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007364 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007364 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 841 # number of ReadReq misses -system.iocache.ReadReq_misses::total 841 # number of ReadReq misses +system.iocache.warmup_cycle 5044527520000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.124742 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007796 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007796 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses +system.iocache.ReadReq_misses::total 844 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47561 # number of demand (read+write) misses -system.iocache.demand_misses::total 47561 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47561 # number of overall misses -system.iocache.overall_misses::total 47561 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 133668932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 133668932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9598301160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9598301160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9731970092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9731970092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9731970092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9731970092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 841 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 841 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses +system.iocache.demand_misses::total 47564 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses +system.iocache.overall_misses::total 47564 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10701739160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10701739160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10841219092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10841219092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10841219092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10841219092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47561 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47561 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47561 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47561 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -241,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158940.466112 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158940.466112 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 205443.089897 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 205443.089897 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 204620.804693 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 204620.804693 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 78425 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229061.197774 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229061.197774 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227929.086957 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227929.086957 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 173428 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10368 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16211 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.564140 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.698168 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 841 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 841 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47561 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47561 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47561 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47561 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89906992 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 89906992 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7166703132 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7166703132 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7256610124 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7256610124 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570991 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 95570991 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8270938224 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8270938224 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8366509215 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8366509215 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -283,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106904.865636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106904.865636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 153396.899229 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 153396.899229 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.771327 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.771327 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177032.068151 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177032.068151 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -304,75 +308,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10382225728 # number of cpu cycles simulated +system.cpu.numCycles 10390324042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128244620 # Number of instructions committed -system.cpu.committedOps 247214608 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231949869 # Number of integer alu accesses +system.cpu.committedInsts 128273348 # Number of instructions committed +system.cpu.committedOps 247275973 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232011682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls -system.cpu.num_int_insts 231949869 # number of integer instructions +system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls +system.cpu.num_int_insts 232011682 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566905534 # number of times the integer registers were read -system.cpu.num_int_register_writes 293156476 # number of times the integer registers were written +system.cpu.num_int_register_reads 567056120 # number of times the integer registers were read +system.cpu.num_int_register_writes 293242224 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22227095 # number of memory refs -system.cpu.num_load_insts 13866667 # Number of load instructions -system.cpu.num_store_insts 8360428 # Number of store instructions -system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942147 # Percentage of idle cycles +system.cpu.num_mem_refs 22232138 # number of memory refs +system.cpu.num_load_insts 13871783 # Number of load instructions +system.cpu.num_store_insts 8360355 # Number of store instructions +system.cpu.num_idle_cycles 9789668776.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600655265.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942191 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790930 # number of replacements -system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use -system.cpu.icache.total_refs 144455345 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.521707 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor +system.cpu.icache.replacements 791521 # number of replacements +system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use +system.cpu.icache.total_refs 144497694 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 792033 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.438982 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144455345 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144455345 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144455345 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144455345 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144455345 # number of overall hits -system.cpu.icache.overall_hits::total 144455345 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses -system.cpu.icache.overall_misses::total 791449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871281000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10871281000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10871281000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145246794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145246794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145246794 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145246794 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145246794 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145246794 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.921076 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13735.921076 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13735.921076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13735.921076 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 144497694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144497694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144497694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144497694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144497694 # number of overall hits +system.cpu.icache.overall_hits::total 144497694 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792040 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792040 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792040 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792040 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792040 # number of overall misses +system.cpu.icache.overall_misses::total 792040 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10957638500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10957638500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10957638500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10957638500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10957638500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10957638500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145289734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145289734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145289734 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145289734 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145289734 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145289734 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.703424 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13834.703424 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13834.703424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13834.703424 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,80 +385,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791449 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791449 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791449 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791449 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791449 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791449 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9288383000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9288383000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9288383000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9288383000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9288383000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9288383000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.921076 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.921076 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11735.921076 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11735.921076 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11735.921076 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11735.921076 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792040 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 792040 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 792040 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 792040 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 792040 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 792040 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9373558500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9373558500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9373558500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9373558500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9373558500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9373558500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.703424 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.703424 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3663 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.069768 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7696 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3675 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.094150 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5164936292000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.069768 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191861 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191861 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7696 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7696 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3425 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.077882 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5164118674000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077882 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192368 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.192368 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8004 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 8004 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7698 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7698 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7698 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7698 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4528 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4528 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4528 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4528 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4528 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4528 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 46136000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 46136000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 46136000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 46136000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 46136000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 46136000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8006 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 8006 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8006 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 8006 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4287 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4287 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4287 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4287 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4287 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4287 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42274000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42274000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42274000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 42274000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42274000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 42274000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12291 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12291 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.370419 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.370419 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.370358 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.370358 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10189.045936 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10189.045936 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10189.045936 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10189.045936 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12293 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12293 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12293 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12293 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.348792 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.348792 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.348735 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.348735 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.348735 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.348735 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9860.975041 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9860.975041 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9860.975041 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -463,78 +467,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 884 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 884 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4528 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4528 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4528 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4528 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4528 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4528 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37080000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37080000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37080000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37080000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37080000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37080000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.370419 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.370419 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8189.045936 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 641 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 641 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4287 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4287 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4287 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4287 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4287 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4287 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33700000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33700000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33700000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33700000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33700000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33700000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.348792 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.348792 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.348735 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.348735 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7860.975041 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 8012 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.053256 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13052 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 8025 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.626417 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5162707625000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053256 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315829 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315829 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13068 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13068 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13068 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13068 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13068 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13068 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9194 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9194 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9194 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9194 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9194 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9194 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 98984000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 98984000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 98984000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 98984000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 98984000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 98984000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22262 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22262 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22262 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22262 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22262 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22262 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.412991 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.412991 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.412991 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.412991 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.412991 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.412991 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10766.151838 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10766.151838 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10766.151838 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10766.151838 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7538 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.062515 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13179 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7552 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.745101 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062515 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13181 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13181 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13181 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13181 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13181 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13181 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8725 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8725 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8725 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8725 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8725 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8725 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92081500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92081500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92081500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 92081500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92081500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 92081500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398293 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398293 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398293 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398293 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398293 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398293 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.753582 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.753582 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.753582 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,90 +547,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3347 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3347 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9194 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9194 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9194 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9194 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9194 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9194 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 80596000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 80596000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 80596000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 80596000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 80596000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 80596000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.412991 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.412991 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.412991 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8766.151838 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2712 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2712 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8725 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8725 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8725 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8725 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8725 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8725 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74631500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74631500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74631500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74631500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398293 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398293 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398293 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.753582 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1620901 # number of replacements -system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use -system.cpu.dcache.total_refs 20018690 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621413 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.346447 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1618787 # number of replacements +system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use +system.cpu.dcache.total_refs 20025899 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1619299 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.367017 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8034928 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8034928 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20016508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20016508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20016508 # number of overall hits -system.cpu.dcache.overall_hits::total 20016508 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308145 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308145 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315486 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623631 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623631 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623631 # number of overall misses -system.cpu.dcache.overall_misses::total 1623631 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313636000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18313636000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702717500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8702717500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27016353500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27016353500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27016353500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27016353500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21640139 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21640139 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21640139 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21640139 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098433 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037781 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037781 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075029 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.698810 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.698810 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.114712 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.114712 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16639.466418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16639.466418 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11988264 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11988264 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035473 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20023737 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20023737 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20023737 # number of overall hits +system.cpu.dcache.overall_hits::total 20023737 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1306607 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1306607 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1621495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1621495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1621495 # number of overall misses +system.cpu.dcache.overall_misses::total 1621495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18344083000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18344083000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556368000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8556368000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26900451000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26900451000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26900451000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26900451000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13294871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13294871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8350361 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350361 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21645232 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21645232 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21645232 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21645232 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098279 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098279 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037710 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037710 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074912 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074912 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074912 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074912 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14039.480119 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14039.480119 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27172.734433 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27172.734433 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16589.906845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16589.906845 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,46 +639,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538028 # number of writebacks -system.cpu.dcache.writebacks::total 1538028 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308145 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1308145 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315486 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1623631 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1623631 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1623631 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1623631 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23769091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769091500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23769091500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469978500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469978500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96617154500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96617154500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098433 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098433 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037781 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037781 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.698810 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.698810 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1536049 # number of writebacks +system.cpu.dcache.writebacks::total 1536049 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306607 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1306607 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1621495 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1621495 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1621495 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1621495 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15730869000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15730869000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926592000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926592000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23657461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23657461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23657461000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23657461000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467832500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467832500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613781500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613781500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037710 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037710 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074912 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074912 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.480119 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.480119 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25172.734433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25172.734433 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -682,127 +686,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 87015 # number of replacements -system.cpu.l2cache.tagsinuse 64709.520704 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3488531 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 151765 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.986400 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 86864 # number of replacements +system.cpu.l2cache.tagsinuse 64770.429000 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3484731 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.981653 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50328.696692 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140121 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3391.684309 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10988.999582 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.767955 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 50336.267441 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.007172 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140366 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3358.135857 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11075.878163 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.768070 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.051753 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.167679 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.987389 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6912 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3076 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 778529 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1278877 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2067394 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1542259 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1542259 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 324 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 324 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199770 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199770 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6912 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3076 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 778529 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1478647 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2267164 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6912 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3076 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 778529 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1478647 # number of overall hits -system.cpu.l2cache.overall_hits::total 2267164 # number of overall hits +system.cpu.l2cache.occ_percent::cpu.inst 0.051241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.169004 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.988318 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6346 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2754 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779155 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1277466 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2065721 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1539402 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1539402 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 293 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 293 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 199364 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 199364 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6346 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2754 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 779155 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1476830 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2265085 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6346 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2754 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779155 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1476830 # number of overall hits +system.cpu.l2cache.overall_hits::total 2265085 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12907 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28433 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41345 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1340 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1340 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113530 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113530 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12872 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28385 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41263 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1364 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1364 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113358 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113358 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12907 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154875 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12872 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141743 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154621 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12907 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141963 # number of overall misses -system.cpu.l2cache.overall_misses::total 154875 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12872 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141743 # number of overall misses +system.cpu.l2cache.overall_misses::total 154621 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 68500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711631000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599594500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2311570500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16623000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16623000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5723743500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5723743500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 789955500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1648844500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2439213500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16174500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 16174500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5583075000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5583075000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 68500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 711631000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7323338000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8035314000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 789955500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7231919500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8022288500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 68500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 711631000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7323338000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8035314000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6912 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3081 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791436 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307310 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108739 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1542259 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1542259 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1664 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313300 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313300 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6912 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3081 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1620610 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422039 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6912 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3081 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1620610 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422039 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001623 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016308 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021749 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019607 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.805288 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.805288 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362368 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.362368 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001623 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016308 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087598 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063944 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001623 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016308 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087598 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063944 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_latency::cpu.inst 789955500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7231919500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8022288500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6347 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2759 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 792027 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1305851 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2106984 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1539402 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1539402 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1657 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1657 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 312722 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 312722 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2759 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792027 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1618573 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2419706 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2759 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792027 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1618573 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2419706 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001812 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016252 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021737 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019584 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823174 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823174 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362488 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.362488 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000158 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001812 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016252 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087573 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063901 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000158 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001812 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016252 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087573 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063901 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68500 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.275432 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.379348 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.311888 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.132300 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.132300 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61370.066812 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58088.585521 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 59113.818675 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11858.137830 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11858.137830 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49251.706981 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49251.706981 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51882.576271 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61370.066812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51021.352024 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51883.563682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51882.576271 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61370.066812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51021.352024 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51883.563682 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -811,78 +829,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80353 # number of writebacks -system.cpu.l2cache.writebacks::total 80353 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 80257 # number of writebacks +system.cpu.l2cache.writebacks::total 80257 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12907 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28433 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41345 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1340 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1340 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113530 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 113530 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12872 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28385 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41263 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1364 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1364 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113358 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113358 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12872 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141743 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154621 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544173395 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230976255 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775429660 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249333352 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249333352 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280010 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544173395 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480309607 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6024763012 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280010 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544173395 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480309607 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6024763012 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86592298500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86592298500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2307004500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2307004500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88899303000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88899303000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021749 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019607 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.805288 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.805288 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362368 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362368 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063944 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.105989 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43293.928006 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42941.822711 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.167198 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141743 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154621 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56252 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281260 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 630045573 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1296264296 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1926647381 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14542846 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14542846 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190240726 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190240726 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281260 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 630045573 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5486505022 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6116888107 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56252 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281260 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 630045573 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5486505022 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6116888107 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305021500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896197000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896197000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063901 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48946.983608 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45667.229029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46691.888156 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36964.667037 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36964.667037 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 015bc1924..c8eb78d93 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.200409 # Number of seconds simulated -sim_ticks 200409284500 # Number of ticks simulated -final_tick 4321205328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 200409293000 # Number of ticks simulated +final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 13697441 # Simulator instruction rate (inst/s) -host_op_rate 13697433 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5245128514 # Simulator tick rate (ticks/s) -host_mem_usage 514692 # Number of bytes of host memory used -host_seconds 38.21 # Real time elapsed on the host -sim_insts 523360203 # Number of instructions simulated -sim_ops 523360203 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 80888044 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 27771396 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 50103096 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 158762536 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 80888044 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 80888044 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 16575224 # Number of bytes written to this memory +host_inst_rate 19440889 # Simulator instruction rate (inst/s) +host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7408936081 # Simulator tick rate (ticks/s) +host_mem_usage 472492 # Number of bytes of host memory used +host_seconds 27.05 # Real time elapsed on the host +sim_insts 525869186 # Number of instructions simulated +sim_ops 525869186 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 27826180 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 51169128 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 160043872 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 81048564 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 81048564 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 16606324 # Number of bytes written to this memory testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 16576126 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 20222011 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 3834989 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 2087611 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 26144611 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 2254078 # Number of write requests responded to by this memory +testsys.physmem.bytes_written::total 16607226 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 20262141 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 3842564 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 2132029 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 26236734 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 2258349 # Number of write requests responded to by this memory testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 2254109 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 403614255 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 138573400 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 250003866 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 792191521 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 403614255 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 403614255 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 82706867 # Write bandwidth from this memory (bytes/s) +testsys.physmem.num_writes::total 2258380 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 404415198 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 138846755 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 255323130 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 798585084 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 404415198 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 404415198 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 82862046 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 82711368 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 403614255 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 221280267 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 250008367 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 874902889 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_write::total 82866547 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 404415198 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 221708801 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 255327631 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 881451630 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.readReqs 0 # Total number of read requests seen testsys.physmem.writeReqs 0 # Total number of write requests seen testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -189,7 +189,7 @@ testsys.physmem.avgRdBW 0.00 # Av testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s testsys.physmem.busUtil 0.00 # Data bus utilization in percentage testsys.physmem.avgRdQLen 0.00 # Average read queue length over time testsys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -214,22 +214,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 3909164 # DTB read hits +testsys.cpu.dtb.read_hits 3916928 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.read_acv 80 # DTB read access violations testsys.cpu.dtb.read_accesses 225414 # DTB read accesses -testsys.cpu.dtb.write_hits 2312434 # DTB write hits +testsys.cpu.dtb.write_hits 2316846 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.dtb.write_acv 81 # DTB write access violations testsys.cpu.dtb.write_accesses 109988 # DTB write accesses -testsys.cpu.dtb.data_hits 6221598 # DTB hits +testsys.cpu.dtb.data_hits 6233774 # DTB hits testsys.cpu.dtb.data_misses 3815 # DTB misses testsys.cpu.dtb.data_acv 161 # DTB access violations testsys.cpu.dtb.data_accesses 335402 # DTB accesses -testsys.cpu.itb.fetch_hits 4045775 # ITB hits +testsys.cpu.itb.fetch_hits 4052272 # ITB hits testsys.cpu.itb.fetch_misses 1497 # ITB misses testsys.cpu.itb.fetch_acv 69 # ITB acv -testsys.cpu.itb.fetch_accesses 4047272 # ITB accesses +testsys.cpu.itb.fetch_accesses 4053769 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -242,51 +242,51 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 400807419 # number of cpu cycles simulated +testsys.cpu.numCycles 400815936 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 20218035 # Number of instructions committed -testsys.cpu.committedOps 20218035 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 18800192 # Number of integer alu accesses -testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses -testsys.cpu.num_func_calls 1218514 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 1439639 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 18800192 # number of integer instructions -testsys.cpu.num_fp_insts 17380 # number of float instructions -testsys.cpu.num_int_register_reads 24739164 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 14664877 # number of times the integer registers were written -testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read -testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written -testsys.cpu.num_mem_refs 6250795 # number of memory refs -testsys.cpu.num_load_insts 3936233 # Number of load instructions -testsys.cpu.num_store_insts 2314562 # Number of store instructions -testsys.cpu.num_idle_cycles 380584404.581032 # Number of idle cycles -testsys.cpu.num_busy_cycles 20223014.418968 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.050456 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.949544 # Percentage of idle cycles +testsys.cpu.committedInsts 20258165 # Number of instructions committed +testsys.cpu.committedOps 20258165 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 18837392 # Number of integer alu accesses +testsys.cpu.num_fp_alu_accesses 17313 # Number of float alu accesses +testsys.cpu.num_func_calls 1221260 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 1442190 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 18837392 # number of integer instructions +testsys.cpu.num_fp_insts 17313 # number of float instructions +testsys.cpu.num_int_register_reads 24787608 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 14694255 # number of times the integer registers were written +testsys.cpu.num_fp_register_reads 11133 # number of times the floating registers were read +testsys.cpu.num_fp_register_writes 10789 # number of times the floating registers were written +testsys.cpu.num_mem_refs 6263009 # number of memory refs +testsys.cpu.num_load_insts 3944038 # Number of load instructions +testsys.cpu.num_store_insts 2318971 # Number of store instructions +testsys.cpu.num_idle_cycles 380552362.972989 # Number of idle cycles +testsys.cpu.num_busy_cycles 20263573.027011 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.050556 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.949444 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 19525 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 153371 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 62656 42.67% 42.67% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 19578 13.33% 56.01% # number of times we switched to this ipl +testsys.cpu.kern.inst.quiesce 19598 # number of quiesce instructions executed +testsys.cpu.kern.inst.hwrei 153677 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 62790 42.68% 42.68% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 19620 13.34% 56.01% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 64383 43.85% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 146822 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 62650 43.18% 43.18% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 19578 13.49% 56.67% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_count::31 64514 43.85% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 147129 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 62784 43.18% 43.18% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 19620 13.49% 56.67% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 62661 43.19% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 145094 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 194361437500 96.98% 96.98% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 1585244500 0.79% 97.78% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_good::31 62791 43.19% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 145400 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 194352160500 96.98% 96.98% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 1588908500 0.79% 97.77% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 4448431000 2.22% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 200403928000 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 4458302500 2.22% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 200408186500 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.973254 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.988231 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::31 0.973293 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.988248 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed @@ -309,30 +309,30 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.kern.syscall::total 83 # number of syscalls executed -testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed +testsys.cpu.kern.callpal::swpctx 437 0.34% 0.34% # number of callpals executed testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed -testsys.cpu.kern.callpal::swpipl 106626 83.26% 83.62% # number of callpals executed +testsys.cpu.kern.callpal::swpipl 106841 83.26% 83.62% # number of callpals executed testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed -testsys.cpu.kern.callpal::rdusp 3 0.00% 83.91% # number of callpals executed -testsys.cpu.kern.callpal::rti 20424 15.95% 99.86% # number of callpals executed +testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed +testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 128057 # number of callpals executed -testsys.cpu.kern.mode_switch::kernel 1279 # number of protection mode switches -testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 19584 # number of protection mode switches +testsys.cpu.kern.callpal::total 128317 # number of callpals executed +testsys.cpu.kern.mode_switch::kernel 1281 # number of protection mode switches +testsys.cpu.kern.mode_switch::user 703 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 19627 # number of protection mode switches testsys.cpu.kern.mode_good::kernel 707 -testsys.cpu.kern.mode_good::user 702 -testsys.cpu.kern.mode_good::idle 5 -testsys.cpu.kern.mode_switch_good::kernel 0.552776 # fraction of useful protection mode switches +testsys.cpu.kern.mode_good::user 703 +testsys.cpu.kern.mode_good::idle 4 +testsys.cpu.kern.mode_switch_good::kernel 0.551913 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::total 0.065569 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks::kernel 993857000 59.77% 59.77% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::user 533068000 32.06% 91.82% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::idle 135946500 8.18% 100.00% # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 438 # number of times the context was actually changed +testsys.cpu.kern.mode_switch_good::idle 0.000204 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks::kernel 1002766500 60.53% 60.53% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::user 533073000 32.18% 92.70% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::idle 120928500 7.30% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 437 # number of times the context was actually changed testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted testsys.tsunami.ethernet.rxBytes 798 # Bytes Received testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted @@ -343,9 +343,9 @@ testsys.tsunami.ethernet.txTcpChecksums 2 # Nu testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -testsys.tsunami.ethernet.descDMAReads 2087576 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 2131994 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 50101824 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 51167856 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) testsys.tsunami.ethernet.totPackets 13 # Total Packets @@ -370,9 +370,9 @@ testsys.tsunami.ethernet.totalRxDesc 5 # to testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 19525 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 2087576 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 2131994 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -380,37 +380,37 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 2087594 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 2132012 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read::cpu.inst 76121948 # Number of bytes read from this memory -drivesys.physmem.bytes_read::cpu.data 26255588 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 50103126 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 152480662 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read::cpu.inst 76121948 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_inst_read::total 76121948 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written::cpu.data 14603776 # Number of bytes written to this memory +drivesys.physmem.bytes_read::cpu.inst 76288612 # Number of bytes read from this memory +drivesys.physmem.bytes_read::cpu.data 26312880 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 51169134 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 153770626 # Number of bytes read from this memory +drivesys.physmem.bytes_inst_read::cpu.inst 76288612 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_inst_read::total 76288612 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_written::cpu.data 14635456 # Number of bytes written to this memory drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory -drivesys.physmem.bytes_written::total 14604840 # Number of bytes written to this memory -drivesys.physmem.num_reads::cpu.inst 19030487 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::cpu.data 3643074 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 2087613 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 24761174 # Number of read requests responded to by this memory -drivesys.physmem.num_writes::cpu.data 2022588 # Number of write requests responded to by this memory +drivesys.physmem.bytes_written::total 14636520 # Number of bytes written to this memory +drivesys.physmem.num_reads::cpu.inst 19072153 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::cpu.data 3651006 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 2132030 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 24855189 # Number of read requests responded to by this memory +drivesys.physmem.num_writes::cpu.data 2026958 # Number of write requests responded to by this memory drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory -drivesys.physmem.num_writes::total 2022625 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 379832442 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 131009839 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 250004016 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 760846297 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 379832442 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 379832442 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 72869758 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.num_writes::total 2026995 # Number of write requests responded to by this memory +drivesys.physmem.bw_read::cpu.inst 380664044 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 131295708 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 255323160 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 767282912 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 380664044 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 380664044 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 73027831 # Write bandwidth from this memory (bytes/s) drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 72875067 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 379832442 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 203879596 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 250009325 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 833721364 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_write::total 73033140 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 380664044 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 204323539 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 255328469 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 840316053 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.readReqs 0 # Total number of read requests seen drivesys.physmem.writeReqs 0 # Total number of write requests seen drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -560,7 +560,7 @@ drivesys.physmem.avgRdBW 0.00 # Av drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -585,22 +585,22 @@ drivesys.cpu.dtb.fetch_hits 0 # IT drivesys.cpu.dtb.fetch_misses 0 # ITB misses drivesys.cpu.dtb.fetch_acv 0 # ITB acv drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses -drivesys.cpu.dtb.read_hits 3721202 # DTB read hits +drivesys.cpu.dtb.read_hits 3729326 # DTB read hits drivesys.cpu.dtb.read_misses 487 # DTB read misses drivesys.cpu.dtb.read_acv 30 # DTB read access violations drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses -drivesys.cpu.dtb.write_hits 2081819 # DTB write hits +drivesys.cpu.dtb.write_hits 2086333 # DTB write hits drivesys.cpu.dtb.write_misses 82 # DTB write misses drivesys.cpu.dtb.write_acv 10 # DTB write access violations drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses -drivesys.cpu.dtb.data_hits 5803021 # DTB hits +drivesys.cpu.dtb.data_hits 5815659 # DTB hits drivesys.cpu.dtb.data_misses 569 # DTB misses drivesys.cpu.dtb.data_acv 40 # DTB access violations drivesys.cpu.dtb.data_accesses 401230 # DTB accesses -drivesys.cpu.itb.fetch_hits 4194101 # ITB hits +drivesys.cpu.itb.fetch_hits 4201097 # ITB hits drivesys.cpu.itb.fetch_misses 194 # ITB misses drivesys.cpu.itb.fetch_acv 22 # ITB acv -drivesys.cpu.itb.fetch_accesses 4194295 # ITB accesses +drivesys.cpu.itb.fetch_accesses 4201291 # ITB accesses drivesys.cpu.itb.read_hits 0 # DTB read hits drivesys.cpu.itb.read_misses 0 # DTB read misses drivesys.cpu.itb.read_acv 0 # DTB read access violations @@ -613,51 +613,51 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 801639056 # number of cpu cycles simulated +drivesys.cpu.numCycles 801619128 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.committedInsts 19029878 # Number of instructions committed -drivesys.cpu.committedOps 19029878 # Number of ops (including micro ops) committed -drivesys.cpu.num_int_alu_accesses 17721251 # Number of integer alu accesses +drivesys.cpu.committedInsts 19071544 # Number of instructions committed +drivesys.cpu.committedOps 19071544 # Number of ops (including micro ops) committed +drivesys.cpu.num_int_alu_accesses 17759891 # Number of integer alu accesses drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses -drivesys.cpu.num_func_calls 1263632 # number of times a function call or return occured -drivesys.cpu.num_conditional_control_insts 1263629 # number of instructions that are conditional controls -drivesys.cpu.num_int_insts 17721251 # number of integer instructions +drivesys.cpu.num_func_calls 1266408 # number of times a function call or return occured +drivesys.cpu.num_conditional_control_insts 1266328 # number of instructions that are conditional controls +drivesys.cpu.num_int_insts 17759891 # number of integer instructions drivesys.cpu.num_fp_insts 1412 # number of float instructions -drivesys.cpu.num_int_register_reads 23047059 # number of times the integer registers were read -drivesys.cpu.num_int_register_writes 13965767 # number of times the integer registers were written +drivesys.cpu.num_int_register_reads 23097438 # number of times the integer registers were read +drivesys.cpu.num_int_register_writes 13996340 # number of times the integer registers were written drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written -drivesys.cpu.num_mem_refs 5824433 # number of memory refs -drivesys.cpu.num_load_insts 3742101 # Number of load instructions -drivesys.cpu.num_store_insts 2082332 # Number of store instructions -drivesys.cpu.num_idle_cycles 782608307.467164 # Number of idle cycles -drivesys.cpu.num_busy_cycles 19030748.532836 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.023740 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.976260 # Percentage of idle cycles +drivesys.cpu.num_mem_refs 5837119 # number of memory refs +drivesys.cpu.num_load_insts 3750273 # Number of load instructions +drivesys.cpu.num_store_insts 2086846 # Number of store instructions +drivesys.cpu.num_idle_cycles 782547188.298833 # Number of idle cycles +drivesys.cpu.num_busy_cycles 19071939.701167 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.023792 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.976208 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.quiesce 19854 # number of quiesce instructions executed -drivesys.cpu.kern.inst.hwrei 143418 # number of hwrei instructions executed -drivesys.cpu.kern.ipl_count::0 60285 42.42% 42.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::21 19703 13.86% 56.28% # number of times we switched to this ipl +drivesys.cpu.kern.inst.quiesce 19898 # number of quiesce instructions executed +drivesys.cpu.kern.inst.hwrei 143758 # number of hwrei instructions executed +drivesys.cpu.kern.ipl_count::0 60430 42.42% 42.42% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::21 19752 13.86% 56.28% # number of times we switched to this ipl drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::31 61936 43.58% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::total 142129 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good::0 60285 42.91% 42.91% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::21 19703 14.03% 56.94% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_count::31 62082 43.58% 100.00% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::total 142469 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good::0 60430 42.91% 42.91% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::21 19752 14.03% 56.94% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::31 60286 42.91% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::total 140479 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 197404825250 98.50% 98.50% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 797938750 0.40% 98.90% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_good::31 60432 42.91% 100.00% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::total 140819 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks::0 197392680000 98.50% 98.50% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 799890500 0.40% 98.90% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::31 2202592500 1.10% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 200409764000 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::31 2207804000 1.10% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 200404782000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::31 0.973360 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::total 0.988391 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::31 0.973422 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::total 0.988419 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed @@ -673,26 +673,26 @@ drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # nu drivesys.cpu.kern.syscall::total 22 # number of syscalls executed drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed -drivesys.cpu.kern.callpal::swpipl 102208 83.31% 83.37% # number of callpals executed +drivesys.cpu.kern.callpal::swpipl 102452 83.31% 83.37% # number of callpals executed drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed -drivesys.cpu.kern.callpal::rti 20014 16.31% 99.97% # number of callpals executed +drivesys.cpu.kern.callpal::rti 20062 16.31% 99.97% # number of callpals executed drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed -drivesys.cpu.kern.callpal::total 122686 # number of callpals executed +drivesys.cpu.kern.callpal::total 122978 # number of callpals executed drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches -drivesys.cpu.kern.mode_switch::idle 19872 # number of protection mode switches +drivesys.cpu.kern.mode_switch::idle 19920 # number of protection mode switches drivesys.cpu.kern.mode_good::kernel 143 drivesys.cpu.kern.mode_good::user 139 drivesys.cpu.kern.mode_good::idle 4 drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::total 0.014141 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::total 0.014107 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::user 319665750 10.81% 13.45% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::idle 2560362000 86.55% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::user 319665750 10.79% 13.43% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::idle 2564974000 86.57% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received @@ -704,9 +704,9 @@ drivesys.tsunami.ethernet.txTcpChecksums 2 # Nu drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -drivesys.tsunami.ethernet.descDMAReads 2087584 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 2132001 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 50102016 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 51168024 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) drivesys.tsunami.ethernet.totPackets 13 # Total Packets @@ -731,9 +731,9 @@ drivesys.tsunami.ethernet.totalRxDesc 8 # to drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -drivesys.tsunami.ethernet.postedTxIdle 19702 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 19750 # number of TxIdle interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 2087584 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 2132001 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -741,49 +741,49 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 2087605 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 2132022 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- ---------- Begin Simulation Statistics ---------- sim_seconds 0.000407 # Number of seconds simulated -sim_ticks 406952000 # Number of ticks simulated -final_tick 4321612280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 407365500 # Number of ticks simulated +final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 7058170696 # Simulator instruction rate (inst/s) -host_op_rate 7056390513 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5484794115 # Simulator tick rate (ticks/s) -host_mem_usage 514692 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -sim_insts 523432506 # Number of instructions simulated -sim_ops 523432506 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 144604 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 296292 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 144604 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 144604 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 27688 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 36151 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 47299 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 355334290 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 728076038 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 355334290 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 355334290 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 355334290 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 796113547 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 12024534237 # Simulator instruction rate (inst/s) +host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9308365303 # Simulator tick rate (ticks/s) +host_mem_usage 472492 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +sim_insts 525940622 # Number of instructions simulated +sim_ops 525940622 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 48760 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 103992 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 293888 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 141136 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 141136 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 27028 # Number of bytes written to this memory +testsys.physmem.bytes_written::total 27028 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 35284 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 6744 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 4333 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 46361 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 3721 # Number of write requests responded to by this memory +testsys.physmem.num_writes::total 3721 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 346460365 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 119695949 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 255279350 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 721435664 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 346460365 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 346460365 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 66348279 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::total 66348279 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 346460365 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 186044228 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 255279350 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 787783943 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.readReqs 0 # Total number of read requests seen testsys.physmem.writeReqs 0 # Total number of write requests seen testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -933,7 +933,7 @@ testsys.physmem.avgRdBW 0.00 # Av testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s testsys.physmem.busUtil 0.00 # Data bus utilization in percentage testsys.physmem.avgRdQLen 0.00 # Average read queue length over time testsys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -958,22 +958,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 7069 # DTB read hits +testsys.cpu.dtb.read_hits 6900 # DTB read hits testsys.cpu.dtb.read_misses 0 # DTB read misses testsys.cpu.dtb.read_acv 0 # DTB read access violations testsys.cpu.dtb.read_accesses 0 # DTB read accesses -testsys.cpu.dtb.write_hits 3933 # DTB write hits +testsys.cpu.dtb.write_hits 3839 # DTB write hits testsys.cpu.dtb.write_misses 0 # DTB write misses testsys.cpu.dtb.write_acv 0 # DTB write access violations testsys.cpu.dtb.write_accesses 0 # DTB write accesses -testsys.cpu.dtb.data_hits 11002 # DTB hits +testsys.cpu.dtb.data_hits 10739 # DTB hits testsys.cpu.dtb.data_misses 0 # DTB misses testsys.cpu.dtb.data_acv 0 # DTB access violations testsys.cpu.dtb.data_accesses 0 # DTB accesses -testsys.cpu.itb.fetch_hits 5992 # ITB hits +testsys.cpu.itb.fetch_hits 5847 # ITB hits testsys.cpu.itb.fetch_misses 0 # ITB misses testsys.cpu.itb.fetch_acv 0 # ITB acv -testsys.cpu.itb.fetch_accesses 5992 # ITB accesses +testsys.cpu.itb.fetch_accesses 5847 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -986,58 +986,58 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 821760 # number of cpu cycles simulated +testsys.cpu.numCycles 799188 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 36151 # Number of instructions committed -testsys.cpu.committedOps 36151 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 33514 # Number of integer alu accesses +testsys.cpu.committedInsts 35284 # Number of instructions committed +testsys.cpu.committedOps 35284 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 32710 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -testsys.cpu.num_func_calls 2388 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 2348 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 33514 # number of integer instructions +testsys.cpu.num_func_calls 2330 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 2292 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 32710 # number of integer instructions testsys.cpu.num_fp_insts 0 # number of float instructions -testsys.cpu.num_int_register_reads 43768 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 26496 # number of times the integer registers were written +testsys.cpu.num_int_register_reads 42720 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 25860 # number of times the integer registers were written testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written -testsys.cpu.num_mem_refs 11043 # number of memory refs -testsys.cpu.num_load_insts 7109 # Number of load instructions -testsys.cpu.num_store_insts 3934 # Number of store instructions -testsys.cpu.num_idle_cycles 785260.061817 # Number of idle cycles -testsys.cpu.num_busy_cycles 36499.938183 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.044417 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.955583 # Percentage of idle cycles +testsys.cpu.num_mem_refs 10779 # number of memory refs +testsys.cpu.num_load_insts 6939 # Number of load instructions +testsys.cpu.num_store_insts 3840 # Number of store instructions +testsys.cpu.num_idle_cycles 764577.129267 # Number of idle cycles +testsys.cpu.num_busy_cycles 34610.870733 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.043308 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.956692 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 398338500 96.95% 96.95% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.74% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.75% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 9258500 2.25% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 410880000 # number of cycles we spent at this ipl +testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed +testsys.cpu.kern.inst.hwrei 288 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 120 41.81% 41.81% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 39 13.59% 55.40% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::22 1 0.35% 55.75% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::31 127 44.25% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 287 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 120 42.86% 42.86% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 39 13.93% 56.79% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::22 1 0.36% 57.14% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::31 120 42.86% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 280 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 387349500 96.94% 96.94% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 3159000 0.79% 97.73% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 9042500 2.26% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 399594000 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed -testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed -testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 254 # number of callpals executed +testsys.cpu.kern.ipl_used::31 0.944882 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.975610 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.callpal::swpipl 207 83.47% 83.47% # number of callpals executed +testsys.cpu.kern.callpal::rdps 1 0.40% 83.87% # number of callpals executed +testsys.cpu.kern.callpal::rti 40 16.13% 100.00% # number of callpals executed +testsys.cpu.kern.callpal::total 248 # number of callpals executed testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 40 # number of protection mode switches testsys.cpu.kern.mode_good::kernel 0 testsys.cpu.kern.mode_good::user 0 testsys.cpu.kern.mode_good::idle 0 @@ -1049,9 +1049,9 @@ testsys.cpu.kern.mode_ticks::kernel 0 # nu testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode testsys.cpu.kern.swap_context 0 # number of times the context was actually changed -testsys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 4333 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 103992 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1068,9 +1068,9 @@ testsys.tsunami.ethernet.totalRxDesc 0 # to testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 39 # number of TxIdle interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 4333 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -1078,34 +1078,34 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 4333 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 296296 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 104016 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 298576 # Number of bytes read from this memory drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 47300 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 4334 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 47395 # Number of read requests responded to by this memory drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 355344119 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 728085868 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 355344119 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 355344119 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 355344119 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 796123376 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.inst 354983424 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 122622068 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 255338265 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 732943757 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 354983424 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 354983424 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 67968446 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::total 67968446 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 354983424 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 190590514 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 255338265 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 800912203 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.readReqs 0 # Total number of read requests seen drivesys.physmem.writeReqs 0 # Total number of write requests seen drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -1255,7 +1255,7 @@ drivesys.physmem.avgRdBW 0.00 # Av drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -1308,7 +1308,7 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 1628160 # number of cpu cycles simulated +drivesys.cpu.numCycles 1624320 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed drivesys.cpu.committedInsts 36152 # Number of instructions committed @@ -1326,10 +1326,10 @@ drivesys.cpu.num_fp_register_writes 0 # nu drivesys.cpu.num_mem_refs 11043 # number of memory refs drivesys.cpu.num_load_insts 7109 # Number of load instructions drivesys.cpu.num_store_insts 3934 # Number of store instructions -drivesys.cpu.num_idle_cycles 1592000.182518 # Number of idle cycles -drivesys.cpu.num_busy_cycles 36159.817482 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.022209 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.977791 # Percentage of idle cycles +drivesys.cpu.num_idle_cycles 1588282.082886 # Number of idle cycles +drivesys.cpu.num_busy_cycles 36037.917114 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.022186 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.977814 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed @@ -1343,11 +1343,11 @@ drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # nu drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 400769000 98.46% 98.46% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::0 399809000 98.46% 98.46% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.85% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 407040000 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 406080000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1371,9 +1371,9 @@ drivesys.cpu.kern.mode_ticks::kernel 0 # nu drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed -drivesys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 4334 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 104016 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1392,7 +1392,7 @@ drivesys.tsunami.ethernet.coalescedTxOk 0 # av drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 4334 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -1400,7 +1400,7 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 4334 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- |