diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-02-19 07:59:46 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-02-19 07:59:46 -0500 |
| commit | fd9343eb857493ba7bade90d99a945f5577ab7ab (patch) | |
| tree | 8807d425acf7a49ca457fb814b4ab1b1d647784c /tests/quick/fs | |
| parent | 6b765ba8b79814eddaa4c10a5cc140b636bb9df8 (diff) | |
| download | gem5-fd9343eb857493ba7bade90d99a945f5577ab7ab.tar.xz | |
arm: Bump stats after FS config script update
This patch updates the stats to reflect the change in kernel options
needed for armv8 (but used for all FS regressions).
Diffstat (limited to 'tests/quick/fs')
5 files changed, 3073 insertions, 3063 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 49d7eb553..49e1054f0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.912097 # Number of seconds simulated -sim_ticks 912096767500 # Number of ticks simulated -final_tick 912096767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.912098 # Number of seconds simulated +sim_ticks 912098398000 # Number of ticks simulated +final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734225 # Simulator instruction rate (inst/s) -host_op_rate 945306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10865482551 # Simulator tick rate (ticks/s) -host_mem_usage 476960 # Number of bytes of host memory used -host_seconds 83.94 # Real time elapsed on the host -sim_insts 61634065 # Number of instructions simulated -sim_ops 79353129 # Number of ops (including micro ops) simulated +host_inst_rate 1169212 # Simulator instruction rate (inst/s) +host_op_rate 1505339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17301899059 # Simulator tick rate (ticks/s) +host_mem_usage 421332 # Number of bytes of host memory used +host_seconds 52.72 # Real time elapsed on the host +sim_insts 61636937 # Number of instructions simulated +sim_ops 79356422 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -35,76 +35,76 @@ system.physmem.bytes_read::realview.clcd 39321600 # Nu system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6235196 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6235260 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3364536 # Number of bytes read from this memory -system.physmem.bytes_read::total 49638596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3364600 # Number of bytes read from this memory +system.physmem.bytes_read::total 49638724 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4195904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7222992 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 97499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 97500 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 52599 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082824 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 52600 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082826 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65561 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory -system.physmem.num_writes::total 822331 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 822333 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43111138 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 550621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 6836112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 550620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6836170 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 235278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3688793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54422511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 550621 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 235278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 785899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4600143 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 235277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3688856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54422554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 550620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 235277 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 785898 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4600276 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4600143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3300179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7919093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4600276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43111138 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 550621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 6854751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 550620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6854809 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 235278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6988978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 62341477 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 64986682 # Throughput (bytes/s) -system.membus.data_through_bus 59274143 # Total data (bytes) +system.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 64987015 # Throughput (bytes/s) +system.membus.data_through_bus 59274552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 70658 # number of replacements -system.l2c.tags.tagsinuse 51560.149479 # Cycle average of tags in use -system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. +system.l2c.tags.replacements 70660 # number of replacements +system.l2c.tags.tagsinuse 51560.418077 # Cycle average of tags in use +system.l2c.tags.total_refs 1623334 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 135812 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.952802 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39278.694836 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 39278.982234 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4358.955623 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2482.444990 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2126.451280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3310.922652 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001109 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4358.948754 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2482.442784 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678936 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2126.447479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3310.916734 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.599350 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy @@ -112,7 +112,7 @@ system.l2c.tags.occ_percent::cpu0.data 0.037879 # Av system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.786750 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id @@ -124,46 +124,46 @@ system.l2c.tags.age_task_id_blocks_1024::3 12549 # system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 16908094 # Number of tag accesses -system.l2c.tags.data_accesses 16908094 # Number of data accesses +system.l2c.tags.tag_accesses 16908072 # Number of tag accesses +system.l2c.tags.data_accesses 16908072 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 175187 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits -system.l2c.Writeback_hits::total 567807 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.data 169510 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1209104 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 567806 # number of Writeback hits +system.l2c.Writeback_hits::total 567806 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 58145 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 50213 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 108358 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 233332 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits -system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits +system.l2c.demand_hits::total 1317462 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits -system.l2c.overall_hits::cpu0.data 233336 # number of overall hits +system.l2c.overall_hits::cpu0.data 233332 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits system.l2c.overall_hits::cpu1.data 219723 # number of overall hits -system.l2c.overall_hits::total 1317466 # number of overall hits +system.l2c.overall_hits::total 1317462 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses @@ -178,63 +178,63 @@ system.l2c.UpgradeReq_misses::total 9391 # nu system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 92465 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 48373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140838 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 98857 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses -system.l2c.demand_misses::total 163290 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 53649 # number of demand (read+write) misses +system.l2c.demand_misses::total 163292 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses -system.l2c.overall_misses::cpu0.data 98856 # number of overall misses +system.l2c.overall_misses::cpu0.data 98857 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses -system.l2c.overall_misses::cpu1.data 53648 # number of overall misses -system.l2c.overall_misses::total 163290 # number of overall misses +system.l2c.overall_misses::cpu1.data 53649 # number of overall misses +system.l2c.overall_misses::total 163292 # number of overall misses system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 181579 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 174786 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1231558 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 567806 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 567806 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150610 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 98586 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 332189 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 273372 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1480754 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 332189 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 273372 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1480754 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses @@ -249,25 +249,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.880544 # mi system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.613937 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.565170 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.297593 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.196249 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.110276 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.297593 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.196249 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.110276 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -276,8 +276,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65559 # number of writebacks -system.l2c.writebacks::total 65559 # number of writebacks +system.l2c.writebacks::writebacks 65561 # number of writebacks +system.l2c.writebacks::total 65561 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -285,11 +285,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 154019994 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 140481139 # Total data (bytes) +system.toL2Bus.throughput 154019817 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 140481228 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 45730949 # Throughput (bytes/s) -system.iobus.data_through_bus 41711051 # Total data (bytes) +system.iobus.throughput 45731035 # Throughput (bytes/s) +system.iobus.data_through_bus 41711204 # Total data (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -313,9 +313,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7977216 # DTB read hits +system.cpu0.dtb.read_hits 7977762 # DTB read hits system.cpu0.dtb.read_misses 3611 # DTB read misses -system.cpu0.dtb.write_hits 5966960 # DTB write hits +system.cpu0.dtb.write_hits 5967140 # DTB write hits system.cpu0.dtb.write_misses 672 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -326,12 +326,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7980827 # DTB read accesses -system.cpu0.dtb.write_accesses 5967632 # DTB write accesses +system.cpu0.dtb.read_accesses 7981373 # DTB read accesses +system.cpu0.dtb.write_accesses 5967812 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13944176 # DTB hits +system.cpu0.dtb.hits 13944902 # DTB hits system.cpu0.dtb.misses 4283 # DTB misses -system.cpu0.dtb.accesses 13948459 # DTB accesses +system.cpu0.dtb.accesses 13949185 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -353,7 +353,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30245736 # ITB inst hits +system.cpu0.itb.inst_hits 30248608 # ITB inst hits system.cpu0.itb.inst_misses 2175 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -370,74 +370,74 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30247911 # ITB inst accesses -system.cpu0.itb.hits 30245736 # DTB hits +system.cpu0.itb.inst_accesses 30250783 # ITB inst accesses +system.cpu0.itb.hits 30248608 # DTB hits system.cpu0.itb.misses 2175 # DTB misses -system.cpu0.itb.accesses 30247911 # DTB accesses -system.cpu0.numCycles 1823671415 # number of cpu cycles simulated +system.cpu0.itb.accesses 30250783 # DTB accesses +system.cpu0.numCycles 1823674676 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29756754 # Number of instructions committed -system.cpu0.committedOps 39137733 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34752271 # Number of integer alu accesses +system.cpu0.committedInsts 29759626 # Number of instructions committed +system.cpu0.committedOps 39141026 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34755088 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses -system.cpu0.num_func_calls 1242676 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4045310 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34752271 # number of integer instructions +system.cpu0.num_func_calls 1242746 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4045769 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34755088 # number of integer instructions system.cpu0.num_fp_insts 5449 # number of float instructions -system.cpu0.num_int_register_reads 179899233 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36833612 # number of times the integer registers were written +system.cpu0.num_int_register_reads 179913159 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36837171 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_mem_refs 14629077 # number of memory refs -system.cpu0.num_load_insts 8358676 # Number of load instructions -system.cpu0.num_store_insts 6270401 # Number of store instructions -system.cpu0.num_idle_cycles 1783997907.577739 # Number of idle cycles -system.cpu0.num_busy_cycles 39673507.422261 # Number of busy cycles -system.cpu0.not_idle_fraction 0.021755 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.978245 # Percentage of idle cycles -system.cpu0.Branches 5491598 # Number of branches fetched +system.cpu0.num_mem_refs 14629859 # number of memory refs +system.cpu0.num_load_insts 8359235 # Number of load instructions +system.cpu0.num_store_insts 6270624 # Number of store instructions +system.cpu0.num_idle_cycles 1783997876.499954 # Number of idle cycles +system.cpu0.num_busy_cycles 39676799.500046 # Number of busy cycles +system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles +system.cpu0.Branches 5492144 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 428546 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.015213 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29818047 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 511.014878 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29820919 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 69.496541 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64537144000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015213 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.avg_refs 69.503235 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64538774500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.014878 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998076 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 30676165 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 30676165 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29818047 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29818047 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29818047 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29818047 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29818047 # number of overall hits -system.cpu0.icache.overall_hits::total 29818047 # number of overall hits +system.cpu0.icache.tags.tag_accesses 30679037 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 30679037 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29820919 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29820919 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29820919 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29820919 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29820919 # number of overall hits +system.cpu0.icache.overall_hits::total 29820919 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses system.cpu0.icache.overall_misses::total 429059 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30247106 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 30247106 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30247106 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 30247106 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30247106 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 30247106 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014185 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014185 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014185 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014185 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014185 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014185 # miss rate for overall accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30249978 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 30249978 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30249978 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 30249978 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30249978 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 30249978 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014184 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014184 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014184 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014184 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014184 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014184 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,68 +447,68 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 323609 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.763093 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12469292 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 38.487726 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 323608 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.763142 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12469968 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 323980 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 38.489931 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763093 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763142 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51682637 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51682637 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6513463 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6513463 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5631258 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5631258 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 51685336 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51685336 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6513975 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6513975 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5631422 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5631422 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12144721 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12144721 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12144721 # number of overall hits -system.cpu0.dcache.overall_hits::total 12144721 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 12145397 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12145397 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12145397 # number of overall hits +system.cpu0.dcache.overall_hits::total 12145397 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167351 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 167351 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167350 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 167350 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 364518 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 364518 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 364518 # number of overall misses -system.cpu0.dcache.overall_misses::total 364518 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6710630 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6710630 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798609 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5798609 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 364517 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 364517 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 364517 # number of overall misses +system.cpu0.dcache.overall_misses::total 364517 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6711142 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6711142 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798772 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5798772 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12509239 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12509239 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12509239 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12509239 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029381 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029381 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12509914 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12509914 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12509914 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12509914 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029379 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029379 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028860 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.028860 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029140 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029140 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029140 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029140 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029138 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029138 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029138 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029138 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,8 +517,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks -system.cpu0.dcache.writebacks::total 300958 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 300957 # number of writebacks +system.cpu0.dcache.writebacks::total 300957 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -604,7 +604,7 @@ system.cpu1.itb.inst_accesses 32415891 # IT system.cpu1.itb.hits 32413691 # DTB hits system.cpu1.itb.misses 2200 # DTB misses system.cpu1.itb.accesses 32415891 # DTB accesses -system.cpu1.numCycles 1824193536 # number of cpu cycles simulated +system.cpu1.numCycles 1824196797 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 31877311 # Number of instructions committed @@ -622,7 +622,7 @@ system.cpu1.num_fp_register_writes 1416 # nu system.cpu1.num_mem_refs 13371151 # number of memory refs system.cpu1.num_load_insts 7642991 # Number of load instructions system.cpu1.num_store_insts 5728160 # Number of store instructions -system.cpu1.num_idle_cycles 1783399616.755682 # Number of idle cycles +system.cpu1.num_idle_cycles 1783402877.755682 # Number of idle cycles system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles @@ -630,14 +630,14 @@ system.cpu1.Branches 5037975 # Nu system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed system.cpu1.icache.tags.replacements 433942 # number of replacements -system.cpu1.icache.tags.tagsinuse 475.447911 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 475.447061 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 69967761000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447911 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.warmup_cycle 69969391500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447061 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928608 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.928608 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id @@ -680,46 +680,46 @@ system.cpu1.icache.fast_writes 0 # nu system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 294289 # number of replacements -system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11708150 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 447.572964 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11708149 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.715435 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67293491000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.avg_refs 39.715432 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 67295121500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.572964 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874166 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.874166 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 48419345 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 48419345 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7002503 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7002503 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4520265 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4520265 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 48419346 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 48419346 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 7002504 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7002504 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4520263 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4520263 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11522768 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11522768 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11522768 # number of overall hits -system.cpu1.dcache.overall_hits::total 11522768 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 126066 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 126066 # number of WriteReq misses +system.cpu1.dcache.demand_hits::cpu1.data 11522767 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11522767 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11522767 # number of overall hits +system.cpu1.dcache.overall_hits::total 11522767 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 198274 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 198274 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 126068 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 126068 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 324341 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 324341 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 324341 # number of overall misses -system.cpu1.dcache.overall_misses::total 324341 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 324342 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 324342 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 324342 # number of overall misses +system.cpu1.dcache.overall_misses::total 324342 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses) @@ -734,8 +734,8 @@ system.cpu1.dcache.overall_accesses::cpu1.data 11847109 system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027132 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027132 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027133 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027133 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index ead7e7aa6..101d25ddf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332810 # Number of seconds simulated -sim_ticks 2332810269000 # Number of ticks simulated -final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.332812 # Number of seconds simulated +sim_ticks 2332811899500 # Number of ticks simulated +final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 702757 # Simulator instruction rate (inst/s) -host_op_rate 903702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27138460197 # Simulator tick rate (ticks/s) -host_mem_usage 475940 # Number of bytes of host memory used -host_seconds 85.96 # Real time elapsed on the host -sim_insts 60408649 # Number of instructions simulated -sim_ops 77681829 # Number of ops (including micro ops) simulated +host_inst_rate 1065837 # Simulator instruction rate (inst/s) +host_op_rate 1370594 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41157671581 # Simulator tick rate (ticks/s) +host_mem_usage 420236 # Number of bytes of host memory used +host_seconds 56.68 # Real time elapsed on the host +sim_insts 60411489 # Number of instructions simulated +sim_ops 77685090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory @@ -29,42 +29,42 @@ system.physmem.bytes_read::realview.clcd 111673344 # Nu system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071640 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071768 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3703424 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719240 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141780 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 141782 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57866 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811820 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3888717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3888770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1292781 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2880318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5181500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942190 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969605 # Throughput (bytes/s) -system.membus.data_through_bus 130566470 # Total data (bytes) +system.physmem.bw_total::cpu.data 5181551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942288 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55969769 # Throughput (bytes/s) +system.membus.data_through_bus 130566943 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -72,8 +72,8 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48895252 # Throughput (bytes/s) -system.iobus.data_through_bus 114063346 # Total data (bytes) +system.iobus.throughput 48895283 # Throughput (bytes/s) +system.iobus.data_through_bus 114063499 # Total data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -98,9 +98,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14971217 # DTB read hits +system.cpu.dtb.read_hits 14971763 # DTB read hits system.cpu.dtb.read_misses 7294 # DTB read misses -system.cpu.dtb.write_hits 11217004 # DTB write hits +system.cpu.dtb.write_hits 11217184 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -111,12 +111,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14978511 # DTB read accesses -system.cpu.dtb.write_accesses 11219185 # DTB write accesses +system.cpu.dtb.read_accesses 14979057 # DTB read accesses +system.cpu.dtb.write_accesses 11219365 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26188221 # DTB hits +system.cpu.dtb.hits 26188947 # DTB hits system.cpu.dtb.misses 9475 # DTB misses -system.cpu.dtb.accesses 26197696 # DTB accesses +system.cpu.dtb.accesses 26198422 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -138,7 +138,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61431840 # ITB inst hits +system.cpu.itb.inst_hits 61434680 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -155,42 +155,42 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61436311 # ITB inst accesses -system.cpu.itb.hits 61431840 # DTB hits +system.cpu.itb.inst_accesses 61439151 # ITB inst accesses +system.cpu.itb.hits 61434680 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61436311 # DTB accesses -system.cpu.numCycles 4665620539 # number of cpu cycles simulated +system.cpu.itb.accesses 61439151 # DTB accesses +system.cpu.numCycles 4665623800 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60408649 # Number of instructions committed -system.cpu.committedOps 77681829 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69130761 # Number of integer alu accesses +system.cpu.committedInsts 60411489 # Number of instructions committed +system.cpu.committedOps 77685090 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69133554 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2136008 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7942115 # number of instructions that are conditional controls -system.cpu.num_int_insts 69130761 # number of integer instructions +system.cpu.num_func_calls 2136078 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7942566 # number of instructions that are conditional controls +system.cpu.num_int_insts 69133554 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 355896757 # number of times the integer registers were read -system.cpu.num_int_register_writes 74438766 # number of times the integer registers were written +system.cpu.num_int_register_reads 355910547 # number of times the integer registers were read +system.cpu.num_int_register_writes 74442273 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27361639 # number of memory refs -system.cpu.num_load_insts 15639529 # Number of load instructions -system.cpu.num_store_insts 11722110 # Number of store instructions -system.cpu.num_idle_cycles 4586822073.007145 # Number of idle cycles -system.cpu.num_busy_cycles 78798465.992855 # Number of busy cycles -system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983111 # Percentage of idle cycles -system.cpu.Branches 10298723 # Number of branches fetched +system.cpu.num_mem_refs 27362421 # number of memory refs +system.cpu.num_load_insts 15640088 # Number of load instructions +system.cpu.num_store_insts 11722333 # Number of store instructions +system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles +system.cpu.num_busy_cycles 78801726.992856 # Number of busy cycles +system.cpu.not_idle_fraction 0.016890 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983110 # Percentage of idle cycles +system.cpu.Branches 10299261 # Number of branches fetched system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu.icache.tags.replacements 850590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60586338 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.678592 # Average occupied blocks per requestor +system.cpu.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.678462 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -199,32 +199,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 78 system.cpu.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62285702 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62285702 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits -system.cpu.icache.overall_hits::total 60583498 # number of overall hits +system.cpu.icache.tags.tag_accesses 62288542 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62288542 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60586338 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60586338 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60586338 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60586338 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60586338 # number of overall hits +system.cpu.icache.overall_hits::total 60586338 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses system.cpu.icache.overall_misses::total 851102 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 61437440 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61437440 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61437440 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013853 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013853 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013853 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -234,23 +234,23 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62243 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50007.272801 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582911 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 62245 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50007.460447 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1669929 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127630 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.084142 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36899.777920 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960146 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720467 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.716487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.011961 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563046 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.763053 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id @@ -261,15 +261,15 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9187 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52388 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17035899 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17035899 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 17035991 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17035991 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 366775 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1216282 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 592648 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 592648 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits @@ -277,13 +277,13 @@ system.cpu.l2cache.ReadExReq_hits::total 113739 # nu system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 480514 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1330021 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits -system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 480514 # number of overall hits +system.cpu.l2cache.overall_hits::total 1330021 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses @@ -291,39 +291,39 @@ system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133470 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133470 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143341 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153953 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses -system.cpu.l2cache.overall_misses::total 153951 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143341 # number of overall misses +system.cpu.l2cache.overall_misses::total 153953 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 376646 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1236765 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 592648 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 592648 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247209 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247209 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 623855 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1483974 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 623855 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1483974 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses @@ -331,18 +331,18 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539908 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.539908 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229767 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103744 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229767 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103744 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,14 +351,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks -system.cpu.l2cache.writebacks::total 57863 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57866 # number of writebacks +system.cpu.l2cache.writebacks::total 57866 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 623337 # number of replacements +system.cpu.dcache.tags.replacements 623343 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 23629012 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 623855 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.875808 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -368,44 +368,44 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 278 system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 97632617 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 97632617 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 97635323 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 97635323 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13180574 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13180574 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9962233 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9962233 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits -system.cpu.dcache.overall_hits::total 23142138 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 23142807 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23142807 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23142807 # number of overall hits +system.cpu.dcache.overall_hits::total 23142807 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 365463 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 365463 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250154 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses -system.cpu.dcache.overall_misses::total 615611 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 615617 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 615617 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615617 # number of overall misses +system.cpu.dcache.overall_misses::total 615617 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13546037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13546037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10212387 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23758424 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23758424 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23758424 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23758424 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses @@ -422,11 +422,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks -system.cpu.dcache.writebacks::total 592643 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592648 # number of writebacks +system.cpu.dcache.writebacks::total 592648 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 59102669 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 137875314 # Total data (bytes) +system.cpu.toL2Bus.throughput 59102995 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 137876171 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index dfe5d9e95..786f029ca 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.196139 # Number of seconds simulated -sim_ticks 1196139241000 # Number of ticks simulated -final_tick 1196139241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.196143 # Number of seconds simulated +sim_ticks 1196142873000 # Number of ticks simulated +final_tick 1196142873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 363491 # Simulator instruction rate (inst/s) -host_op_rate 463152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7074263356 # Simulator tick rate (ticks/s) -host_mem_usage 480032 # Number of bytes of host memory used -host_seconds 169.08 # Real time elapsed on the host -sim_insts 61460236 # Number of instructions simulated -sim_ops 78311148 # Number of ops (including micro ops) simulated +host_inst_rate 497666 # Simulator instruction rate (inst/s) +host_op_rate 634118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9685782626 # Simulator tick rate (ticks/s) +host_mem_usage 425428 # Number of bytes of host memory used +host_seconds 123.49 # Real time elapsed on the host +sim_insts 61459155 # Number of instructions simulated +sim_ops 78310163 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -34,141 +34,141 @@ system.realview.nvmem.bw_total::total 57 # To system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4714556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4724988 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4804536 # Number of bytes read from this memory -system.physmem.bytes_read::total 62141956 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4110528 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 324292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4798584 # Number of bytes read from this memory +system.physmem.bytes_read::total 62146244 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 324292 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4113152 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7137872 # Number of bytes written to this memory +system.physmem.bytes_written::total 7140496 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12371 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12374 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73902 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75099 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654445 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64227 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75006 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654512 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64268 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821063 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43393369 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821104 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43393238 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 328694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3941478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 328854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3950187 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 271437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4016703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51952109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 328694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 271437 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 600131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3436496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 271115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4011715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51955536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 328854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 271115 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 599968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3438680 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2516717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5967426 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3436496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43393369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2516709 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5969601 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3438680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43393238 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 328694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3955690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 328854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3964399 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 271437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6533420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57919534 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654445 # Number of read requests accepted -system.physmem.writeReqs 821063 # Number of write requests accepted -system.physmem.readBursts 6654445 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821063 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425854976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 29504 # Total number of bytes read from write queue -system.physmem.bytesWritten 7264576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62141956 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7137872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707541 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12043 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415328 # Per bank write bursts -system.physmem.perBankRdBursts::1 415204 # Per bank write bursts -system.physmem.perBankRdBursts::2 415403 # Per bank write bursts -system.physmem.perBankRdBursts::3 415627 # Per bank write bursts -system.physmem.perBankRdBursts::4 422407 # Per bank write bursts -system.physmem.perBankRdBursts::5 415617 # Per bank write bursts -system.physmem.perBankRdBursts::6 415785 # Per bank write bursts -system.physmem.perBankRdBursts::7 415500 # Per bank write bursts -system.physmem.perBankRdBursts::8 416027 # Per bank write bursts -system.physmem.perBankRdBursts::9 415632 # Per bank write bursts -system.physmem.perBankRdBursts::10 415316 # Per bank write bursts -system.physmem.perBankRdBursts::11 414840 # Per bank write bursts -system.physmem.perBankRdBursts::12 415044 # Per bank write bursts -system.physmem.perBankRdBursts::13 415557 # Per bank write bursts -system.physmem.perBankRdBursts::14 415554 # Per bank write bursts -system.physmem.perBankRdBursts::15 415143 # Per bank write bursts -system.physmem.perBankWrBursts::0 6946 # Per bank write bursts -system.physmem.perBankWrBursts::1 6844 # Per bank write bursts -system.physmem.perBankWrBursts::2 7080 # Per bank write bursts -system.physmem.perBankWrBursts::3 7140 # Per bank write bursts -system.physmem.perBankWrBursts::4 7438 # Per bank write bursts -system.physmem.perBankWrBursts::5 7223 # Per bank write bursts -system.physmem.perBankWrBursts::6 7431 # Per bank write bursts -system.physmem.perBankWrBursts::7 7190 # Per bank write bursts -system.physmem.perBankWrBursts::8 7575 # Per bank write bursts -system.physmem.perBankWrBursts::9 7264 # Per bank write bursts -system.physmem.perBankWrBursts::10 7139 # Per bank write bursts -system.physmem.perBankWrBursts::11 6649 # Per bank write bursts -system.physmem.perBankWrBursts::12 6729 # Per bank write bursts -system.physmem.perBankWrBursts::13 7011 # Per bank write bursts -system.physmem.perBankWrBursts::14 7090 # Per bank write bursts -system.physmem.perBankWrBursts::15 6760 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 271115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6528424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57925137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654512 # Number of read requests accepted +system.physmem.writeReqs 821104 # Number of write requests accepted +system.physmem.readBursts 6654512 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821104 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425857728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31040 # Total number of bytes read from write queue +system.physmem.bytesWritten 7268800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62146244 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7140496 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 485 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707525 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12040 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415388 # Per bank write bursts +system.physmem.perBankRdBursts::1 415219 # Per bank write bursts +system.physmem.perBankRdBursts::2 415339 # Per bank write bursts +system.physmem.perBankRdBursts::3 415675 # Per bank write bursts +system.physmem.perBankRdBursts::4 422392 # Per bank write bursts +system.physmem.perBankRdBursts::5 415542 # Per bank write bursts +system.physmem.perBankRdBursts::6 415783 # Per bank write bursts +system.physmem.perBankRdBursts::7 415483 # Per bank write bursts +system.physmem.perBankRdBursts::8 416074 # Per bank write bursts +system.physmem.perBankRdBursts::9 415577 # Per bank write bursts +system.physmem.perBankRdBursts::10 415249 # Per bank write bursts +system.physmem.perBankRdBursts::11 414844 # Per bank write bursts +system.physmem.perBankRdBursts::12 415143 # Per bank write bursts +system.physmem.perBankRdBursts::13 415555 # Per bank write bursts +system.physmem.perBankRdBursts::14 415561 # Per bank write bursts +system.physmem.perBankRdBursts::15 415203 # Per bank write bursts +system.physmem.perBankWrBursts::0 6999 # Per bank write bursts +system.physmem.perBankWrBursts::1 6843 # Per bank write bursts +system.physmem.perBankWrBursts::2 7018 # Per bank write bursts +system.physmem.perBankWrBursts::3 7170 # Per bank write bursts +system.physmem.perBankWrBursts::4 7419 # Per bank write bursts +system.physmem.perBankWrBursts::5 7182 # Per bank write bursts +system.physmem.perBankWrBursts::6 7433 # Per bank write bursts +system.physmem.perBankWrBursts::7 7180 # Per bank write bursts +system.physmem.perBankWrBursts::8 7611 # Per bank write bursts +system.physmem.perBankWrBursts::9 7217 # Per bank write bursts +system.physmem.perBankWrBursts::10 7107 # Per bank write bursts +system.physmem.perBankWrBursts::11 6660 # Per bank write bursts +system.physmem.perBankWrBursts::12 6804 # Per bank write bursts +system.physmem.perBankWrBursts::13 7009 # Per bank write bursts +system.physmem.perBankWrBursts::14 7096 # Per bank write bursts +system.physmem.perBankWrBursts::15 6827 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1196134740000 # Total gap between requests +system.physmem.totGap 1196138285000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6849 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159532 # Read request sizes (log2) +system.physmem.readPktSize::6 159599 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64227 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 627903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 474579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 475456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1579907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1133019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1127067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1123495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64268 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 628282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 475071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 476093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1580129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1132007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1126499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1123122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8860 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -183,29 +183,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5163 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -215,727 +215,726 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5818.973345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 397.615709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13075.139994 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25664 34.48% 34.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15269 20.51% 54.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3288 4.42% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2378 3.19% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1591 2.14% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1326 1.78% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1035 1.39% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1141 1.53% 69.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 724 0.97% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 588 0.79% 71.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 595 0.80% 72.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 643 0.86% 72.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 322 0.43% 73.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 287 0.39% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 216 0.29% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 358 0.48% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 180 0.24% 74.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 137 0.18% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 152 0.20% 75.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2272 3.05% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 131 0.18% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 156 0.21% 78.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 73 0.10% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 70 0.09% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 130 0.17% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 52 0.07% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 26 0.03% 79.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 15 0.02% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 134 0.18% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 21 0.03% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 27 0.04% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 25 0.03% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 14 0.02% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 24 0.03% 79.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 22 0.03% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 23 0.03% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 8 0.01% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 25 0.03% 80.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 35 0.05% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 11 0.01% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 26 0.03% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 8 0.01% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 105 0.14% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 6 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 7 0.01% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 41 0.06% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 7 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 26 0.03% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 85 0.11% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 5 0.01% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 20 0.03% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 29 0.04% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 86 0.12% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 19 0.03% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 202 0.27% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 3 0.00% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 6 0.01% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 18 0.02% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 2 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 20 0.03% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 17 0.02% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 92 0.12% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 17 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 96 0.13% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 30 0.04% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 172 0.23% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 8 0.01% 81.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 88 0.12% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 223 0.30% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 29 0.04% 82.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 24 0.03% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 22 0.03% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 74541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5810.577695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 397.196541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 13066.067638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25758 34.56% 34.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 15237 20.44% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3243 4.35% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2416 3.24% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1619 2.17% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1307 1.75% 66.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1041 1.40% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1103 1.48% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 718 0.96% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 614 0.82% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 577 0.77% 71.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 705 0.95% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 343 0.46% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 280 0.38% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 211 0.28% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 365 0.49% 74.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 178 0.24% 74.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.19% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 160 0.21% 75.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 121 0.16% 75.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2248 3.02% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 145 0.19% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 165 0.22% 78.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 59 0.08% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 66 0.09% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 116 0.16% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 53 0.07% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 27 0.04% 79.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 17 0.02% 79.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 120 0.16% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 17 0.02% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 29 0.04% 79.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 31 0.04% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 12 0.02% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 26 0.03% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 23 0.03% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 24 0.03% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 12 0.02% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 29 0.04% 80.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 10 0.01% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 25 0.03% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 133 0.18% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 12 0.02% 80.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 14 0.02% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 45 0.06% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 4 0.01% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 21 0.03% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.01% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 17 0.02% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 31 0.04% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 79 0.11% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 18 0.02% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 3 0.00% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 183 0.25% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 2 0.00% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 24 0.03% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 3 0.00% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 17 0.02% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 18 0.02% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 95 0.13% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 11 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 5 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 15 0.02% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 100 0.13% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 4 0.01% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 16 0.02% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 174 0.23% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 9 0.01% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 93 0.12% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 3 0.00% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 214 0.29% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 32 0.04% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 12 0.02% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 158 0.21% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 160 0.21% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 82.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7367 1 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 33 0.04% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 14 0.02% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 10 0.01% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 260 0.35% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 7 0.01% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 14 0.02% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 33 0.04% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 155 0.21% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9287 2 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 19 0.03% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 22 0.03% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 27 0.04% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 223 0.30% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 89 0.12% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 6 0.01% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 22 0.03% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 2 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11207 1 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 98 0.13% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 76 0.10% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 19 0.03% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 15 0.02% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 169 0.23% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 85 0.11% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 80 0.11% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 90 0.12% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13511 1 0.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 22 0.03% 84.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14023 1 0.00% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 7 0.01% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 2 0.00% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 95 0.13% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 100 0.13% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 2 0.00% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 74 0.10% 85.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 18 0.02% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 105 0.14% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 76 0.10% 85.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 18 0.02% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 76 0.10% 85.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 161 0.22% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 2 0.00% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 77 0.10% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 1 0.00% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 23 0.03% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 72 0.10% 86.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 107 0.14% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 15 0.02% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 76 0.10% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 97 0.13% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 102 0.14% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 2 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 4 0.01% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 1 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 78 0.10% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 82 0.11% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 16 0.02% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 83 0.11% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 81 0.11% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 176 0.24% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 2 0.00% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 17 0.02% 87.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 73 0.10% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 87 0.12% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 23 0.03% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 10 0.01% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 223 0.30% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 27 0.04% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 22 0.03% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 25 0.03% 88.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 23 0.03% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 12 0.02% 82.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 24 0.03% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 265 0.36% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 29 0.04% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 17 0.02% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 27 0.04% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 153 0.21% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 18 0.02% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 16 0.02% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 33 0.04% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 214 0.29% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 86 0.12% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 12 0.02% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 17 0.02% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 106 0.14% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 1 0.00% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 81 0.11% 84.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 14 0.02% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 16 0.02% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 3 0.00% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 158 0.21% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 76 0.10% 84.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 84 0.11% 84.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 29 0.04% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 105 0.14% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13383 1 0.00% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 26 0.03% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 13 0.02% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 92 0.12% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 80 0.11% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 81 0.11% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 16 0.02% 85.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 110 0.15% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 77 0.10% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15815 1 0.00% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 13 0.02% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 82 0.11% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 3 0.00% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 155 0.21% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 83 0.11% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 8 0.01% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 77 0.10% 86.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 119 0.16% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 21 0.03% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 82 0.11% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 80 0.11% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 83 0.11% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 3 0.00% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 10 0.01% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 1 0.00% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 83 0.11% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 103 0.14% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 25 0.03% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 80 0.11% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 1 0.00% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 73 0.10% 87.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 155 0.21% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 19 0.03% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 16 0.02% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 81 0.11% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 95 0.13% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 10 0.01% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 9 0.01% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 219 0.29% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 30 0.04% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::23424-23431 2 0.00% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 30 0.04% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 16 0.02% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 8 0.01% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 269 0.36% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 5 0.01% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 32 0.04% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25536-25543 1 0.00% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 144 0.19% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 22 0.03% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25927 1 0.00% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 20 0.03% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 26 0.03% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 224 0.30% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 85 0.11% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 1 0.00% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 6 0.01% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 26 0.03% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 2 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 89 0.12% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 73 0.10% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 18 0.02% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 16 0.02% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 1 0.00% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 161 0.22% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 2 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 84 0.11% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 80 0.11% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 15 0.02% 90.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 89 0.12% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 19 0.03% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 82 0.11% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 2 0.00% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 5 0.01% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 1 0.00% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 93 0.12% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 1 0.00% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 97 0.13% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 74 0.10% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31296-31303 1 0.00% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 16 0.02% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 105 0.14% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 2 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 73 0.10% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 21 0.03% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 75 0.10% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 157 0.21% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 81 0.11% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 29 0.04% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 2 0.00% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 73 0.10% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 105 0.14% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 16 0.02% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 71 0.10% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 97 0.13% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34759 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 90 0.12% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35008-35015 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 3 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 81 0.11% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 18 0.02% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 87 0.12% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 13 0.02% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 79 0.11% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36672-36679 2 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 156 0.21% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37056-37063 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 14 0.02% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 16 0.02% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 75 0.10% 93.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 86 0.12% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 24 0.03% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 6 0.01% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 85 0.11% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 221 0.30% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 25 0.03% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39360-39367 3 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 18 0.02% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 2 0.00% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 142 0.19% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 1 0.00% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 32 0.04% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 5 0.01% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 265 0.36% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 6 0.01% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 13 0.02% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 2 0.00% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 31 0.04% 94.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 24 0.03% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 20 0.03% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 27 0.04% 94.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 221 0.30% 95.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 85 0.11% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 22 0.03% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 84 0.11% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 73 0.10% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 13 0.02% 95.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 166 0.22% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 79 0.11% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 1 0.00% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 82 0.11% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 15 0.02% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 87 0.12% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 22 0.03% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 6 0.01% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 1 0.00% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 93 0.12% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 1 0.00% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 101 0.14% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 79 0.11% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 16 0.02% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 127 0.17% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 87 0.12% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 17 0.02% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48704-48711 1 0.00% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 76 0.10% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 12 0.02% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 5 0.01% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2061 2.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74432 # Bytes accessed per row activation -system.physmem.totQLat 159552537250 # Total ticks spent queuing -system.physmem.totMemAccLat 202473692250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33269920000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9651235000 # Total ticks spent accessing banks -system.physmem.avgQLat 23978.50 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1450.44 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::23808-23815 22 0.03% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23872-23879 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 13 0.02% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 23 0.03% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 3 0.00% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 273 0.37% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 26 0.03% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 2 0.00% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 24 0.03% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 143 0.19% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 12 0.02% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 28 0.04% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 214 0.29% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 90 0.12% 89.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 13 0.02% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 92 0.12% 89.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 79 0.11% 89.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 14 0.02% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 19 0.03% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 159 0.21% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 74 0.10% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 82 0.11% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 26 0.03% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 2 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 92 0.12% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 27 0.04% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 80 0.11% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 9 0.01% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 85 0.11% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 81 0.11% 90.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 79 0.11% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 18 0.02% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 112 0.15% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 76 0.10% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 8 0.01% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 82 0.11% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 154 0.21% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 83 0.11% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33095 1 0.00% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 23 0.03% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 76 0.10% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 112 0.15% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 18 0.02% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 79 0.11% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 80 0.11% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 78 0.10% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34880-34887 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35008-35015 2 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 8 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 80 0.11% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 27 0.04% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 91 0.12% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 82 0.11% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 73 0.10% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 149 0.20% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 15 0.02% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 14 0.02% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 80 0.11% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 93 0.12% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 10 0.01% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 11 0.01% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 90 0.12% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 212 0.28% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 27 0.04% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 11 0.01% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39872-39879 1 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 144 0.19% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 21 0.03% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 1 0.00% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 25 0.03% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 269 0.36% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 10 0.01% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 23 0.03% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 21 0.03% 94.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 11 0.01% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 1 0.00% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 31 0.04% 94.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 219 0.29% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43072-43079 1 0.00% 95.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 87 0.12% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 11 0.01% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 80 0.11% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 18 0.02% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 149 0.20% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 71 0.10% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 78 0.10% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 1 0.00% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 27 0.04% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 99 0.13% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 83 0.11% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46656-46663 1 0.00% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 11 0.01% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 90 0.12% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 82 0.11% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 83 0.11% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 18 0.02% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 130 0.17% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 2 0.00% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 100 0.13% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48576-48583 1 0.00% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 6 0.01% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 79 0.11% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 5 0.01% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2052 2.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74541 # Bytes accessed per row activation +system.physmem.totQLat 159547739500 # Total ticks spent queuing +system.physmem.totMemAccLat 202481649500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33270135000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9663775000 # Total ticks spent accessing banks +system.physmem.avgQLat 23977.62 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1452.32 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30428.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.95 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30429.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.50 # Average write queue length when enqueuing -system.physmem.readRowHits 6598277 # Number of row buffer hits during reads -system.physmem.writeRowHits 94784 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.60 # Average write queue length when enqueuing +system.physmem.readRowHits 6598250 # Number of row buffer hits during reads +system.physmem.writeRowHits 94811 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.49 # Row buffer hit rate for writes -system.physmem.avgGap 160007.15 # Average gap between requests +system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes +system.physmem.avgGap 160005.31 # Average gap between requests system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.90 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 59936382 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703367 # Transaction distribution -system.membus.trans_dist::ReadResp 7703367 # Transaction distribution -system.membus.trans_dist::WriteReq 767572 # Transaction distribution -system.membus.trans_dist::WriteResp 767572 # Transaction distribution -system.membus.trans_dist::Writeback 64227 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31703 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17214 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12043 # Transaction distribution -system.membus.trans_dist::ReadExReq 137706 # Transaction distribution -system.membus.trans_dist::ReadExResp 137264 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382576 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 4.94 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 59942042 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703387 # Transaction distribution +system.membus.trans_dist::ReadResp 7703387 # Transaction distribution +system.membus.trans_dist::WriteReq 767577 # Transaction distribution +system.membus.trans_dist::WriteResp 767577 # Transaction distribution +system.membus.trans_dist::Writeback 64268 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31533 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12040 # Transaction distribution +system.membus.trans_dist::ReadExReq 137758 # Transaction distribution +system.membus.trans_dist::ReadExResp 137334 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382660 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10292 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972063 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4365907 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972105 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366005 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17342035 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17342133 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390026 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20640 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20584 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375316 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19787746 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17382228 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19794734 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71692258 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71692258 # Total data (bytes) +system.membus.tot_pkt_size::total 71699246 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71699246 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224733500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224801500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9246500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9220500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9211003500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9211496500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5080947314 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5081612097 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657701499 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657936499 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69413 # number of replacements -system.l2c.tags.tagsinuse 53013.525953 # Cycle average of tags in use -system.l2c.tags.total_refs 1672541 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134599 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.426103 # Average number of references to valid blocks. +system.l2c.tags.replacements 69480 # number of replacements +system.l2c.tags.tagsinuse 52958.538682 # Cycle average of tags in use +system.l2c.tags.total_refs 1674406 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134639 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.436263 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40184.108166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40140.336267 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3710.656491 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4243.565236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742460 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2809.342303 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2063.107654 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.613161 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001545 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3711.388388 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4232.378884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742427 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2812.770235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2058.918835 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.612493 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056620 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064752 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056631 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064581 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031481 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808922 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042919 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031417 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808083 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65181 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65154 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8037 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55165 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1929 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8108 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55070 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994583 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17211018 # Number of tag accesses -system.l2c.tags.data_accesses 17211018 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3808 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419108 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1908 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464853 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143402 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1246251 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571037 # number of Writeback hits -system.l2c.Writeback_hits::total 571037 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1156 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 566 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1722 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 102 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56302 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52763 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109065 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3808 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419108 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5506 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1908 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464853 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196165 # number of demand (read+write) hits -system.l2c.demand_hits::total 1355316 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3808 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1739 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419108 # number of overall hits -system.l2c.overall_hits::cpu0.data 262229 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5506 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1908 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464853 # number of overall hits -system.l2c.overall_hits::cpu1.data 196165 # number of overall hits -system.l2c.overall_hits::total 1355316 # number of overall hits +system.l2c.tags.occ_task_id_percent::1024 0.994171 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17216542 # Number of tag accesses +system.l2c.tags.data_accesses 17216542 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 3810 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1731 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 419647 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 206017 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5550 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1931 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143237 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1246526 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 570959 # number of Writeback hits +system.l2c.Writeback_hits::total 570959 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1148 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 589 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 220 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 320 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56693 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52725 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109418 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3810 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1731 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 419647 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 262710 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5550 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1931 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464603 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 195962 # number of demand (read+write) hits +system.l2c.demand_hits::total 1355944 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 3810 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1731 # number of overall hits +system.l2c.overall_hits::cpu0.inst 419647 # number of overall hits +system.l2c.overall_hits::cpu0.data 262710 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5550 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1931 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464603 # 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mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865654 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.832621 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721649 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823224 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543840 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.579058 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561585 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013483 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65879.081350 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61338.254401 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.150437 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.392926 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.936960 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.567857 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.364211 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10006.310145 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54315.569856 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62669.317131 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1129,67 +1128,67 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119505667 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2535246 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535246 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767572 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767572 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 571037 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30983 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17532 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260644 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260644 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863518 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226193 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12684 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601780 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6235 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15427 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7672553 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27216160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41363346 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15236 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30075316 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39635324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7636 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138342022 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138342022 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4603396 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4759597686 # Layer occupancy (ticks) +system.toL2Bus.throughput 119544694 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2535779 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535779 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767577 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767577 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 570959 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30837 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17592 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48429 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260947 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260947 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1227966 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6129 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12680 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940064 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600791 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6258 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15477 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7673967 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27250848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41432384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30058932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39583066 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138377350 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138377350 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4615184 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4759626187 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1923628472 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1926082966 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1753100289 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1756498781 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8875000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2118090473 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2116921475 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2927544636 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 2926499865 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 9917499 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 9923499 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45391376 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671402 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671402 # Transaction distribution -system.iobus.trans_dist::WriteReq 7950 # Transaction distribution -system.iobus.trans_dist::WriteResp 7950 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45391348 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671431 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671431 # Transaction distribution +system.iobus.trans_dist::WriteReq 7963 # Transaction distribution +system.iobus.trans_dist::WriteResp 7963 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1206,17 +1205,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382576 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382660 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358704 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358788 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16112 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1233,14 +1232,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390026 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294406 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294538 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4034000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1250,7 +1249,7 @@ system.iobus.reqLayer4.occupancy 27000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) @@ -1286,9 +1285,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374626000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374697000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17778333501 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17777962501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1313,25 +1312,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7064121 # DTB read hits -system.cpu0.dtb.read_misses 3756 # DTB read misses -system.cpu0.dtb.write_hits 5649416 # DTB write hits -system.cpu0.dtb.write_misses 801 # DTB write misses +system.cpu0.dtb.read_hits 7070497 # DTB read hits +system.cpu0.dtb.read_misses 3747 # DTB read misses +system.cpu0.dtb.write_hits 5655659 # DTB write hits +system.cpu0.dtb.write_misses 806 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1708 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7067877 # DTB read accesses -system.cpu0.dtb.write_accesses 5650217 # DTB write accesses +system.cpu0.dtb.read_accesses 7074244 # DTB read accesses +system.cpu0.dtb.write_accesses 5656465 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12713537 # DTB hits -system.cpu0.dtb.misses 4557 # DTB misses -system.cpu0.dtb.accesses 12718094 # DTB accesses +system.cpu0.dtb.hits 12726156 # DTB hits +system.cpu0.dtb.misses 4553 # DTB misses +system.cpu0.dtb.accesses 12730709 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1353,7 +1352,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 29561361 # ITB inst hits +system.cpu0.itb.inst_hits 29571351 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1370,88 +1369,88 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29563566 # ITB inst accesses -system.cpu0.itb.hits 29561361 # DTB hits +system.cpu0.itb.inst_accesses 29573556 # ITB inst accesses +system.cpu0.itb.hits 29571351 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29563566 # DTB accesses -system.cpu0.numCycles 2392278482 # number of cpu cycles simulated +system.cpu0.itb.accesses 29573556 # DTB accesses +system.cpu0.numCycles 2392285746 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28863304 # Number of instructions committed -system.cpu0.committedOps 37189208 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33114268 # Number of integer alu accesses +system.cpu0.committedInsts 28873226 # Number of instructions committed +system.cpu0.committedOps 37212709 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33137047 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241816 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4372124 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33114268 # number of integer instructions +system.cpu0.num_func_calls 1242091 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373605 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33137047 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 192166322 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36246326 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192300691 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36265278 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13380719 # number of memory refs -system.cpu0.num_load_insts 7401377 # Number of load instructions -system.cpu0.num_store_insts 5979342 # Number of store instructions -system.cpu0.num_idle_cycles 2246536230.490122 # Number of idle cycles -system.cpu0.num_busy_cycles 145742251.509878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060922 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939078 # Percentage of idle cycles -system.cpu0.Branches 5599941 # Number of branches fetched +system.cpu0.num_mem_refs 13394015 # number of memory refs +system.cpu0.num_load_insts 7407936 # Number of load instructions +system.cpu0.num_store_insts 5986079 # Number of store instructions +system.cpu0.num_idle_cycles 2246427166.466122 # Number of idle cycles +system.cpu0.num_busy_cycles 145858579.533878 # Number of busy cycles +system.cpu0.not_idle_fraction 0.060970 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.939030 # Percentage of idle cycles +system.cpu0.Branches 5601726 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46939 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 424872 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.359183 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29135959 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425384 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.493312 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359183 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994842 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994842 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 46915 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 425414 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.356883 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29145407 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 425926 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.428335 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76234819000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.356883 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994838 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994838 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29986729 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29986729 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29135959 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29135959 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29135959 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29135959 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29135959 # number of overall hits -system.cpu0.icache.overall_hits::total 29135959 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425385 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425385 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425385 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425385 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425385 # number of overall misses -system.cpu0.icache.overall_misses::total 425385 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5898245722 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5898245722 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5898245722 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5898245722 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5898245722 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5898245722 # 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number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1460,128 +1459,128 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425385 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425385 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425385 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425385 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425385 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425385 # 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Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.775151 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.890186 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.890186 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.093016 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.888854 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.888854 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50852132 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50852132 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6594161 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6594161 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5344638 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5344638 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148004 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 148004 # 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average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.064033 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.064033 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5914.391124 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5914.391124 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24327.440240 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24327.440240 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 50903218 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50903218 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6600273 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6600273 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5350518 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5350518 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147975 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147975 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149621 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149621 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11950791 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11950791 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11950791 # number of overall hits +system.cpu0.dcache.overall_hits::total 11950791 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227769 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227769 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141711 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141711 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9370 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9370 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7532 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7532 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369480 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369480 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369480 # number of overall misses +system.cpu0.dcache.overall_misses::total 369480 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3309712250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3309712250 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5686464712 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5686464712 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92538750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 92538750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44740069 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44740069 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8996176962 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8996176962 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8996176962 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8996176962 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6828042 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6828042 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5492229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5492229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157345 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157345 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157153 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157153 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12320271 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12320271 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12320271 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12320271 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033358 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033358 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025802 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025802 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047928 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047928 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029990 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029990 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029990 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029990 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14531.004000 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14531.004000 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40127.193457 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40127.193457 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9876.067236 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9876.067236 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5939.998540 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5939.998540 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24348.210896 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24348.210896 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1590,62 +1589,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 305670 # number of writebacks -system.cpu0.dcache.writebacks::total 305670 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227537 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227537 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141373 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141373 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9339 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9339 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7479 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7479 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 368910 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 368910 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 368910 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 368910 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2850420254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2850420254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5353542767 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5353542767 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 74365250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74365250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29286440 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29286440 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8203963021 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8203963021 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8203963021 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8203963021 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13556999000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13556999000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167889500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167889500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14724888500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14724888500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025770 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025770 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059354 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059354 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047596 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047596 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029974 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029974 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12527.282394 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12527.282394 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37868.212226 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37868.212226 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7962.870757 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7962.870757 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.822971 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.822971 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306085 # number of writebacks +system.cpu0.dcache.writebacks::total 306085 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227769 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227769 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141711 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141711 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9370 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9370 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369480 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369480 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369480 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369480 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2852244750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2852244750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372105288 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5372105288 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73750250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73750250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29678931 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29678931 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8224350038 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8224350038 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8224350038 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8224350038 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13565968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13565968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170779500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170779500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14736748000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14736748000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033358 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033358 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025802 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025802 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047915 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047915 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029990 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029990 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.532698 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.532698 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37908.879960 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37908.879960 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7870.891142 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7870.891142 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3941.425100 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3941.425100 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1676,25 +1675,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8319266 # DTB read hits -system.cpu1.dtb.read_misses 3647 # DTB read misses -system.cpu1.dtb.write_hits 5834802 # DTB write hits -system.cpu1.dtb.write_misses 1433 # DTB write misses +system.cpu1.dtb.read_hits 8312417 # DTB read hits +system.cpu1.dtb.read_misses 3644 # DTB read misses +system.cpu1.dtb.write_hits 5828126 # DTB write hits +system.cpu1.dtb.write_misses 1438 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1864 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8322913 # DTB read accesses -system.cpu1.dtb.write_accesses 5836235 # DTB write accesses +system.cpu1.dtb.read_accesses 8316061 # DTB read accesses +system.cpu1.dtb.write_accesses 5829564 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14154068 # DTB hits -system.cpu1.dtb.misses 5080 # DTB misses -system.cpu1.dtb.accesses 14159148 # DTB accesses +system.cpu1.dtb.hits 14140543 # DTB hits +system.cpu1.dtb.misses 5082 # DTB misses +system.cpu1.dtb.accesses 14145625 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1716,7 +1715,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 33207997 # ITB inst hits +system.cpu1.itb.inst_hits 33196912 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1733,87 +1732,87 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33210168 # ITB inst accesses -system.cpu1.itb.hits 33207997 # DTB hits +system.cpu1.itb.inst_accesses 33199083 # ITB inst accesses +system.cpu1.itb.hits 33196912 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33210168 # DTB accesses -system.cpu1.numCycles 2390803785 # number of cpu cycles simulated +system.cpu1.itb.accesses 33199083 # DTB accesses +system.cpu1.numCycles 2390815191 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32596932 # Number of instructions committed -system.cpu1.committedOps 41121940 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37644247 # Number of integer alu accesses +system.cpu1.committedInsts 32585929 # Number of instructions committed +system.cpu1.committedOps 41097454 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37620588 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962790 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3735035 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37644247 # number of integer instructions +system.cpu1.num_func_calls 962436 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3733629 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37620588 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 218344706 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39781553 # number of times the integer registers were written +system.cpu1.num_int_register_reads 218203394 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39762349 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14692820 # number of memory refs -system.cpu1.num_load_insts 8641241 # Number of load instructions -system.cpu1.num_store_insts 6051579 # Number of store instructions -system.cpu1.num_idle_cycles 1874235342.195830 # Number of idle cycles -system.cpu1.num_busy_cycles 516568442.804169 # Number of busy cycles -system.cpu1.not_idle_fraction 0.216065 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.783935 # Percentage of idle cycles -system.cpu1.Branches 4947677 # Number of branches fetched +system.cpu1.num_mem_refs 14678716 # number of memory refs +system.cpu1.num_load_insts 8634369 # Number of load instructions +system.cpu1.num_store_insts 6044347 # Number of store instructions +system.cpu1.num_idle_cycles 1874341984.155535 # Number of idle cycles +system.cpu1.num_busy_cycles 516473206.844465 # Number of busy cycles +system.cpu1.not_idle_fraction 0.216024 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.783976 # Percentage of idle cycles +system.cpu1.Branches 4945874 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469929 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.566840 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32737552 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 470441 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.589071 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 93987616500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.566840 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934701 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 469670 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.560169 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32726726 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 470182 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.604379 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 94003216500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.560169 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934688 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934688 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33678434 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33678434 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32737552 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32737552 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32737552 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32737552 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32737552 # number of overall hits -system.cpu1.icache.overall_hits::total 32737552 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 470441 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 470441 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 470441 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 470441 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 470441 # number of overall misses -system.cpu1.icache.overall_misses::total 470441 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6446126723 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6446126723 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6446126723 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6446126723 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6446126723 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6446126723 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33207993 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33207993 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33207993 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33207993 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33207993 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33207993 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13702.306395 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13702.306395 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13702.306395 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13702.306395 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33667090 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33667090 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32726726 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32726726 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32726726 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32726726 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32726726 # number of overall hits +system.cpu1.icache.overall_hits::total 32726726 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 470182 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 470182 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 470182 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 470182 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 470182 # number of overall misses +system.cpu1.icache.overall_misses::total 470182 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6443403725 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6443403725 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6443403725 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6443403725 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6443403725 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6443403725 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196908 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33196908 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33196908 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33196908 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33196908 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33196908 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014163 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014163 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014163 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014163 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014163 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014163 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13704.062948 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13704.062948 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13704.062948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13704.062948 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1822,126 +1821,126 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470441 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 470441 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 470441 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 470441 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 470441 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 470441 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5503297277 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5503297277 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5503297277 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5503297277 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5503297277 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5503297277 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7106250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7106250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7106250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 7106250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014166 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014166 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014166 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11698.166778 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11698.166778 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11698.166778 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470182 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 470182 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 470182 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 470182 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 470182 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 470182 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5501099275 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5501099275 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5501099275 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5501099275 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5501099275 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5501099275 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6820250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6820250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6820250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6820250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014163 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014163 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014163 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11699.935929 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 292485 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.346411 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11976402 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292833 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.898403 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 85276695250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.346411 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920598 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920598 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 49497647 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 49497647 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 6954137 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6954137 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4834149 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4834149 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82001 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 82001 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82789 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82789 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11788286 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11788286 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11788286 # number of overall hits -system.cpu1.dcache.overall_hits::total 11788286 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170721 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170721 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150254 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150254 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11274 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11274 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10054 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10054 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320975 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320975 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320975 # number of overall misses -system.cpu1.dcache.overall_misses::total 320975 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219304994 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2219304994 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6585994013 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6585994013 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 97542000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 97542000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52010474 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 52010474 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8805299007 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8805299007 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8805299007 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8805299007 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7124858 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7124858 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4984403 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4984403 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93275 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 93275 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92843 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92843 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12109261 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12109261 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12109261 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12109261 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023961 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023961 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030145 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030145 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120868 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120868 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108290 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108290 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026507 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026507 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026507 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026507 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12999.601654 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12999.601654 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43832.403883 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 43832.403883 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8651.942523 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8651.942523 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5173.112592 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5173.112592 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27432.974553 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27432.974553 # average overall miss latency +system.cpu1.dcache.tags.replacements 292321 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.500981 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11963226 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 292696 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.872530 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 85292295250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.500981 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 361 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 49443351 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 49443351 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 6947316 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6947316 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4827697 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4827697 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82016 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 82016 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82738 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82738 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11775013 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11775013 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11775013 # number of overall hits +system.cpu1.dcache.overall_hits::total 11775013 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170735 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170735 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 150073 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 150073 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11224 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11224 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10063 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 52014971 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8788375265 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8788375265 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8788375265 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8788375265 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118051 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7118051 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977770 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4977770 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93240 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 93240 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92801 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92801 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12095821 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12095821 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12095821 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12095821 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023986 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023986 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030149 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030149 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120378 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120378 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108436 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108436 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026522 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026522 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026522 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026522 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13002.735221 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13002.735221 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43767.721489 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 43767.721489 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8600.877584 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8600.877584 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5168.932823 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5168.932823 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27394.501587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27394.501587 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1950,62 +1949,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265367 # number of writebacks -system.cpu1.dcache.writebacks::total 265367 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170721 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170721 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150254 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150254 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11274 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11274 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10053 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10053 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320975 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320975 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320975 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320975 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877186006 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877186006 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6262088987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6262088987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74982000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74982000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31903526 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31903526 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8139274993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8139274993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8139274993 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8139274993 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608498500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608498500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182871345 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182871345 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791369845 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791369845 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023961 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023961 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120868 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120868 # 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average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6650.878127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6650.878127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3173.532876 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3173.532876 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 264874 # number of writebacks +system.cpu1.dcache.writebacks::total 264874 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170735 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170735 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150073 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150073 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11224 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11224 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320808 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320808 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320808 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320808 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877877002 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877877002 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6244849733 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6244849733 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74077750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74077750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31889029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31889029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8122726735 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8122726735 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8122726735 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8122726735 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168606064250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168606064250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182609871 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182609871 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193788674121 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193788674121 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023986 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023986 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030149 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030149 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120378 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120378 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108426 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108426 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026522 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026522 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10998.781749 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10998.781749 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41612.080341 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41612.080341 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6599.942088 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6599.942088 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3169.253528 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3169.253528 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2029,10 +2028,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651805197501 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651805197501 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651805197501 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651805197501 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651823594501 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651823594501 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651823594501 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651823594501 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 48b455079..524da38ff 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616536 # Number of seconds simulated -sim_ticks 2616536483000 # Number of ticks simulated -final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616552 # Number of seconds simulated +sim_ticks 2616552083000 # Number of ticks simulated +final_tick 2616552083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 317845 # Simulator instruction rate (inst/s) -host_op_rate 404472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13815397020 # Simulator tick rate (ticks/s) -host_mem_usage 476964 # Number of bytes of host memory used -host_seconds 189.39 # Real time elapsed on the host -sim_insts 60197590 # Number of instructions simulated -sim_ops 76603983 # Number of ops (including micro ops) simulated +host_inst_rate 423166 # Simulator instruction rate (inst/s) +host_op_rate 538494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18392483259 # Simulator tick rate (ticks/s) +host_mem_usage 421292 # Number of bytes of host memory used +host_seconds 142.26 # Real time elapsed on the host +sim_insts 60200379 # Number of instructions simulated +sim_ops 76607188 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory @@ -29,59 +29,59 @@ system.physmem.bytes_read::realview.clcd 122683392 # Nu system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9089752 # Number of bytes read from this memory -system.physmem.bytes_read::total 132477536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089880 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477664 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory +system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142063 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494705 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 142065 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494707 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46887426 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3473963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50630877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1416443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3473992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50630624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1416484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1152689 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2569173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1416484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46887426 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4626660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53200016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494705 # Number of read requests accepted -system.physmem.writeReqs 811927 # Number of write requests accepted -system.physmem.readBursts 15494705 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991556032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue -system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132477536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.inst 269035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4626681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53199797 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494707 # Number of read requests accepted +system.physmem.writeReqs 811929 # Number of write requests accepted +system.physmem.readBursts 15494707 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991550144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 111104 # Total number of bytes read from write queue +system.physmem.bytesWritten 6844864 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132477664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1736 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 704958 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 967983 # Per bank write bursts -system.physmem.perBankRdBursts::1 967714 # Per bank write bursts +system.physmem.perBankRdBursts::1 967715 # Per bank write bursts system.physmem.perBankRdBursts::2 967672 # Per bank write bursts system.physmem.perBankRdBursts::3 967769 # Per bank write bursts system.physmem.perBankRdBursts::4 974609 # Per bank write bursts system.physmem.perBankRdBursts::5 968229 # Per bank write bursts -system.physmem.perBankRdBursts::6 967807 # Per bank write bursts +system.physmem.perBankRdBursts::6 967819 # Per bank write bursts system.physmem.perBankRdBursts::7 967736 # Per bank write bursts system.physmem.perBankRdBursts::8 968546 # Per bank write bursts system.physmem.perBankRdBursts::9 968137 # Per bank write bursts @@ -89,58 +89,58 @@ system.physmem.perBankRdBursts::10 967949 # Pe system.physmem.perBankRdBursts::11 967746 # Per bank write bursts system.physmem.perBankRdBursts::12 967851 # Per bank write bursts system.physmem.perBankRdBursts::13 967741 # Per bank write bursts -system.physmem.perBankRdBursts::14 967778 # Per bank write bursts -system.physmem.perBankRdBursts::15 967796 # Per bank write bursts -system.physmem.perBankWrBursts::0 6610 # Per bank write bursts +system.physmem.perBankRdBursts::14 967672 # Per bank write bursts +system.physmem.perBankRdBursts::15 967797 # Per bank write bursts +system.physmem.perBankWrBursts::0 6609 # Per bank write bursts system.physmem.perBankWrBursts::1 6410 # Per bank write bursts -system.physmem.perBankWrBursts::2 6422 # Per bank write bursts -system.physmem.perBankWrBursts::3 6344 # Per bank write bursts -system.physmem.perBankWrBursts::4 6906 # Per bank write bursts -system.physmem.perBankWrBursts::5 7096 # Per bank write bursts -system.physmem.perBankWrBursts::6 6901 # Per bank write bursts -system.physmem.perBankWrBursts::7 6892 # Per bank write bursts -system.physmem.perBankWrBursts::8 7193 # Per bank write bursts -system.physmem.perBankWrBursts::9 6845 # Per bank write bursts -system.physmem.perBankWrBursts::10 6667 # Per bank write bursts -system.physmem.perBankWrBursts::11 6550 # Per bank write bursts -system.physmem.perBankWrBursts::12 6596 # Per bank write bursts -system.physmem.perBankWrBursts::13 6392 # Per bank write bursts -system.physmem.perBankWrBursts::14 6532 # Per bank write bursts -system.physmem.perBankWrBursts::15 6576 # Per bank write bursts +system.physmem.perBankWrBursts::2 6425 # Per bank write bursts +system.physmem.perBankWrBursts::3 6343 # Per bank write bursts +system.physmem.perBankWrBursts::4 6914 # Per bank write bursts +system.physmem.perBankWrBursts::5 7103 # Per bank write bursts +system.physmem.perBankWrBursts::6 6905 # Per bank write bursts +system.physmem.perBankWrBursts::7 6899 # Per bank write bursts +system.physmem.perBankWrBursts::8 7185 # Per bank write bursts +system.physmem.perBankWrBursts::9 6844 # Per bank write bursts +system.physmem.perBankWrBursts::10 6668 # Per bank write bursts +system.physmem.perBankWrBursts::11 6551 # Per bank write bursts +system.physmem.perBankWrBursts::12 6595 # Per bank write bursts +system.physmem.perBankWrBursts::13 6390 # Per bank write bursts +system.physmem.perBankWrBursts::14 6535 # Per bank write bursts +system.physmem.perBankWrBursts::15 6575 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2616532122000 # Total gap between requests +system.physmem.totGap 2616547722000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15335424 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152617 # Read request sizes (log2) +system.physmem.readPktSize::6 152619 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57909 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1247001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1099674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1103822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2684241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2677986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2686359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 54486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 161 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57911 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1246677 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1099488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1103361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2684438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2678406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2686634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 54458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20429 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 160 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -156,28 +156,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4864 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4863 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4863 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4862 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -188,453 +188,464 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89676 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11133.405772 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1028.811660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16712.159564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23202 25.87% 25.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14564 16.24% 42.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2857 3.19% 45.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2044 2.28% 47.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1359 1.52% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1218 1.36% 50.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 957 1.07% 51.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1129 1.26% 52.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 646 0.72% 53.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 589 0.66% 54.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 513 0.57% 54.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 690 0.77% 55.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 338 0.38% 55.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 262 0.29% 56.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 213 0.24% 56.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 156 0.17% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 151 0.17% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 136 0.15% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 156 0.17% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 102 0.11% 58.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2292 2.56% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 63 0.07% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 60 0.07% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 44 0.05% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 133 0.15% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 30 0.03% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 25 0.03% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 303 0.34% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 33 0.04% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.01% 61.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 97 0.11% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 22 0.02% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 14 0.02% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 28 0.03% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 19 0.02% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 14 0.02% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 14 0.02% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 9 0.01% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 370 0.41% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 11 0.01% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 17 0.02% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 15 0.02% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 14 0.02% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 102 0.11% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 12 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 37 0.04% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 13 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 11 0.01% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 225 0.25% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 9 0.01% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 10 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 165 0.18% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 10 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 83 0.09% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 88 0.10% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 435 0.49% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 9 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 6 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 9 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 26 0.03% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 67 0.07% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 8 0.01% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 280 0.31% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 72 0.08% 65.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 269 0.30% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 83 0.09% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 89706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11129.630393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1027.657053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16709.623735 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23265 25.93% 25.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14539 16.21% 42.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2841 3.17% 45.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2049 2.28% 47.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1384 1.54% 49.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1206 1.34% 50.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 956 1.07% 51.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1124 1.25% 52.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 653 0.73% 53.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 549 0.61% 54.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 562 0.63% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 672 0.75% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 328 0.37% 55.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 247 0.28% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 203 0.23% 56.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 737 0.82% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 166 0.19% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 147 0.16% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 151 0.17% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 100 0.11% 58.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2290 2.55% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 54 0.06% 61.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 47 0.05% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 132 0.15% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 20 0.02% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 24 0.03% 61.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 30 0.03% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 15 0.02% 61.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 101 0.11% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 16 0.02% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 24 0.03% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 89 0.10% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 8 0.01% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 22 0.02% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 154 0.17% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 15 0.02% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 13 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 380 0.42% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 15 0.02% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 13 0.01% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 16 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 17 0.02% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 10 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 98 0.11% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 14 0.02% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 34 0.04% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 92 0.10% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 11 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 10 0.01% 63.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 9 0.01% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 228 0.25% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 8 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 164 0.18% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 10 0.01% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 80 0.09% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 9 0.01% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 8 0.01% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 90 0.10% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 8 0.01% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 9 0.01% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 436 0.49% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 10 0.01% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 7 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 28 0.03% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 68 0.08% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 11 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 279 0.31% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 70 0.08% 65.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 270 0.30% 65.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 65.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 82 0.09% 65.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6791 3 0.00% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 142 0.16% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 1 0.00% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 2 0.00% 65.61% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 21 0.02% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 66.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 77 0.09% 66.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 78 0.09% 66.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 401 0.45% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 24 0.03% 66.85% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 18 0.02% 68.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 6 0.01% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 429 0.48% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 85 0.09% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 79 0.09% 68.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 159 0.18% 69.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 7 0.01% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 431 0.48% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 83 0.09% 68.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 80 0.09% 68.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 159 0.18% 69.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::12160-12167 2 0.00% 69.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::12288-12295 208 0.23% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 83 0.09% 69.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 89 0.10% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 144 0.16% 69.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 350 0.39% 70.09% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 148 0.16% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 354 0.39% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 2 0.00% 70.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 141 0.16% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13639 1 0.00% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 73 0.08% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 83 0.09% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14279 1 0.00% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 279 0.31% 70.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 93 0.10% 70.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14663 1 0.00% 70.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 91 0.10% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 15 0.02% 70.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 4 0.00% 70.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 490 0.55% 71.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 72 0.08% 71.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 2 0.00% 71.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 143 0.16% 71.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 77 0.09% 71.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 10 0.01% 71.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 534 0.60% 72.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 75 0.08% 72.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 145 0.16% 72.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 76 0.08% 72.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::17280-17287 3 0.00% 72.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::17408-17415 492 0.55% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 15 0.02% 73.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 87 0.10% 73.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 73.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 16 0.02% 73.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 2 0.00% 73.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 87 0.10% 73.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 100 0.11% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 2 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 274 0.31% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 95 0.11% 73.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 2 0.00% 73.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 275 0.31% 73.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 80 0.09% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 72 0.08% 74.06% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 1 0.00% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 347 0.39% 74.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::19584-19591 2 0.00% 74.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 134 0.15% 74.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 136 0.15% 74.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::19776-19783 1 0.00% 74.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 89 0.10% 74.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 88 0.10% 74.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 82 0.09% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 84 0.09% 74.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::20352-20359 5 0.01% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 2 0.00% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 211 0.24% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 155 0.17% 75.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 77 0.09% 75.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 216 0.24% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20551 1 0.00% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 155 0.17% 75.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 77 0.09% 75.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 82 0.09% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 2 0.00% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 418 0.47% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 17 0.02% 76.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 143 0.16% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22215 1 0.00% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 76 0.08% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 5 0.01% 76.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 264 0.29% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 24 0.03% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 79 0.09% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 5 0.01% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 419 0.47% 76.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21696-21703 1 0.00% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 21 0.02% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 147 0.16% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 72 0.08% 76.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 4 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 265 0.30% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 21 0.02% 76.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::23040-23047 84 0.09% 76.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 139 0.16% 76.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 3 0.00% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 413 0.46% 77.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.34% # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 3 0.00% 78.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 76 0.08% 78.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 19 0.02% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 88 0.10% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 78.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 83 0.09% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 2 0.00% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 75 0.08% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 159 0.18% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 210 0.23% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 77 0.09% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.66% # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 71 0.08% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 80 0.09% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 2 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 274 0.31% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 91 0.10% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 90 0.10% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 17 0.02% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 485 0.54% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 77 0.09% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 143 0.16% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 2 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 84 0.09% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 538 0.60% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 86 0.10% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 150 0.17% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 80 0.09% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 484 0.54% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 12 0.01% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 89 0.10% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 274 0.31% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 69 0.08% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 144 0.16% 79.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 23 0.03% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 414 0.46% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 1 0.00% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 80 0.09% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 2 0.00% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 76 0.08% 80.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.17% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 346 0.39% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 142 0.16% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 1 0.00% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 72 0.08% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 82 0.09% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 276 0.31% 81.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 91 0.10% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 88 0.10% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 20 0.02% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 482 0.54% 82.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 73 0.08% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 142 0.16% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 2 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 83 0.09% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32704-32711 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 535 0.60% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 89 0.10% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 149 0.17% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 76 0.08% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 481 0.54% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 15 0.02% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 88 0.10% 84.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 94 0.10% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34624-34631 3 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 264 0.29% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 79 0.09% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 2 0.00% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 71 0.08% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35392-35399 1 0.00% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 144 0.16% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 347 0.39% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 133 0.15% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 87 0.10% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36416-36423 1 0.00% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 92 0.10% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34624-34631 1 0.00% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 3 0.00% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 267 0.30% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 2 0.00% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 81 0.09% 85.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 74 0.08% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 144 0.16% 85.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 346 0.39% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 134 0.15% 85.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 86 0.10% 86.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::36480-36487 1 0.00% 86.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 78 0.09% 86.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 204 0.23% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 155 0.17% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 74 0.08% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37568-37575 2 0.00% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 89 0.10% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 419 0.47% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 79 0.09% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 207 0.23% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37056-37063 1 0.00% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 154 0.17% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 75 0.08% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 87 0.10% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 418 0.47% 87.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 18 0.02% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 140 0.16% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 3 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 69 0.08% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 2 0.00% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 266 0.30% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 19 0.02% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39303 2 0.00% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 88 0.10% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 20 0.02% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38208-38215 1 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 142 0.16% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 3 0.00% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 69 0.08% 87.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 267 0.30% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 18 0.02% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39303 2 0.00% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 85 0.09% 87.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 145 0.16% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 410 0.46% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 83 0.09% 88.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 2 0.00% 88.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 17 0.02% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 397 0.44% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 75 0.08% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 24 0.03% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 2 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 145 0.16% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 411 0.46% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 83 0.09% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40263 1 0.00% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40320-40327 2 0.00% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 16 0.02% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 79 0.09% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 395 0.44% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 17 0.02% 89.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::41600-41607 3 0.00% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 83 0.09% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 408 0.45% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 140 0.16% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 82 0.09% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 25 0.03% 90.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 264 0.29% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 2 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 89 0.10% 89.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 405 0.45% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42048-42055 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 142 0.16% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 82 0.09% 90.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 22 0.02% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 265 0.30% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 73 0.08% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 142 0.16% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 17 0.02% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 418 0.47% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 82 0.09% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 69 0.08% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 144 0.16% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 21 0.02% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 417 0.46% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 79 0.09% 91.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::44544-44551 77 0.09% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 156 0.17% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 198 0.22% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45120-45127 2 0.00% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 81 0.09% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 90 0.10% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 154 0.17% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 203 0.23% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 82 0.09% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 88 0.10% 91.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 133 0.15% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 135 0.15% 92.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::45952-45959 2 0.00% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 350 0.39% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 348 0.39% 92.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::46336-46343 145 0.16% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 72 0.08% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 3 0.00% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 83 0.09% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 73 0.08% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 84 0.09% 92.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 266 0.30% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 97 0.11% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 5 0.01% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 17 0.02% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 515 0.57% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 2 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 100 0.11% 94.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 142 0.16% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 8 0.01% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5062 5.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89676 # Bytes accessed per row activation -system.physmem.totQLat 373682624750 # Total ticks spent queuing -system.physmem.totMemAccLat 469595819750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77465315000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18447880000 # Total ticks spent accessing banks -system.physmem.avgQLat 24119.35 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1190.72 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::47104-47111 268 0.30% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 92 0.10% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47680-47687 1 0.00% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 19 0.02% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48064-48071 1 0.00% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 511 0.57% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 2 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 2 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 90 0.10% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 140 0.16% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 6 0.01% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 6 0.01% 94.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5078 5.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89706 # Bytes accessed per row activation +system.physmem.totQLat 373696644500 # Total ticks spent queuing +system.physmem.totMemAccLat 469604897000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77464855000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18443397500 # Total ticks spent accessing banks +system.physmem.avgQLat 24120.40 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1190.44 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30310.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30310.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 378.95 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s @@ -643,45 +654,45 @@ system.physmem.busUtil 2.98 # Da system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing -system.physmem.readRowHits 15419173 # Number of row buffer hits during reads -system.physmem.writeRowHits 91146 # Number of row buffer hits during writes +system.physmem.avgWrQLen 14.55 # Average write queue length when enqueuing +system.physmem.readRowHits 15419069 # Number of row buffer hits during reads +system.physmem.writeRowHits 91147 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.22 # Row buffer hit rate for writes -system.physmem.avgGap 160458.16 # Average gap between requests -system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.writeRowHitRate 85.21 # Row buffer hit rate for writes +system.physmem.avgGap 160459.07 # Average gap between requests +system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54116538 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546563 # Transaction distribution -system.membus.trans_dist::ReadResp 16546563 # Transaction distribution -system.membus.trans_dist::WriteReq 763368 # Transaction distribution -system.membus.trans_dist::WriteResp 763368 # Transaction distribution -system.membus.trans_dist::Writeback 57909 # Transaction distribution +system.membus.throughput 54116372 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546597 # Transaction distribution +system.membus.trans_dist::ReadResp 16546597 # Transaction distribution +system.membus.trans_dist::WriteReq 763385 # Transaction distribution +system.membus.trans_dist::WriteResp 763385 # Transaction distribution +system.membus.trans_dist::Writeback 57911 # Transaction distribution system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution -system.membus.trans_dist::ReadExReq 132216 # Transaction distribution -system.membus.trans_dist::ReadExResp 132216 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 132218 # Transaction distribution +system.membus.trans_dist::ReadExResp 132218 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383088 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893537 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893543 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280493 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951233 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34951341 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390542 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914505 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914914 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141597897 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141597897 # Total data (bytes) +system.membus.tot_pkt_size::total 141598306 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141598306 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206226000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -689,11 +700,11 @@ system.membus.reqLayer2.occupancy 3614000 # La system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17910622000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17910626500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4950375335 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4950468826 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34635983250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34635984750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -701,12 +712,12 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47801275 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution -system.iobus.trans_dist::WriteReq 8166 # Transaction distribution -system.iobus.trans_dist::WriteResp 8166 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.throughput 47801049 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518785 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518785 # Transaction distribution +system.iobus.trans_dist::WriteReq 8183 # Transaction distribution +system.iobus.trans_dist::WriteResp 8183 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) @@ -729,11 +740,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 33053936 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) @@ -756,12 +767,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390542 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073781 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 125073934 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073934 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -809,9 +820,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374905000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42035727250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -837,9 +848,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995647 # DTB read hits +system.cpu.dtb.read_hits 14996193 # DTB read hits system.cpu.dtb.read_misses 7334 # DTB read misses -system.cpu.dtb.write_hits 11230146 # DTB write hits +system.cpu.dtb.write_hits 11230326 # DTB write hits system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -850,12 +861,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002981 # DTB read accesses -system.cpu.dtb.write_accesses 11232358 # DTB write accesses +system.cpu.dtb.read_accesses 15003527 # DTB read accesses +system.cpu.dtb.write_accesses 11232538 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26225793 # DTB hits +system.cpu.dtb.hits 26226519 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 26235339 # DTB accesses +system.cpu.dtb.accesses 26236065 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -877,7 +888,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61491413 # ITB inst hits +system.cpu.itb.inst_hits 61494253 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -894,88 +905,88 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495884 # ITB inst accesses -system.cpu.itb.hits 61491413 # DTB hits +system.cpu.itb.inst_accesses 61498724 # ITB inst accesses +system.cpu.itb.hits 61494253 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495884 # DTB accesses -system.cpu.numCycles 5233072966 # number of cpu cycles simulated +system.cpu.itb.accesses 61498724 # DTB accesses +system.cpu.numCycles 5233104166 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197590 # Number of instructions committed -system.cpu.committedOps 76603983 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69206189 # Number of integer alu accesses +system.cpu.committedInsts 60200379 # Number of instructions committed +system.cpu.committedOps 76607188 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69208982 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140403 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948249 # number of instructions that are conditional controls -system.cpu.num_int_insts 69206189 # number of integer instructions +system.cpu.num_func_calls 2140473 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948700 # number of instructions that are conditional controls +system.cpu.num_int_insts 69208982 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 401354573 # number of times the integer registers were read -system.cpu.num_int_register_writes 74515956 # number of times the integer registers were written +system.cpu.num_int_register_reads 401369988 # number of times the integer registers were read +system.cpu.num_int_register_writes 74519463 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393282 # number of memory refs -system.cpu.num_load_insts 15659729 # Number of load instructions -system.cpu.num_store_insts 11733553 # Number of store instructions -system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles -system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles -system.cpu.not_idle_fraction 0.124505 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875495 # Percentage of idle cycles -system.cpu.Branches 10308279 # Number of branches fetched +system.cpu.num_mem_refs 27394064 # number of memory refs +system.cpu.num_load_insts 15660288 # Number of load instructions +system.cpu.num_store_insts 11733776 # Number of store instructions +system.cpu.num_idle_cycles 4581523252.608249 # Number of idle cycles +system.cpu.num_busy_cycles 651580913.391751 # Number of busy cycles +system.cpu.not_idle_fraction 0.124511 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875489 # Percentage of idle cycles +system.cpu.Branches 10308817 # Number of branches fetched system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed system.cpu.icache.tags.replacements 856260 # number of replacements -system.cpu.icache.tags.tagsinuse 510.868407 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60634641 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 510.867590 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60637481 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.771035 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.868407 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy +system.cpu.icache.tags.avg_refs 70.774350 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19998571250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.867590 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997788 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997788 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62348185 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62348185 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60634641 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60634641 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60634641 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60634641 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60634641 # number of overall hits -system.cpu.icache.overall_hits::total 60634641 # number of overall hits +system.cpu.icache.tags.tag_accesses 62351025 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62351025 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60637481 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60637481 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60637481 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60637481 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60637481 # number of overall hits +system.cpu.icache.overall_hits::total 60637481 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 856772 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 856772 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 856772 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses system.cpu.icache.overall_misses::total 856772 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11774021000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11774021000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11774021000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11774021000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11774021000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11774021000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491413 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491413 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491413 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11774299750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11774299750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11774299750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11774299750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11774299750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11774299750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61494253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61494253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61494253 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61494253 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61494253 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61494253 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.303670 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13742.303670 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13742.303670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13742.303670 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.629019 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13742.629019 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.629019 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13742.629019 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.629019 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13742.629019 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -990,12 +1001,12 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 856772 system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056430000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10056430000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056430000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10056430000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056430000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10056430000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056704250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10056704250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056704250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10056704250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056704250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10056704250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435943750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435943750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435943750 # number of overall MSHR uncacheable cycles @@ -1006,34 +1017,34 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.580126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.580126 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.900223 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.900223 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.900223 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.900223 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.900223 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.900223 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62509 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50754.656257 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1682272 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.153951 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37718.394097 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 62511 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50754.773862 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1682280 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127893 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.153808 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2565659385000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37718.578019 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884348 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400068 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977018 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.361988 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.948805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.575540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106710 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.774456 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id @@ -1044,15 +1055,15 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6898 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56267 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17137304 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17137304 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 17137404 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17137404 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 844551 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 369631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226419 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595233 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595233 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 369636 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226424 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595238 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595238 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 752786250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10359035143 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11112276643 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 752512000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10356829393 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11109796643 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 752786250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10359035143 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11112276643 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8710 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3534 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 855136 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 379440 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1246820 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 595233 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 595233 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 379445 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1246825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 595238 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 595238 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2934 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2934 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247211 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247211 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247213 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247213 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8710 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3534 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 855136 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 626651 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494031 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 626658 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494038 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8710 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3534 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 855136 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 626651 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494031 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 626658 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494038 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses @@ -1133,37 +1144,37 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025851 system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991138 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991138 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541331 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541331 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541335 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541335 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.229206 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103227 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103228 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.229206 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103227 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103228 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71092.300425 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75128.147620 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73030.697025 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71118.209731 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75229.228260 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73092.740552 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.616231 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.616231 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71885.231933 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71885.231933 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71893.231033 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71893.231033 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71092.300425 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72106.699016 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72036.755907 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71118.209731 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72121.051722 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72051.902033 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71092.300425 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72106.699016 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72036.755907 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71118.209731 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72121.051722 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72051.902033 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1172,8 +1183,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57909 # number of writebacks -system.cpu.l2cache.writebacks::total 57909 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57911 # number of writebacks +system.cpu.l2cache.writebacks::total 57911 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10585 # number of ReadReq MSHR misses @@ -1181,45 +1192,45 @@ system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9809 system.cpu.l2cache.ReadReq_mshr_misses::total 20401 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2908 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2908 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133823 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133823 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133825 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133825 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 10585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143632 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154224 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143634 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154226 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143632 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154224 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143634 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154226 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619946000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 614046500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1234360250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 620216750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 615039000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1235623500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29085908 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29085908 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7945262107 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7945262107 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7946453357 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7946453357 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619946000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8559308607 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9179622357 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 620216750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8561492357 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9182076857 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619946000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8559308607 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9179622357 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 620216750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8561492357 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9182076857 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 344358750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657044750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167001403500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702635150 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702635150 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664193250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167008552000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706218159 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706218159 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 344358750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359679900 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183704038650 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370411409 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183714770159 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses @@ -1227,37 +1238,37 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991138 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991138 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541331 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541331 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541335 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541335 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103227 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103228 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103227 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103228 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58568.351441 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62600.316036 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60504.889466 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58593.930090 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62701.498624 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60566.810450 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59371.424247 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59371.424247 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59379.438498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59379.438498 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58593.930090 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59606.307399 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59536.503942 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58593.930090 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59606.307399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59536.503942 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1267,13 +1278,13 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626139 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.876590 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655440 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626651 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.748986 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 626146 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.876591 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23656108 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626658 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.749631 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 664772250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.876590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.876591 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1281,54 +1292,54 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 97755015 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 97755015 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13195741 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195741 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972594 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972594 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 97757722 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 97757722 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13196248 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196248 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972755 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972755 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236393 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236393 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168335 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168335 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168335 # number of overall hits -system.cpu.dcache.overall_hits::total 23168335 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368054 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368054 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250145 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250145 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 23169003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23169003 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23169003 # number of overall hits +system.cpu.dcache.overall_hits::total 23169003 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368059 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368059 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250147 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250147 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 11386 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11386 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618199 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618199 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618199 # number of overall misses -system.cpu.dcache.overall_misses::total 618199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5415523000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5415523000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11621830515 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11621830515 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158390000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158390000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17037353515 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17037353515 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17037353515 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17037353515 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222739 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 618206 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618206 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618206 # number of overall misses +system.cpu.dcache.overall_misses::total 618206 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416606500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5416606500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11623055265 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11623055265 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158362000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158362000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17039661765 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17039661765 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17039661765 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17039661765 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564307 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564307 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222902 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222902 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23786534 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23786534 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23786534 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23786534 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027135 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027135 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23787209 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787209 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787209 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787209 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027134 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027134 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses @@ -1337,16 +1348,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.935999 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.935999 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46460.375042 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46460.375042 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13910.943264 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13910.943264 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27559.658807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27559.658807 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14716.679934 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14716.679934 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46464.899699 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46464.899699 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13908.484103 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13908.484103 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27563.080535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27563.080535 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1355,36 +1366,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595233 # number of writebacks -system.cpu.dcache.writebacks::total 595233 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368054 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368054 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250145 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250145 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 595238 # number of writebacks +system.cpu.dcache.writebacks::total 595238 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250147 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618199 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618199 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618199 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618199 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677118000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677118000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069604485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069604485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135564000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135564000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15746722485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15746722485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15746722485 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15746722485 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050737750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050737750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284890100 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284890100 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 618206 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618206 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618206 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618206 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678192500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678192500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11070820735 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11070820735 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135536000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135536000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15749013235 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15749013235 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15749013235 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15749013235 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058328250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058328250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26237936841 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26237936841 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208296265091 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208296265091 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027134 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027134 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses @@ -1393,16 +1404,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12707.695066 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12707.695066 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44252.751344 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44252.751344 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11906.200597 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11906.200597 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12710.441804 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12710.441804 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44257.259671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44257.259671 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11903.741437 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11903.741437 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1410,33 +1421,33 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52965212 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595233 # Transaction distribution +system.cpu.toL2Bus.throughput 52965248 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 595238 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247213 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749353 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749474 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7514413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514534 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755228 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614893 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615814 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138419097 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138419097 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138420018 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138420018 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3008588500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3008633500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295451750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295454000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2534384415 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2534439174 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1458,10 +1469,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1538393065750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1538393065750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1538398399250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1538398399250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 4226653cc..e35c391b5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332810 # Number of seconds simulated -sim_ticks 2332810269000 # Number of ticks simulated -final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.332812 # Number of seconds simulated +sim_ticks 2332811899500 # Number of ticks simulated +final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1221068 # Simulator instruction rate (inst/s) -host_op_rate 1570218 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47154151043 # Simulator tick rate (ticks/s) -host_mem_usage 421264 # Number of bytes of host memory used -host_seconds 49.47 # Real time elapsed on the host -sim_insts 60408649 # Number of instructions simulated -sim_ops 77681829 # Number of ops (including micro ops) simulated +host_inst_rate 1003640 # Simulator instruction rate (inst/s) +host_op_rate 1290613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38755909714 # Simulator tick rate (ticks/s) +host_mem_usage 421296 # Number of bytes of host memory used +host_seconds 60.19 # Real time elapsed on the host +sim_insts 60411489 # Number of instructions simulated +sim_ops 77685090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 492744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6494808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 212416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2577132 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 492744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 212416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu0.inst 492808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6490328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 212352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2581740 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450892 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 492808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 212352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1405784 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1610060 # Number of bytes written to this memory -system.physmem.bytes_written::total 6718884 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1405780 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1610064 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719076 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 101517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3319 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 40278 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118198 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 351446 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 402515 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811821 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 13912 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 101447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3318 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 40350 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118200 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 351445 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 402516 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811824 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 211223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2784113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 91056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1104733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 211223 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 91056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 211251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2782191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 91028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1106707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52062017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 211251 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 91028 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587373 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 602614 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 690180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 602612 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 690182 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2880248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 211223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3386727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 211251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3384803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 91028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1796889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942264 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -76,31 +76,31 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969581 # Throughput (bytes/s) -system.membus.data_through_bus 130566414 # Total data (bytes) +system.membus.throughput 55969745 # Throughput (bytes/s) +system.membus.data_through_bus 130566887 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62242 # number of replacements -system.l2c.tags.tagsinuse 50006.300115 # Cycle average of tags in use -system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36900.571374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor +system.l2c.tags.replacements 62244 # number of replacements +system.l2c.tags.tagsinuse 50006.487761 # Cycle average of tags in use +system.l2c.tags.total_refs 1678458 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127629 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.151071 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.766383 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993822 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4917.298409 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3152.525305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2097.421521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2936.495752 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4918.263908 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3149.549186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2096.452041 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2939.468488 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563061 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075047 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.031989 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044853 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.763038 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id @@ -111,132 +111,132 @@ system.l2c.tags.age_task_id_blocks_1024::3 9187 # system.l2c.tags.age_task_id_blocks_1024::4 52391 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17104735 # Number of tag accesses -system.l2c.tags.data_accesses 17104735 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 473132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 196968 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4875 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 365739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169796 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1224842 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 592682 # number of Writeback hits -system.l2c.Writeback_hits::total 592682 # number of Writeback hits +system.l2c.tags.tag_accesses 17104555 # Number of tag accesses +system.l2c.tags.data_accesses 17104555 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3279 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 473060 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 196973 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4855 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2031 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 365811 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 169795 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1224812 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 592687 # number of Writeback hits +system.l2c.Writeback_hits::total 592687 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63334 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50404 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 63344 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 50394 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 113738 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9005 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3277 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 473132 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 260302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4875 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 365739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 220200 # number of demand (read+write) hits -system.l2c.demand_hits::total 1338580 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9005 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3277 # number of overall hits -system.l2c.overall_hits::cpu0.inst 473132 # number of overall hits -system.l2c.overall_hits::cpu0.data 260302 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4875 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2050 # number of overall hits -system.l2c.overall_hits::cpu1.inst 365739 # number of overall hits -system.l2c.overall_hits::cpu1.data 220200 # number of overall hits -system.l2c.overall_hits::total 1338580 # number of overall hits +system.l2c.demand_hits::cpu0.dtb.walker 9008 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3279 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 473060 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 260317 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4855 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2031 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 365811 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 220189 # number of demand (read+write) hits +system.l2c.demand_hits::total 1338550 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9008 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3279 # number of overall hits +system.l2c.overall_hits::cpu0.inst 473060 # number of overall hits +system.l2c.overall_hits::cpu0.data 260317 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4855 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2031 # number of overall hits +system.l2c.overall_hits::cpu1.inst 365811 # number of overall hits +system.l2c.overall_hits::cpu1.data 220189 # number of overall hits +system.l2c.overall_hits::total 1338550 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5807 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3319 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4065 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7286 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5804 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3318 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4068 # number of ReadReq misses system.l2c.ReadReq_misses::total 20481 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1520 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1399 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1525 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1394 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 96488 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 36984 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133472 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 96422 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 37052 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133474 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7285 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 102295 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3319 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 41049 # number of demand (read+write) misses -system.l2c.demand_misses::total 153953 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7286 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 102226 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3318 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 41120 # number of demand (read+write) misses +system.l2c.demand_misses::total 153955 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7285 # number of overall misses -system.l2c.overall_misses::cpu0.data 102295 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3319 # number of overall misses -system.l2c.overall_misses::cpu1.data 41049 # number of overall misses -system.l2c.overall_misses::total 153953 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9007 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3280 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 480417 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 202775 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4875 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2050 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 369058 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 173861 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1245323 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 592682 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 592682 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1532 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 7286 # number of overall misses +system.l2c.overall_misses::cpu0.data 102226 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3318 # number of overall misses +system.l2c.overall_misses::cpu1.data 41120 # number of overall misses +system.l2c.overall_misses::total 153955 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9010 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3282 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 480346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 202777 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4855 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 369129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 173863 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1245293 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 592687 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 592687 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1537 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1408 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 159822 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 87388 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247210 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9007 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3280 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 480417 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 362597 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4875 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2050 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 369058 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 261249 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492533 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9007 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3280 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 480417 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 362597 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4875 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2050 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 369058 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 261249 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492533 # number of overall (read+write) accesses +system.l2c.ReadExReq_accesses::cpu0.data 159766 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 87446 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247212 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9010 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3282 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 480346 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 362543 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4855 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2031 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 369129 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 261309 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492505 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9010 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3282 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 480346 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 362543 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4855 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2031 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 369129 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 261309 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492505 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000915 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015164 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028638 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008993 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023381 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992167 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990092 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000914 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015168 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028623 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008989 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.023398 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016447 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992193 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990057 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.603722 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.423216 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539913 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.603520 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.423713 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539917 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000915 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015164 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.282118 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008993 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.157126 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.103149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000914 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015168 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008989 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.157362 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103152 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000915 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015164 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.282118 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008993 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.157126 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.103149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000914 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015168 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008989 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.157362 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103152 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -245,8 +245,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57860 # number of writebacks -system.l2c.writebacks::total 57860 # number of writebacks +system.l2c.writebacks::writebacks 57863 # number of writebacks +system.l2c.writebacks::total 57863 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -254,11 +254,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59119271 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 137914042 # Total data (bytes) +system.toL2Bus.throughput 59119535 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 137914755 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 48895252 # Throughput (bytes/s) -system.iobus.data_through_bus 114063346 # Total data (bytes) +system.iobus.throughput 48895283 # Throughput (bytes/s) +system.iobus.data_through_bus 114063499 # Total data (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -282,25 +282,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7929199 # DTB read hits -system.cpu0.dtb.read_misses 6444 # DTB read misses -system.cpu0.dtb.write_hits 6437089 # DTB write hits +system.cpu0.dtb.read_hits 7929658 # DTB read hits +system.cpu0.dtb.read_misses 6455 # DTB read misses +system.cpu0.dtb.write_hits 6435419 # DTB write hits system.cpu0.dtb.write_misses 1929 # DTB write misses system.cpu0.dtb.flush_tlb 2334 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5568 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5575 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7935643 # DTB read accesses -system.cpu0.dtb.write_accesses 6439018 # DTB write accesses +system.cpu0.dtb.read_accesses 7936113 # DTB read accesses +system.cpu0.dtb.write_accesses 6437348 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14366288 # DTB hits -system.cpu0.dtb.misses 8373 # DTB misses -system.cpu0.dtb.accesses 14374661 # DTB accesses +system.cpu0.dtb.hits 14365077 # DTB hits +system.cpu0.dtb.misses 8384 # DTB misses +system.cpu0.dtb.accesses 14373461 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -322,62 +322,62 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32543256 # ITB inst hits -system.cpu0.itb.inst_misses 3703 # ITB inst misses +system.cpu0.itb.inst_hits 32541992 # ITB inst hits +system.cpu0.itb.inst_misses 3717 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2334 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2663 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2674 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32546959 # ITB inst accesses -system.cpu0.itb.hits 32543256 # DTB hits -system.cpu0.itb.misses 3703 # DTB misses -system.cpu0.itb.accesses 32546959 # DTB accesses -system.cpu0.numCycles 4633654699 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32545709 # ITB inst accesses +system.cpu0.itb.hits 32541992 # DTB hits +system.cpu0.itb.misses 3717 # DTB misses +system.cpu0.itb.accesses 32545709 # DTB accesses +system.cpu0.numCycles 4625561989 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31998107 # Number of instructions committed -system.cpu0.committedOps 41901559 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37244533 # Number of integer alu accesses +system.cpu0.committedInsts 31996828 # Number of instructions committed +system.cpu0.committedOps 41898003 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37241416 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5364 # Number of float alu accesses -system.cpu0.num_func_calls 1207172 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4285554 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37244533 # number of integer instructions +system.cpu0.num_func_calls 1207166 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4285035 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37241416 # number of integer instructions system.cpu0.num_fp_insts 5364 # number of float instructions -system.cpu0.num_int_register_reads 192529528 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39716026 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192512823 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39713188 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3938 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu0.num_mem_refs 15013044 # number of memory refs -system.cpu0.num_load_insts 8304661 # Number of load instructions -system.cpu0.num_store_insts 6708383 # Number of store instructions -system.cpu0.num_idle_cycles 4553702806.473283 # Number of idle cycles -system.cpu0.num_busy_cycles 79951892.526717 # Number of busy cycles -system.cpu0.not_idle_fraction 0.017255 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.982745 # Percentage of idle cycles -system.cpu0.Branches 5613939 # Number of branches fetched +system.cpu0.num_mem_refs 15011832 # number of memory refs +system.cpu0.num_load_insts 8305325 # Number of load instructions +system.cpu0.num_store_insts 6706507 # Number of store instructions +system.cpu0.num_idle_cycles 4549718927.235470 # Number of idle cycles +system.cpu0.num_busy_cycles 75843061.764530 # Number of busy cycles +system.cpu0.not_idle_fraction 0.016397 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.983603 # Percentage of idle cycles +system.cpu0.Branches 5613326 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 850590 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60586338 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.509134 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.169458 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868182 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131190 # Average percentage of cache occupancy +system.cpu0.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.500524 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.177938 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868165 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131207 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id @@ -385,44 +385,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 78 system.cpu0.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62285702 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62285702 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32064740 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 28518758 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32064740 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 28518758 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60583498 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32064740 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 28518758 # number of overall hits -system.cpu0.icache.overall_hits::total 60583498 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 481295 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 369807 # number of ReadReq misses +system.cpu0.icache.tags.tag_accesses 62288542 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62288542 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 32063555 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 28522783 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60586338 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32063555 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 28522783 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60586338 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32063555 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 28522783 # number of overall hits +system.cpu0.icache.overall_hits::total 60586338 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 481227 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 369875 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 851102 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 481295 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 369807 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 481227 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 369875 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 851102 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 481295 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 369807 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 481227 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 369875 # number of overall misses system.cpu0.icache.overall_misses::total 851102 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32546035 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 28888565 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32546035 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 28888565 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32546035 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 28888565 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014788 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012801 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014788 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012801 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014788 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012801 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32544782 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 28892658 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32544782 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 28892658 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32544782 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 28892658 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014787 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012802 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014787 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012802 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014787 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012802 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,90 +432,90 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 623334 # number of replacements +system.cpu0.dcache.tags.replacements 623340 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23628286 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.875190 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 23628946 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623852 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.875884 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298836 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698194 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.291431 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.705599 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881429 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118566 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97632374 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97632374 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6995580 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6184442 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13180022 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5776847 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4185218 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9962065 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139292 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96744 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 97635044 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97635044 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6996051 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6184470 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13180521 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5775160 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4187066 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9962226 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139339 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96697 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 236036 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145938 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101280 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145986 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101232 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247218 # 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number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12771211 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10371536 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23142747 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12771211 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10371536 # number of overall hits +system.cpu0.dcache.overall_hits::total 23142747 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 196129 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 169328 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 365457 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 161303 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 88854 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250157 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5938201 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4274019 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10212220 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145939 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101280 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 357432 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 258182 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 615614 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 357432 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 258182 # number of overall misses +system.cpu0.dcache.overall_misses::total 615614 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7192180 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353798 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13545978 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5936463 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4275920 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10212383 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145987 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101232 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247219 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145938 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101280 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145986 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101232 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247218 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13129909 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 10627786 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23757695 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13129909 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10627786 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23757695 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027271 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 13128643 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 10629718 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23758361 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13128643 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10629718 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23758361 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027270 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026650 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020777 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024496 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045546 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044787 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020780 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045538 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044798 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027227 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024288 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027227 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024288 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027225 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024289 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025911 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027225 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024289 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.025911 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,8 +524,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 592682 # number of writebacks -system.cpu0.dcache.writebacks::total 592682 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 592687 # number of writebacks +system.cpu0.dcache.writebacks::total 592687 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -550,25 +550,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7038606 # DTB read hits -system.cpu1.dtb.read_misses 4220 # DTB read misses -system.cpu1.dtb.write_hits 4778915 # DTB write hits -system.cpu1.dtb.write_misses 1252 # DTB write misses +system.cpu1.dtb.read_hits 7038699 # DTB read hits +system.cpu1.dtb.read_misses 4194 # DTB read misses +system.cpu1.dtb.write_hits 4780763 # DTB write hits +system.cpu1.dtb.write_misses 1254 # DTB write misses system.cpu1.dtb.flush_tlb 2332 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2946 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2928 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 80 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7042826 # DTB read accesses -system.cpu1.dtb.write_accesses 4780167 # DTB write accesses +system.cpu1.dtb.read_accesses 7042893 # DTB read accesses +system.cpu1.dtb.write_accesses 4782017 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 11817521 # DTB hits -system.cpu1.dtb.misses 5472 # DTB misses -system.cpu1.dtb.accesses 11822993 # DTB accesses +system.cpu1.dtb.hits 11819462 # DTB hits +system.cpu1.dtb.misses 5448 # DTB misses +system.cpu1.dtb.accesses 11824910 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -590,50 +590,50 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 28886889 # ITB inst hits -system.cpu1.itb.inst_misses 2463 # ITB inst misses +system.cpu1.itb.inst_hits 28890998 # ITB inst hits +system.cpu1.itb.inst_misses 2444 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2332 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1658 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1642 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28889352 # ITB inst accesses -system.cpu1.itb.hits 28886889 # DTB hits -system.cpu1.itb.misses 2463 # DTB misses -system.cpu1.itb.accesses 28889352 # DTB accesses -system.cpu1.numCycles 4277971820 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 28893442 # ITB inst accesses +system.cpu1.itb.hits 28890998 # DTB hits +system.cpu1.itb.misses 2444 # DTB misses +system.cpu1.itb.accesses 28893442 # DTB accesses +system.cpu1.numCycles 4282034895 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 28410542 # Number of instructions committed -system.cpu1.committedOps 35780270 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 31886228 # Number of integer alu accesses +system.cpu1.committedInsts 28414661 # Number of instructions committed +system.cpu1.committedOps 35787087 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 31892138 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 4905 # Number of float alu accesses -system.cpu1.num_func_calls 928836 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3656561 # number of instructions that are conditional controls -system.cpu1.num_int_insts 31886228 # number of integer instructions +system.cpu1.num_func_calls 928912 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3657531 # number of instructions that are conditional controls +system.cpu1.num_int_insts 31892138 # number of integer instructions system.cpu1.num_fp_insts 4905 # number of float instructions -system.cpu1.num_int_register_reads 163367229 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34722740 # number of times the integer registers were written +system.cpu1.num_int_register_reads 163397724 # number of times the integer registers were read +system.cpu1.num_int_register_writes 34729085 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3555 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1352 # number of times the floating registers were written -system.cpu1.num_mem_refs 12348595 # number of memory refs -system.cpu1.num_load_insts 7334868 # Number of load instructions -system.cpu1.num_store_insts 5013727 # Number of store instructions -system.cpu1.num_idle_cycles 4215699127.014197 # Number of idle cycles -system.cpu1.num_busy_cycles 62272692.985803 # Number of busy cycles -system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles -system.cpu1.Branches 4684784 # Number of branches fetched +system.cpu1.num_mem_refs 12350589 # number of memory refs +system.cpu1.num_load_insts 7334763 # Number of load instructions +system.cpu1.num_store_insts 5015826 # Number of store instructions +system.cpu1.num_idle_cycles 4212351630.069436 # Number of idle cycles +system.cpu1.num_busy_cycles 69683264.930565 # Number of busy cycles +system.cpu1.not_idle_fraction 0.016273 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.983727 # Percentage of idle cycles +system.cpu1.Branches 4685935 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements |