diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/quick/fs | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/quick/fs')
5 files changed, 4767 insertions, 5742 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 14efebcaa..85845c2fe 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.960910 # Number of seconds simulated -sim_ticks 1960909874500 # Number of ticks simulated -final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961814 # Number of seconds simulated +sim_ticks 1961813569500 # Number of ticks simulated +final_tick 1961813569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1305982 # Simulator instruction rate (inst/s) -host_op_rate 1305981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42027651646 # Simulator tick rate (ticks/s) -host_mem_usage 309852 # Number of bytes of host memory used -host_seconds 46.66 # Real time elapsed on the host -sim_insts 60933947 # Number of instructions simulated -sim_ops 60933947 # Number of ops (including micro ops) simulated +host_inst_rate 1769979 # Simulator instruction rate (inst/s) +host_op_rate 1769979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57024152249 # Simulator tick rate (ticks/s) +host_mem_usage 311592 # Number of bytes of host memory used +host_seconds 34.40 # Real time elapsed on the host +sim_insts 60892925 # Number of instructions simulated +sim_ops 60892925 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 338304 # Number of bytes read from this memory -system.physmem.bytes_read::total 28741248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7743680 # Number of bytes written to this memory -system.physmem.bytes_written::total 7743680 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5286 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449082 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120995 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120995 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12691610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 172524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14657098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16156 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3949024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3949024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3949024 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12691610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 172524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18606122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449082 # Number of read requests accepted -system.physmem.writeReqs 120995 # Number of write requests accepted -system.physmem.readBursts 449082 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120995 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28737664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue -system.physmem.bytesWritten 7742592 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28741248 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7743680 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 833088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24884096 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 337152 # Number of bytes read from this memory +system.physmem.bytes_read::total 28737152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7735232 # Number of bytes written to this memory +system.physmem.bytes_written::total 7735232 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388814 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5268 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449018 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120863 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120863 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12684231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 171857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14648258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424652 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3942899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3942899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3942899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12684231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 171857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449018 # Number of read requests accepted +system.physmem.writeReqs 120863 # Number of write requests accepted +system.physmem.readBursts 449018 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120863 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28729600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 7733952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28737152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7735232 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7094 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28167 # Per bank write bursts -system.physmem.perBankRdBursts::1 28459 # Per bank write bursts -system.physmem.perBankRdBursts::2 28057 # Per bank write bursts -system.physmem.perBankRdBursts::3 27664 # Per bank write bursts -system.physmem.perBankRdBursts::4 27762 # Per bank write bursts -system.physmem.perBankRdBursts::5 27793 # Per bank write bursts -system.physmem.perBankRdBursts::6 28259 # Per bank write bursts -system.physmem.perBankRdBursts::7 27872 # Per bank write bursts -system.physmem.perBankRdBursts::8 28083 # Per bank write bursts -system.physmem.perBankRdBursts::9 27730 # Per bank write bursts -system.physmem.perBankRdBursts::10 27672 # Per bank write bursts -system.physmem.perBankRdBursts::11 28135 # Per bank write bursts -system.physmem.perBankRdBursts::12 28179 # Per bank write bursts -system.physmem.perBankRdBursts::13 28505 # Per bank write bursts -system.physmem.perBankRdBursts::14 28654 # Per bank write bursts -system.physmem.perBankRdBursts::15 28035 # Per bank write bursts -system.physmem.perBankWrBursts::0 7928 # Per bank write bursts -system.physmem.perBankWrBursts::1 7868 # Per bank write bursts -system.physmem.perBankWrBursts::2 7543 # Per bank write bursts -system.physmem.perBankWrBursts::3 7157 # Per bank write bursts -system.physmem.perBankWrBursts::4 7275 # Per bank write bursts -system.physmem.perBankWrBursts::5 7314 # Per bank write bursts -system.physmem.perBankWrBursts::6 7747 # Per bank write bursts -system.physmem.perBankWrBursts::7 7251 # Per bank write bursts -system.physmem.perBankWrBursts::8 7322 # Per bank write bursts -system.physmem.perBankWrBursts::9 7110 # Per bank write bursts -system.physmem.perBankWrBursts::10 7099 # Per bank write bursts -system.physmem.perBankWrBursts::11 7523 # Per bank write bursts -system.physmem.perBankWrBursts::12 7681 # Per bank write bursts -system.physmem.perBankWrBursts::13 8141 # Per bank write bursts -system.physmem.perBankWrBursts::14 8335 # Per bank write bursts -system.physmem.perBankWrBursts::15 7684 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6983 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28166 # Per bank write bursts +system.physmem.perBankRdBursts::1 28350 # Per bank write bursts +system.physmem.perBankRdBursts::2 28054 # Per bank write bursts +system.physmem.perBankRdBursts::3 27500 # Per bank write bursts +system.physmem.perBankRdBursts::4 27615 # Per bank write bursts +system.physmem.perBankRdBursts::5 27605 # Per bank write bursts +system.physmem.perBankRdBursts::6 28127 # Per bank write bursts +system.physmem.perBankRdBursts::7 27851 # Per bank write bursts +system.physmem.perBankRdBursts::8 28176 # Per bank write bursts +system.physmem.perBankRdBursts::9 27723 # Per bank write bursts +system.physmem.perBankRdBursts::10 27750 # Per bank write bursts +system.physmem.perBankRdBursts::11 28018 # Per bank write bursts +system.physmem.perBankRdBursts::12 28330 # Per bank write bursts +system.physmem.perBankRdBursts::13 28694 # Per bank write bursts +system.physmem.perBankRdBursts::14 28891 # Per bank write bursts +system.physmem.perBankRdBursts::15 28050 # Per bank write bursts +system.physmem.perBankWrBursts::0 7929 # Per bank write bursts +system.physmem.perBankWrBursts::1 7797 # Per bank write bursts +system.physmem.perBankWrBursts::2 7545 # Per bank write bursts +system.physmem.perBankWrBursts::3 7029 # Per bank write bursts +system.physmem.perBankWrBursts::4 7135 # Per bank write bursts +system.physmem.perBankWrBursts::5 7129 # Per bank write bursts +system.physmem.perBankWrBursts::6 7643 # Per bank write bursts +system.physmem.perBankWrBursts::7 7252 # Per bank write bursts +system.physmem.perBankWrBursts::8 7395 # Per bank write bursts +system.physmem.perBankWrBursts::9 7084 # Per bank write bursts +system.physmem.perBankWrBursts::10 7104 # Per bank write bursts +system.physmem.perBankWrBursts::11 7401 # Per bank write bursts +system.physmem.perBankWrBursts::12 7833 # Per bank write bursts +system.physmem.perBankWrBursts::13 8315 # Per bank write bursts +system.physmem.perBankWrBursts::14 8551 # Per bank write bursts +system.physmem.perBankWrBursts::15 7701 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1960902862500 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1961806557500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 449082 # Read request sizes (log2) +system.physmem.readPktSize::6 449018 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120995 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 409890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120863 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -143,456 +143,370 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49380 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 738.726934 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 222.746795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1735.319745 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 17723 35.89% 35.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7354 14.89% 50.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4892 9.91% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2955 5.98% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1860 3.77% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1462 2.96% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1143 2.31% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 851 1.72% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 746 1.51% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 676 1.37% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 661 1.34% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 443 0.90% 82.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 337 0.68% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 276 0.56% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 300 0.61% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 399 0.81% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 192 0.39% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 178 0.36% 85.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 196 0.40% 86.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 170 0.34% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 202 0.41% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 873 1.77% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 184 0.37% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 168 0.34% 89.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 96 0.19% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 82 0.17% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 107 0.22% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 72 0.15% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 81 0.16% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 51 0.10% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 64 0.13% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 84 0.17% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 51 0.10% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 54 0.11% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 70 0.14% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 45 0.09% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 72 0.15% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 49 0.10% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 40 0.08% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 72 0.15% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 42 0.09% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 45 0.09% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 69 0.14% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 44 0.09% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 64 0.13% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 43 0.09% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 76 0.15% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 39 0.08% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 46 0.09% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 67 0.14% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 46 0.09% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 66 0.13% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 46 0.09% 93.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 37 0.07% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 72 0.15% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 38 0.08% 93.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 42 0.09% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 69 0.14% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 43 0.09% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 64 0.13% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 42 0.09% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 41 0.08% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 74 0.15% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 37 0.07% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 43 0.09% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 66 0.13% 94.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 46 0.09% 94.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 64 0.13% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 43 0.09% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 37 0.07% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 404 0.82% 95.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 34 0.07% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 44 0.09% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 36 0.07% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 44 0.09% 96.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 34 0.07% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 44 0.09% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 33 0.07% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 41 0.08% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 51 0.10% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 44 0.09% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 32 0.06% 96.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 40 0.08% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 37 0.07% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 43 0.09% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 35 0.07% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 40 0.08% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 33 0.07% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 47 0.10% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 34 0.07% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 43 0.09% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 35 0.07% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 44 0.09% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 34 0.07% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 44 0.09% 97.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 38 0.08% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 42 0.09% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 35 0.07% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 43 0.09% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 32 0.06% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 40 0.08% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 37 0.07% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 41 0.08% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 32 0.06% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 431 0.87% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 10 0.02% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 3 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 36 0.07% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 180 0.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49380 # Bytes accessed per row activation -system.physmem.totQLat 6346588750 # Total ticks spent queuing -system.physmem.totMemAccLat 14721193750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2245130000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6129475000 # Total ticks spent accessing banks -system.physmem.avgQLat 14134.12 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13650.60 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 48187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 641.951066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 418.430190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 422.843508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8213 17.04% 17.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7073 14.68% 31.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2891 6.00% 37.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1720 3.57% 41.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1328 2.76% 44.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 906 1.88% 45.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 669 1.39% 47.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 536 1.11% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24851 51.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48187 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6896 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 65.095418 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2542.617511 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6893 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6896 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6896 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.523637 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.253710 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.981541 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4466 64.76% 64.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 342 4.96% 69.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 377 5.47% 75.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1323 19.19% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 32 0.46% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.23% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 12 0.17% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.32% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 43 0.62% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 30 0.44% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 27 0.39% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 32 0.46% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 29 0.42% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 31 0.45% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 6 0.09% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 8 0.12% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 10 0.15% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.04% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 4 0.06% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 4 0.06% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 3 0.04% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 5 0.07% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.04% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 3 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 3 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 6 0.09% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 12 0.17% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 5 0.07% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 7 0.10% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 3 0.04% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 5 0.07% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 6 0.09% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6896 # Writes before turning the bus around for reads +system.physmem.totQLat 7845433250 # Total ticks spent queuing +system.physmem.totMemAccLat 16453873250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2244500000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6363940000 # Total ticks spent accessing banks +system.physmem.avgQLat 17477.02 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14176.74 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32784.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 36653.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.65 # Average write queue length when enqueuing -system.physmem.readRowHits 424775 # Number of row buffer hits during reads -system.physmem.writeRowHits 95849 # Number of row buffer hits during writes -system.physmem.readRowHitRate 94.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.22 # Row buffer hit rate for writes -system.physmem.avgGap 3439715.80 # Average gap between requests -system.physmem.pageHitRate 91.33 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18666756 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292805 # Transaction distribution -system.membus.trans_dist::ReadResp 292805 # Transaction distribution -system.membus.trans_dist::WriteReq 14109 # Transaction distribution -system.membus.trans_dist::WriteResp 14109 # Transaction distribution -system.membus.trans_dist::Writeback 120995 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16488 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11559 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7097 # Transaction distribution -system.membus.trans_dist::ReadExReq 164894 # Transaction distribution -system.membus.trans_dist::ReadExResp 164048 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931055 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 973671 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124663 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124663 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1098334 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82290 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31259250 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5307968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36567218 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36567218 # Total data (bytes) -system.membus.snoop_data_through_bus 36608 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 43251000 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.52 # Average write queue length when enqueuing +system.physmem.readRowHits 403422 # Number of row buffer hits during reads +system.physmem.writeRowHits 97436 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.62 # Row buffer hit rate for writes +system.physmem.avgGap 3442484.58 # Average gap between requests +system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.55 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18651494 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292756 # Transaction distribution +system.membus.trans_dist::ReadResp 292756 # Transaction distribution +system.membus.trans_dist::WriteReq 14067 # Transaction distribution +system.membus.trans_dist::WriteResp 14067 # Transaction distribution +system.membus.trans_dist::Writeback 120863 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16150 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11271 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6986 # Transaction distribution +system.membus.trans_dist::ReadExReq 164854 # Transaction distribution +system.membus.trans_dist::ReadExResp 164030 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 972562 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1097228 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31164224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31246178 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36554338 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36554338 # Total data (bytes) +system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43154000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1579578000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1578633000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3830990646 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3834132000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376702000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342160 # number of replacements -system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use -system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407347 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.997899 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8615385750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55312.026017 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4807.093964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4897.564051 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 159.017352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.243921 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843995 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073350 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy +system.l2c.tags.replacements 342098 # number of replacements +system.l2c.tags.tagsinuse 65220.106735 # Cycle average of tags in use +system.l2c.tags.total_refs 2445213 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407285 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.003690 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8658635750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55273.758884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4807.212496 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4935.163888 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 160.761256 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 43.210211 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.843411 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075305 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002453 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995180 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 761 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5186 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7242 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51881 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 784 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5254 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7171 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51861 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25932224 # Number of tag accesses -system.l2c.tags.data_accesses 25932224 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 107430 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774057 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 791641 # number of Writeback hits -system.l2c.Writeback_hits::total 791641 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 180 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 539 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 719 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 129054 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 42974 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172028 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 684719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 793579 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 317383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 150404 # number of demand (read+write) hits -system.l2c.demand_hits::total 1946085 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 684719 # number of overall hits -system.l2c.overall_hits::cpu0.data 793579 # number of overall hits -system.l2c.overall_hits::cpu1.inst 317383 # number of overall hits -system.l2c.overall_hits::cpu1.data 150404 # number of overall hits -system.l2c.overall_hits::total 1946085 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13026 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271672 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 503 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 242 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285443 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1793 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4742 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 919 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 927 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1846 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117950 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5055 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123005 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13026 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389622 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 503 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 5297 # number of demand (read+write) misses -system.l2c.demand_misses::total 408448 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13026 # number of overall misses -system.l2c.overall_misses::cpu0.data 389622 # number of overall misses -system.l2c.overall_misses::cpu1.inst 503 # number of overall misses -system.l2c.overall_misses::cpu1.data 5297 # number of overall misses -system.l2c.overall_misses::total 408448 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 997409492 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17552881248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 35450000 # 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number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 529 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 713 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 64 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 130516 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 42247 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172763 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 690864 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 798814 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 311515 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 146457 # number of demand (read+write) hits +system.l2c.demand_hits::total 1947650 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55884.310050 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59621.283419 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56037.522980 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -728,14 +642,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.570482 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.569649 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754531382000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.570482 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035655 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035655 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1755503918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569649 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035603 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035603 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -749,14 +663,14 @@ system.iocache.demand_misses::tsunami.ide 41726 # n system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21249133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21249133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12966402814 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12966402814 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12987651947 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12987651947 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12987651947 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12987651947 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21248883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21248883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13129991411 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13129991411 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13151240294 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13151240294 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13151240294 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13151240294 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -773,19 +687,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122121.454023 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122121.454023 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312052.435839 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312052.435839 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311260.411901 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311260.411901 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 401197 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122120.017241 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122120.017241 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 315989.396684 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 315989.396684 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 315180.949384 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 315180.949384 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 388544 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28980 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28481 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.843927 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.642218 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -799,14 +713,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41726 system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12200133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12200133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10804136814 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10804136814 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10816336947 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10816336947 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10816336947 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10816336947 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12199883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10966952411 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10966952411 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10979152294 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10979152294 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10979152294 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10979152294 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -815,14 +729,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70114.270115 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70114.270115 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 263933.202036 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 263933.202036 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -840,22 +754,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7532654 # DTB read hits -system.cpu0.dtb.read_misses 7812 # DTB read misses +system.cpu0.dtb.read_hits 7562587 # DTB read hits +system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524694 # DTB read accesses -system.cpu0.dtb.write_hits 5120278 # DTB write hits -system.cpu0.dtb.write_misses 919 # DTB write misses -system.cpu0.dtb.write_acv 139 # DTB write access violations -system.cpu0.dtb.write_accesses 202960 # DTB write accesses -system.cpu0.dtb.data_hits 12652932 # DTB hits -system.cpu0.dtb.data_misses 8731 # DTB misses -system.cpu0.dtb.data_acv 349 # DTB access violations -system.cpu0.dtb.data_accesses 727654 # DTB accesses -system.cpu0.itb.fetch_hits 3655515 # ITB hits -system.cpu0.itb.fetch_misses 4023 # ITB misses +system.cpu0.dtb.read_accesses 524069 # DTB read accesses +system.cpu0.dtb.write_hits 5147352 # DTB write hits +system.cpu0.dtb.write_misses 910 # DTB write misses +system.cpu0.dtb.write_acv 133 # DTB write access violations +system.cpu0.dtb.write_accesses 202595 # DTB write accesses +system.cpu0.dtb.data_hits 12709939 # DTB hits +system.cpu0.dtb.data_misses 8675 # DTB misses +system.cpu0.dtb.data_acv 343 # DTB access violations +system.cpu0.dtb.data_accesses 726664 # DTB accesses +system.cpu0.itb.fetch_hits 3660806 # ITB hits +system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3659538 # ITB accesses +system.cpu0.itb.fetch_accesses 3664790 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -868,56 +782,56 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3921819749 # number of cpu cycles simulated +system.cpu0.numCycles 3923627139 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47983654 # Number of instructions committed -system.cpu0.committedOps 47983654 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44515044 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211401 # Number of float alu accesses -system.cpu0.num_func_calls 1203620 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5635723 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44515044 # number of integer instructions -system.cpu0.num_fp_insts 211401 # number of float instructions -system.cpu0.num_int_register_reads 61226145 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33154260 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 103282 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 105080 # number of times the floating registers were written -system.cpu0.num_mem_refs 12694028 # number of memory refs -system.cpu0.num_load_insts 7560495 # Number of load instructions -system.cpu0.num_store_insts 5133533 # Number of store instructions -system.cpu0.num_idle_cycles 3698209766.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223609982.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057017 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942983 # Percentage of idle cycles -system.cpu0.Branches 7227606 # Number of branches fetched +system.cpu0.committedInsts 48127942 # Number of instructions committed +system.cpu0.committedOps 48127942 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44644072 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 213646 # Number of float alu accesses +system.cpu0.num_func_calls 1209779 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5646914 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44644072 # number of integer instructions +system.cpu0.num_fp_insts 213646 # number of float instructions +system.cpu0.num_int_register_reads 61387929 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33243119 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 104403 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 106204 # number of times the floating registers were written +system.cpu0.num_mem_refs 12751056 # number of memory refs +system.cpu0.num_load_insts 7590434 # Number of load instructions +system.cpu0.num_store_insts 5160622 # Number of store instructions +system.cpu0.num_idle_cycles 3699531471.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 224095667.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057114 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942886 # Percentage of idle cycles +system.cpu0.Branches 7246727 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165343 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56789 40.24% 40.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.40% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 42.04% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81806 57.96% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141134 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56279 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 166332 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 57240 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.39% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82451 57.97% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 142220 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56707 49.09% 49.09% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55844 48.70% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114662 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1901501471500 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95150500 0.00% 96.98% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767153500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 322241000 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58223100500 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1960909117000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991019 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1974 1.71% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1902164041000 96.96% 96.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95225000 0.00% 96.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 767277500 0.04% 97.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314374500 0.02% 97.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58471894000 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961812812000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682639 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812434 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682624 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812256 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -949,37 +863,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3090 2.07% 2.42% # number of callpals executed -system.cpu0.kern.callpal::tbi 52 0.03% 2.45% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134176 89.74% 92.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6700 4.48% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rti 4418 2.95% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 396 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3107 2.06% 2.40% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed +system.cpu0.kern.callpal::swpipl 135267 89.81% 92.25% # number of callpals executed +system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149515 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7023 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1378 # number of protection mode switches +system.cpu0.kern.callpal::total 150615 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7022 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1377 -system.cpu0.kern.mode_good::user 1378 +system.cpu0.kern.mode_good::kernel 1371 +system.cpu0.kern.mode_good::user 1372 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.196070 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195244 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327937 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1957102433500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3806679000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.326781 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958041026500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3771781000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3091 # number of times the context was actually changed +system.cpu0.kern.swap_context 3108 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1011,47 +925,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 103937669 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2101927 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2101912 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14109 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14109 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 791641 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16698 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11618 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28316 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 338479 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296929 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1395511 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 635773 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 463473 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5616114 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44655680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119473096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20344704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16974250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 201447730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 201437426 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2374976 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4790041400 # Layer occupancy (ticks) +system.toL2Bus.throughput 103965077 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2102306 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102291 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 792911 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16363 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11335 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27698 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 339143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297593 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134857 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5619111 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45048576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120057312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19969408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16548674 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 201623970 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201613666 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2346432 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4795947858 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3142512505 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3170057255 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5519878863 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5536383084 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1430590492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1404201241 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 794307231 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 776393157 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1399302 # Throughput (bytes/s) +system.iobus.throughput 1398487 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55661 # Transaction distribution -system.iobus.trans_dist::WriteResp 55661 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14006 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 55619 # Transaction distribution +system.iobus.trans_dist::WriteResp 55619 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1063,11 +977,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126068 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1079,12 +993,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 82290 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2743906 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2743906 # Total data (bytes) -system.iobus.reqLayer0.occupancy 13361000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2743570 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1106,67 +1020,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377744447 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380082294 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28507000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42681500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43185000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 697136 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.398756 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47294969 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 697648 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.792023 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40091069250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 703274 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.380970 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47433057 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 703786 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.396989 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40278267250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.380970 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992932 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992932 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48690501 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48690501 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47294969 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47294969 # number of overall hits -system.cpu0.icache.overall_hits::total 47294969 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 697766 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 697766 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 697766 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 697766 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 697766 # number of overall misses -system.cpu0.icache.overall_misses::total 697766 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9984385005 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9984385005 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9984385005 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9984385005 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9984385005 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9984385005 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47992735 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47992735 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47992735 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47992735 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47992735 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47992735 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014539 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014539 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014539 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014539 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014539 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014539 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14309.073536 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14309.073536 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48840865 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48840865 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1186229 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.271614 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11460994 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1186741 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.657536 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 107902250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.271614 # 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Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51851796 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51851796 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6451735 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6451735 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4706856 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4706856 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140512 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140512 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148003 # 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number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420082 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7420082 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989599 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4989599 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155267 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 155267 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154715 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 154715 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12409681 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12409681 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12409681 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12409681 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127046 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127046 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051712 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051712 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088345 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088345 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035239 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035239 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096756 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096756 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096756 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096756 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28917.196894 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28917.196894 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39851.835252 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39851.835252 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11000.328060 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11000.328060 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7701.648569 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7701.648569 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31266.962765 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31266.962765 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1296,66 +1210,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682519 # number of writebacks -system.cpu0.dcache.writebacks::total 682519 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939483 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939483 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256736 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 256736 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13633 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13633 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5600 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5600 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1196219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196219 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1196219 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25065202500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25065202500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9891526306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9891526306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121052250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121052250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32145581 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32145581 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34956728806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 34956728806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34956728806 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 34956728806 # number of overall MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 686471 # number of writebacks +system.cpu0.dcache.writebacks::total 686471 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942691 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942691 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258024 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 258024 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13717 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13717 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200715 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1200715 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200715 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1200715 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25249299743 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25249299743 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9714288061 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9714288061 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 123443500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 123443500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31083612 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31083612 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34963587804 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34963587804 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34963587804 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34963587804 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284723500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284723500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750325500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750325500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127108 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127108 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088443 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088443 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036458 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036458 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096822 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096822 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8879.355241 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8879.355241 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5740.282321 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5740.282321 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2280051500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2280051500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3745653500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3745653500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051712 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051712 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088345 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088345 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035239 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035239 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096756 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096756 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26784.280048 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26784.280048 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37648.777094 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37648.777094 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8999.307429 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8999.307429 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5701.322817 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5701.322817 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1367,22 +1277,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2383442 # DTB read hits +system.cpu1.dtb.read_hits 2348422 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1706844 # DTB write hits +system.cpu1.dtb.write_hits 1677006 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4090286 # DTB hits +system.cpu1.dtb.data_hits 4025428 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1814139 # ITB hits +system.cpu1.itb.fetch_hits 1801062 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1815203 # ITB accesses +system.cpu1.itb.fetch_accesses 1802126 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1395,52 +1305,52 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3919927793 # number of cpu cycles simulated +system.cpu1.numCycles 3921881188 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12950293 # Number of instructions committed -system.cpu1.committedOps 12950293 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11929999 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses -system.cpu1.num_func_calls 410658 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1281658 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11929999 # number of integer instructions -system.cpu1.num_fp_insts 174217 # number of float instructions -system.cpu1.num_int_register_reads 16394755 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8774296 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written -system.cpu1.num_mem_refs 4113222 # number of memory refs -system.cpu1.num_load_insts 2397194 # Number of load instructions -system.cpu1.num_store_insts 1716028 # Number of store instructions -system.cpu1.num_idle_cycles 3870487590.349789 # Number of idle cycles -system.cpu1.num_busy_cycles 49440202.650211 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles -system.cpu1.Branches 1846576 # Number of branches fetched +system.cpu1.committedInsts 12764983 # Number of instructions committed +system.cpu1.committedOps 12764983 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11763372 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses +system.cpu1.num_func_calls 404056 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1265589 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11763372 # number of integer instructions +system.cpu1.num_fp_insts 170364 # number of float instructions +system.cpu1.num_int_register_reads 16177579 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8656447 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written +system.cpu1.num_mem_refs 4047975 # number of memory refs +system.cpu1.num_load_insts 2361944 # Number of load instructions +system.cpu1.num_store_insts 1686031 # Number of store instructions +system.cpu1.num_idle_cycles 3873256564.808130 # Number of idle cycles +system.cpu1.num_busy_cycles 48624623.191870 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012398 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987602 # Percentage of idle cycles +system.cpu1.Branches 1821589 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78268 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26619 38.27% 38.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40454 58.16% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69559 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25752 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25236 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53474 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1908686801000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700508000 0.04% 97.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 362068000 0.02% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50214489500 2.56% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1959963866500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967429 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77081 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26132 38.19% 38.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 39821 58.19% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68428 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25288 48.13% 48.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24782 47.16% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 52545 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909614205500 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700881500 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 353850000 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50271627000 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960940564000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967702 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.623820 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.768757 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.622335 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.767887 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1456,87 +1366,87 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2001 2.79% 3.40% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63355 88.19% 91.60% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 2.99% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::rti 3718 5.18% 99.77% # number of callpals executed +system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62267 88.12% 91.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::rti 3685 5.22% 99.77% # number of callpals executed system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71838 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches +system.cpu1.kern.callpal::total 70661 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1917 # number of protection mode switches system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2906 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 809 +system.cpu1.kern.mode_switch::idle 2889 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 798 system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 441 -system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 430 +system.cpu1.kern.mode_switch_good::kernel 0.416275 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.151755 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309369 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17986814000 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1484472500 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1939632240000 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2002 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 317336 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.450379 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12635285 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 317847 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.752727 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1958987590000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.450379 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871973 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871973 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.148840 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.308465 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17543884000 0.90% 0.90% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1484004500 0.08% 0.97% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941017048000 99.03% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1956 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 311472 # number of replacements +system.cpu1.icache.tags.tagsinuse 449.263709 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12455839 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 311983 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.924736 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960006992500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 449.263709 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.877468 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.877468 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 437 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13271059 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13271059 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12635285 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12635285 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12635285 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12635285 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12635285 # number of overall hits -system.cpu1.icache.overall_hits::total 12635285 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 317887 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 317887 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 317887 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 317887 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 317887 # number of overall misses -system.cpu1.icache.overall_misses::total 317887 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4180819492 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4180819492 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4180819492 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4180819492 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4180819492 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4180819492 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953172 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12953172 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12953172 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12953172 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12953172 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12953172 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024541 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024541 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024541 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024541 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024541 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024541 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13151.904582 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13151.904582 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13151.904582 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13151.904582 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13079885 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13079885 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12455839 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12455839 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12455839 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12455839 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12455839 # number of overall hits +system.cpu1.icache.overall_hits::total 12455839 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 312023 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 312023 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 312023 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 312023 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 312023 # number of overall misses +system.cpu1.icache.overall_misses::total 312023 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4106650741 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4106650741 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4106650741 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4106650741 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4106650741 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4106650741 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12767862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12767862 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12767862 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12767862 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12767862 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024438 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024438 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024438 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024438 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024438 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024438 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13161.371889 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13161.371889 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13161.371889 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13161.371889 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1545,118 +1455,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317887 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 317887 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 317887 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 317887 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 317887 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 317887 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3544847508 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3544847508 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3544847508 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3544847508 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3544847508 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3544847508 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024541 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024541 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024541 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11151.281770 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312023 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 312023 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 312023 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 312023 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 312023 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 312023 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3482409259 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3482409259 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3482409259 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3482409259 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3482409259 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3482409259 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024438 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024438 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024438 # 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Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.619316 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67802253000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.752776 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948736 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.948736 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16587420 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16587420 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2220669 # 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number of cycles access was blocked @@ -1665,62 +1575,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 109122 # number of writebacks -system.cpu1.dcache.writebacks::total 109122 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116704 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 116704 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 56889 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 56889 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9081 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9081 # 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number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64195000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32145073 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32145073 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2105938196 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2105938196 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2105938196 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2105938196 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718207000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718207000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 736983000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 736983000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049930 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049930 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034433 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034433 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159003 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159003 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043512 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043512 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7069.155379 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7069.155379 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5340.600266 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5340.600266 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 106440 # number of writebacks +system.cpu1.dcache.writebacks::total 106440 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113735 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 113735 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55930 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 55930 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8863 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8863 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 169665 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 169665 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 169665 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 169665 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 895105752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 895105752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62746000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62746000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31539091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31539091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2039395752 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2039395752 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2039395752 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2039395752 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713537000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713537000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732313500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732313500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049377 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049377 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158744 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158744 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106262 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106262 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043206 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043206 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.019035 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.019035 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16004.036331 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16004.036331 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.544172 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.544172 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.055754 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.055754 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 1efa023f6..5b0dc7b99 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920428 # Number of seconds simulated -sim_ticks 1920428041000 # Number of ticks simulated -final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920416 # Number of seconds simulated +sim_ticks 1920416181000 # Number of ticks simulated +final_tick 1920416181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1405906 # Simulator instruction rate (inst/s) -host_op_rate 1405905 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48056353161 # Simulator tick rate (ticks/s) -host_mem_usage 307800 # Number of bytes of host memory used -host_seconds 39.96 # Real time elapsed on the host -sim_insts 56182750 # Number of instructions simulated -sim_ops 56182750 # Number of ops (including micro ops) simulated +host_inst_rate 1752736 # Simulator instruction rate (inst/s) +host_op_rate 1752735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59896862792 # Simulator tick rate (ticks/s) +host_mem_usage 308520 # Number of bytes of host memory used +host_seconds 32.06 # Real time elapsed on the host +sim_insts 56196255 # Number of instructions simulated +sim_ops 56196255 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory -system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28363328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7405888 # Number of bytes written to this memory +system.physmem.bytes_written::total 7405888 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442968 # Number of read requests accepted -system.physmem.writeReqs 115466 # Number of write requests accepted -system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue -system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 443177 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115717 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115717 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12945227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1381134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14769365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3856397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3856397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3856397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12945227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1381134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18625763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443177 # Number of read requests accepted +system.physmem.writeReqs 115717 # Number of write requests accepted +system.physmem.readBursts 443177 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115717 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28355584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue +system.physmem.bytesWritten 7404416 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28363328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7405888 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27966 # Per bank write bursts -system.physmem.perBankRdBursts::1 28089 # Per bank write bursts -system.physmem.perBankRdBursts::2 28297 # Per bank write bursts -system.physmem.perBankRdBursts::3 28053 # Per bank write bursts -system.physmem.perBankRdBursts::4 27407 # Per bank write bursts -system.physmem.perBankRdBursts::5 27545 # Per bank write bursts -system.physmem.perBankRdBursts::6 26911 # Per bank write bursts -system.physmem.perBankRdBursts::7 26762 # Per bank write bursts -system.physmem.perBankRdBursts::8 27807 # Per bank write bursts -system.physmem.perBankRdBursts::9 27255 # Per bank write bursts -system.physmem.perBankRdBursts::10 27714 # Per bank write bursts -system.physmem.perBankRdBursts::11 27327 # Per bank write bursts -system.physmem.perBankRdBursts::12 27431 # Per bank write bursts -system.physmem.perBankRdBursts::13 28073 # Per bank write bursts -system.physmem.perBankRdBursts::14 28024 # Per bank write bursts -system.physmem.perBankRdBursts::15 28256 # Per bank write bursts -system.physmem.perBankWrBursts::0 7722 # Per bank write bursts -system.physmem.perBankWrBursts::1 7593 # Per bank write bursts -system.physmem.perBankWrBursts::2 7833 # Per bank write bursts -system.physmem.perBankWrBursts::3 7543 # Per bank write bursts -system.physmem.perBankWrBursts::4 7010 # Per bank write bursts -system.physmem.perBankWrBursts::5 6982 # Per bank write bursts -system.physmem.perBankWrBursts::6 6469 # Per bank write bursts -system.physmem.perBankWrBursts::7 6223 # Per bank write bursts -system.physmem.perBankWrBursts::8 7224 # Per bank write bursts -system.physmem.perBankWrBursts::9 6661 # Per bank write bursts -system.physmem.perBankWrBursts::10 7099 # Per bank write bursts -system.physmem.perBankWrBursts::11 6780 # Per bank write bursts -system.physmem.perBankWrBursts::12 7009 # Per bank write bursts -system.physmem.perBankWrBursts::13 7722 # Per bank write bursts -system.physmem.perBankWrBursts::14 7773 # Per bank write bursts -system.physmem.perBankWrBursts::15 7817 # Per bank write bursts +system.physmem.perBankRdBursts::0 27851 # Per bank write bursts +system.physmem.perBankRdBursts::1 28132 # Per bank write bursts +system.physmem.perBankRdBursts::2 28319 # Per bank write bursts +system.physmem.perBankRdBursts::3 28010 # Per bank write bursts +system.physmem.perBankRdBursts::4 27531 # Per bank write bursts +system.physmem.perBankRdBursts::5 27552 # Per bank write bursts +system.physmem.perBankRdBursts::6 26732 # Per bank write bursts +system.physmem.perBankRdBursts::7 26855 # Per bank write bursts +system.physmem.perBankRdBursts::8 27890 # Per bank write bursts +system.physmem.perBankRdBursts::9 27110 # Per bank write bursts +system.physmem.perBankRdBursts::10 27744 # Per bank write bursts +system.physmem.perBankRdBursts::11 27465 # Per bank write bursts +system.physmem.perBankRdBursts::12 27482 # Per bank write bursts +system.physmem.perBankRdBursts::13 28199 # Per bank write bursts +system.physmem.perBankRdBursts::14 28116 # Per bank write bursts +system.physmem.perBankRdBursts::15 28068 # Per bank write bursts +system.physmem.perBankWrBursts::0 7630 # Per bank write bursts +system.physmem.perBankWrBursts::1 7636 # Per bank write bursts +system.physmem.perBankWrBursts::2 7854 # Per bank write bursts +system.physmem.perBankWrBursts::3 7535 # Per bank write bursts +system.physmem.perBankWrBursts::4 7127 # Per bank write bursts +system.physmem.perBankWrBursts::5 6994 # Per bank write bursts +system.physmem.perBankWrBursts::6 6317 # Per bank write bursts +system.physmem.perBankWrBursts::7 6319 # Per bank write bursts +system.physmem.perBankWrBursts::8 7309 # Per bank write bursts +system.physmem.perBankWrBursts::9 6529 # Per bank write bursts +system.physmem.perBankWrBursts::10 7110 # Per bank write bursts +system.physmem.perBankWrBursts::11 6915 # Per bank write bursts +system.physmem.perBankWrBursts::12 7060 # Per bank write bursts +system.physmem.perBankWrBursts::13 7819 # Per bank write bursts +system.physmem.perBankWrBursts::14 7860 # Per bank write bursts +system.physmem.perBankWrBursts::15 7680 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1920416169000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1920404309000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 442968 # Read request sizes (log2) +system.physmem.readPktSize::6 443177 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115466 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115717 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -133,289 +133,205 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation -system.physmem.totQLat 6257775000 # Total ticks spent queuing -system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks -system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 658.429646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 435.074403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 420.347464 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7559 16.39% 16.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6338 13.74% 30.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2663 5.77% 35.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1600 3.47% 39.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1319 2.86% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 861 1.87% 44.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 594 1.29% 45.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 461 1.00% 46.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24722 53.61% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46117 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6598 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 67.149288 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2598.278449 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6595 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6598 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.534707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.278859 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.820387 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4179 63.34% 63.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 322 4.88% 68.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 428 6.49% 74.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1303 19.75% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 22 0.33% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 17 0.26% 95.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 11 0.17% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 27 0.41% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 43 0.65% 96.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 28 0.42% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 21 0.32% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 25 0.38% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 19 0.29% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 43 0.65% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.06% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 12 0.18% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 10 0.15% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 5 0.08% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 4 0.06% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 5 0.08% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 9 0.14% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.06% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 2 0.03% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 3 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 6 0.09% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 8 0.12% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 5 0.08% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 6 0.09% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 3 0.05% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 4 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6598 # Writes before turning the bus around for reads +system.physmem.totQLat 7790286250 # Total ticks spent queuing +system.physmem.totMemAccLat 16274878750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2215280000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6269312500 # Total ticks spent accessing banks +system.physmem.avgQLat 17583.07 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14150.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 36733.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing -system.physmem.readRowHits 419360 # Number of row buffer hits during reads -system.physmem.writeRowHits 92763 # Number of row buffer hits during writes -system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes -system.physmem.avgGap 3438931.31 # Average gap between requests -system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18651952 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292310 # Transaction distribution -system.membus.trans_dist::ReadResp 292310 # Transaction distribution +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.59 # Average write queue length when enqueuing +system.physmem.readRowHits 398457 # Number of row buffer hits during reads +system.physmem.writeRowHits 94179 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.39 # Row buffer hit rate for writes +system.physmem.avgGap 3436079.67 # Average gap between requests +system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.57 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18667397 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292363 # Transaction distribution +system.membus.trans_dist::ReadResp 292363 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115466 # Transaction distribution +system.membus.trans_dist::Writeback 115717 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158141 # Transaction distribution -system.membus.trans_dist::ReadExResp 158141 # Transaction distribution +system.membus.trans_dist::ReadExReq 158297 # Transaction distribution +system.membus.trans_dist::ReadExResp 158297 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911366 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036046 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30460096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30504660 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35784340 # Total data (bytes) +system.membus.tot_pkt_size::total 35813780 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35813780 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1492987250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3752965347 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376688000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.344147 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1754500427000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.344147 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084009 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084009 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -429,14 +345,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134633 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134633 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13148459442 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13148459442 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13169594075 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13169594075 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13169594075 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13169594075 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -453,19 +369,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122165.508671 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 316433.852570 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 315628.378071 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 315628.378071 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 393896 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28296 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.920554 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -479,14 +395,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137633 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137633 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10985430442 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10985430442 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10997568075 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10997568075 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10997568075 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10997568075 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -495,14 +411,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -521,22 +437,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064966 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9066711 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6356267 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6357503 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15421233 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15424214 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973920 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4974520 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978917 # ITB accesses +system.cpu.itb.fetch_accesses 4979530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -549,52 +465,52 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840856082 # number of cpu cycles simulated +system.cpu.numCycles 3840832362 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56182750 # Number of instructions committed -system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses -system.cpu.num_func_calls 1483342 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls -system.cpu.num_int_insts 52054772 # number of integer instructions -system.cpu.num_fp_insts 324326 # number of float instructions -system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read -system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written -system.cpu.num_mem_refs 15473812 # number of memory refs -system.cpu.num_load_insts 9101789 # Number of load instructions -system.cpu.num_store_insts 6372023 # Number of store instructions -system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934400 # Percentage of idle cycles -system.cpu.Branches 8421946 # Number of branches fetched +system.cpu.committedInsts 56196255 # Number of instructions committed +system.cpu.committedOps 56196255 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52067788 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1483738 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469789 # number of instructions that are conditional controls +system.cpu.num_int_insts 52067788 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71342399 # number of times the integer registers were read +system.cpu.num_int_register_writes 38531411 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15476821 # number of memory refs +system.cpu.num_load_insts 9103557 # Number of load instructions +system.cpu.num_store_insts 6373264 # Number of store instructions +system.cpu.num_idle_cycles 3589010980.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251821381.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065564 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934436 # Percentage of idle cycles +system.cpu.Branches 8424076 # Number of branches fetched system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212001 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858066400000 96.75% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91407000 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737349500 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61520290500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920415447000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692248 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814083 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -630,10 +546,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175963 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -642,21 +558,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192898 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.callpal::total 192909 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1739 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4176 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46067941500 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5182686000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869164817500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -688,7 +604,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1409150 # Throughput (bytes/s) +system.iobus.throughput 1409159 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51202 # Transaction distribution @@ -748,67 +664,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380034075 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43162000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928358 # number of replacements -system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928494 # number of replacements +system.cpu.icache.tags.tagsinuse 508.301721 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55278924 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929005 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.503365 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39895254250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.301721 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992777 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57123599 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57123599 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits -system.cpu.icache.overall_hits::total 55265541 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses -system.cpu.icache.overall_misses::total 929029 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56194570 # 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average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57137254 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57137254 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55278924 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55278924 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55278924 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55278924 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55278924 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11098555742 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979 # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391286 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099982 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 107796250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978892 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1035,72 +951,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63152102 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63152102 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7814622 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814622 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852326 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852326 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182986 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182986 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199222 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199222 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13666948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13666948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13666948 # number of overall hits -system.cpu.dcache.overall_hits::total 13666948 # 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number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15040788 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15040788 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15040788 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15040788 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63164291 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63164291 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7816324 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816324 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853358 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853358 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13669682 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669682 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669682 # number of overall hits +system.cpu.dcache.overall_hits::total 13669682 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069509 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069509 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304562 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304562 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17233 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17233 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374071 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374071 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374071 # number of overall misses +system.cpu.dcache.overall_misses::total 1374071 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29019471009 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29019471009 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10854033885 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10854033885 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228736500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228736500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39873504894 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39873504894 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39873504894 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39873504894 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8885833 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8885833 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200260 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200260 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15043753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15043753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15043753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15043753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120361 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120361 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086053 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086053 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # 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average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29018.518617 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1109,54 +1025,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks -system.cpu.dcache.writebacks::total 835114 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.writebacks::writebacks 835359 # number of writebacks +system.cpu.dcache.writebacks::total 835359 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069509 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069509 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304562 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304562 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374071 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374071 # 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mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086053 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086053 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1164,31 +1080,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution +system.cpu.toL2Bus.throughput 105199341 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2023010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022993 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835359 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 346097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304546 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5509594 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59465280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142559956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 202025236 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 202015188 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2426388000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1396297259 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2187438394 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 786f029ca..789d25c60 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.196143 # Number of seconds simulated -sim_ticks 1196142873000 # Number of ticks simulated -final_tick 1196142873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.196225 # Number of seconds simulated +sim_ticks 1196225147500 # Number of ticks simulated +final_tick 1196225147500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 497666 # Simulator instruction rate (inst/s) -host_op_rate 634118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9685782626 # Simulator tick rate (ticks/s) -host_mem_usage 425428 # Number of bytes of host memory used -host_seconds 123.49 # Real time elapsed on the host -sim_insts 61459155 # Number of instructions simulated -sim_ops 78310163 # Number of ops (including micro ops) simulated +host_inst_rate 669591 # Simulator instruction rate (inst/s) +host_op_rate 853186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13029857543 # Simulator tick rate (ticks/s) +host_mem_usage 426076 # Number of bytes of host memory used +host_seconds 91.81 # Real time elapsed on the host +sim_insts 61472758 # Number of instructions simulated +sim_ops 78327958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -33,142 +33,138 @@ system.realview.nvmem.bw_total::cpu1.inst 40 # T system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4724988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 378508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4532924 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 324292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4798584 # Number of bytes read from this memory -system.physmem.bytes_read::total 62146244 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 324292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4113152 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 337988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4964984 # Number of bytes read from this memory +system.physmem.bytes_read::total 62119428 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 378508 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 337988 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4092288 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7140496 # Number of bytes written to this memory +system.physmem.bytes_written::total 7119632 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12374 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73902 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12142 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70901 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5158 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75006 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654512 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64268 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5372 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77606 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654093 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63942 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821104 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43393238 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 820778 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43390253 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 328854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3950187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 316419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3789357 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 271115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4011715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51955536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 328854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 271115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 599968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3438680 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2516709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5969601 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3438680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43393238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 282545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4150543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51929545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 316419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 282545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 598964 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3421001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2516536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5951749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3421001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43390253 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 328854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3964399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 316419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3803568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 271115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6528424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57925137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654512 # Number of read requests accepted -system.physmem.writeReqs 821104 # Number of write requests accepted -system.physmem.readBursts 6654512 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821104 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425857728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31040 # Total number of bytes read from write queue -system.physmem.bytesWritten 7268800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62146244 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7140496 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 485 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707525 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12040 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415388 # Per bank write bursts -system.physmem.perBankRdBursts::1 415219 # Per bank write bursts -system.physmem.perBankRdBursts::2 415339 # Per bank write bursts -system.physmem.perBankRdBursts::3 415675 # Per bank write bursts -system.physmem.perBankRdBursts::4 422392 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 282545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6667079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57881294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654093 # Number of read requests accepted +system.physmem.writeReqs 820778 # Number of write requests accepted +system.physmem.readBursts 6654093 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 820778 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425823936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 38016 # Total number of bytes read from write queue +system.physmem.bytesWritten 7142848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62119428 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7119632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 594 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709146 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 11979 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415258 # Per bank write bursts +system.physmem.perBankRdBursts::1 415304 # Per bank write bursts +system.physmem.perBankRdBursts::2 415298 # Per bank write bursts +system.physmem.perBankRdBursts::3 415715 # Per bank write bursts +system.physmem.perBankRdBursts::4 422332 # Per bank write bursts system.physmem.perBankRdBursts::5 415542 # Per bank write bursts -system.physmem.perBankRdBursts::6 415783 # Per bank write bursts -system.physmem.perBankRdBursts::7 415483 # Per bank write bursts -system.physmem.perBankRdBursts::8 416074 # Per bank write bursts -system.physmem.perBankRdBursts::9 415577 # Per bank write bursts -system.physmem.perBankRdBursts::10 415249 # Per bank write bursts -system.physmem.perBankRdBursts::11 414844 # Per bank write bursts -system.physmem.perBankRdBursts::12 415143 # Per bank write bursts -system.physmem.perBankRdBursts::13 415555 # Per bank write bursts -system.physmem.perBankRdBursts::14 415561 # Per bank write bursts -system.physmem.perBankRdBursts::15 415203 # Per bank write bursts -system.physmem.perBankWrBursts::0 6999 # Per bank write bursts -system.physmem.perBankWrBursts::1 6843 # Per bank write bursts -system.physmem.perBankWrBursts::2 7018 # Per bank write bursts -system.physmem.perBankWrBursts::3 7170 # Per bank write bursts -system.physmem.perBankWrBursts::4 7419 # Per bank write bursts -system.physmem.perBankWrBursts::5 7182 # Per bank write bursts -system.physmem.perBankWrBursts::6 7433 # Per bank write bursts -system.physmem.perBankWrBursts::7 7180 # Per bank write bursts -system.physmem.perBankWrBursts::8 7611 # Per bank write bursts -system.physmem.perBankWrBursts::9 7217 # Per bank write bursts -system.physmem.perBankWrBursts::10 7107 # Per bank write bursts -system.physmem.perBankWrBursts::11 6660 # Per bank write bursts -system.physmem.perBankWrBursts::12 6804 # Per bank write bursts -system.physmem.perBankWrBursts::13 7009 # Per bank write bursts -system.physmem.perBankWrBursts::14 7096 # Per bank write bursts -system.physmem.perBankWrBursts::15 6827 # Per bank write bursts +system.physmem.perBankRdBursts::6 415821 # Per bank write bursts +system.physmem.perBankRdBursts::7 415579 # Per bank write bursts +system.physmem.perBankRdBursts::8 415943 # Per bank write bursts +system.physmem.perBankRdBursts::9 415582 # Per bank write bursts +system.physmem.perBankRdBursts::10 415396 # Per bank write bursts +system.physmem.perBankRdBursts::11 414885 # Per bank write bursts +system.physmem.perBankRdBursts::12 414891 # Per bank write bursts +system.physmem.perBankRdBursts::13 415396 # Per bank write bursts +system.physmem.perBankRdBursts::14 415532 # Per bank write bursts +system.physmem.perBankRdBursts::15 415025 # Per bank write bursts +system.physmem.perBankWrBursts::0 6797 # Per bank write bursts +system.physmem.perBankWrBursts::1 6838 # Per bank write bursts +system.physmem.perBankWrBursts::2 6874 # Per bank write bursts +system.physmem.perBankWrBursts::3 7108 # Per bank write bursts +system.physmem.perBankWrBursts::4 7245 # Per bank write bursts +system.physmem.perBankWrBursts::5 7088 # Per bank write bursts +system.physmem.perBankWrBursts::6 7332 # Per bank write bursts +system.physmem.perBankWrBursts::7 7150 # Per bank write bursts +system.physmem.perBankWrBursts::8 7392 # Per bank write bursts +system.physmem.perBankWrBursts::9 7114 # Per bank write bursts +system.physmem.perBankWrBursts::10 7008 # Per bank write bursts +system.physmem.perBankWrBursts::11 6578 # Per bank write bursts +system.physmem.perBankWrBursts::12 6732 # Per bank write bursts +system.physmem.perBankWrBursts::13 6801 # Per bank write bursts +system.physmem.perBankWrBursts::14 7004 # Per bank write bursts +system.physmem.perBankWrBursts::15 6546 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1196138285000 # Total gap between requests +system.physmem.totGap 1196220625500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6849 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159599 # Read request sizes (log2) +system.physmem.readPktSize::6 159180 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64268 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 628282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 475071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 476093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1580129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1132007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1126499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1123122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 63942 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 568386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 406756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 406740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 413202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 408903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 410926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1188562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1189774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1562236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 22558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 14685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 15166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 13714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 12546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 9828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -183,758 +179,434 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5810.577695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 397.196541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13066.067638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25758 34.56% 34.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15237 20.44% 55.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3243 4.35% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2416 3.24% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1619 2.17% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1307 1.75% 66.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1041 1.40% 67.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1103 1.48% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 718 0.96% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 614 0.82% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 577 0.77% 71.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 705 0.95% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 343 0.46% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 280 0.38% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 211 0.28% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 365 0.49% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 178 0.24% 74.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.19% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 160 0.21% 75.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 121 0.16% 75.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2248 3.02% 78.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 145 0.19% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 165 0.22% 78.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 59 0.08% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 66 0.09% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 116 0.16% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 53 0.07% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 27 0.04% 79.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 17 0.02% 79.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 120 0.16% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 29 0.04% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 31 0.04% 79.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 12 0.02% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 26 0.03% 79.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 23 0.03% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 24 0.03% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 12 0.02% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 29 0.04% 80.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 10 0.01% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 25 0.03% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 133 0.18% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 12 0.02% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 14 0.02% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 45 0.06% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 4 0.01% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 21 0.03% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.01% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 17 0.02% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 31 0.04% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 79 0.11% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 18 0.02% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 3 0.00% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 183 0.25% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 2 0.00% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 24 0.03% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 3 0.00% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 17 0.02% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 18 0.02% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 95 0.13% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 11 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 5 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 15 0.02% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 100 0.13% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 4 0.01% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 16 0.02% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 174 0.23% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 9 0.01% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 93 0.12% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 3 0.00% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 214 0.29% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 32 0.04% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 12 0.02% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 160 0.21% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 1 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 23 0.03% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 12 0.02% 82.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 24 0.03% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 265 0.36% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 29 0.04% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 17 0.02% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 27 0.04% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 153 0.21% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 18 0.02% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 16 0.02% 83.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 33 0.04% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 214 0.29% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 86 0.12% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 12 0.02% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 17 0.02% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 106 0.14% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 1 0.00% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 81 0.11% 84.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 14 0.02% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 16 0.02% 84.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 3 0.00% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 158 0.21% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 76 0.10% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 84 0.11% 84.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 29 0.04% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 105 0.14% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13383 1 0.00% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 26 0.03% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 13 0.02% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 92 0.12% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 80 0.11% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 81 0.11% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 16 0.02% 85.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 110 0.15% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 77 0.10% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15815 1 0.00% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 13 0.02% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 82 0.11% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 3 0.00% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 155 0.21% 85.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 83 0.11% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 8 0.01% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 77 0.10% 86.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 119 0.16% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 21 0.03% 86.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 82 0.11% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 1 0.00% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 80 0.11% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 83 0.11% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 3 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 10 0.01% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18880-18887 1 0.00% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 83 0.11% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 103 0.14% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 25 0.03% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 80 0.11% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 1 0.00% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 73 0.10% 87.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 155 0.21% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 19 0.03% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 16 0.02% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 81 0.11% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 95 0.13% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 10 0.01% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 9 0.01% 87.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 219 0.29% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 30 0.04% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 2 0.00% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 22 0.03% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23872-23879 1 0.00% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 13 0.02% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 23 0.03% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 3 0.00% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 273 0.37% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 26 0.03% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 2 0.00% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 1 0.00% 88.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 24 0.03% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 143 0.19% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 12 0.02% 89.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 28 0.04% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 214 0.29% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 90 0.12% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 13 0.02% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 92 0.12% 89.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 79 0.11% 89.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 14 0.02% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 19 0.03% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 159 0.21% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 74 0.10% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 82 0.11% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 26 0.03% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 2 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 92 0.12% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 27 0.04% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 80 0.11% 90.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 9 0.01% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 85 0.11% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 81 0.11% 90.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 79 0.11% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 18 0.02% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 112 0.15% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 76 0.10% 91.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 8 0.01% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 82 0.11% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 154 0.21% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 83 0.11% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33088-33095 1 0.00% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 2 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 23 0.03% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 76 0.10% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 112 0.15% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 2 0.00% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 18 0.02% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 79 0.11% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 80 0.11% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 78 0.10% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34880-34887 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35008-35015 2 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 8 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 80 0.11% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 27 0.04% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 91 0.12% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 82 0.11% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 73 0.10% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 149 0.20% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 15 0.02% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 14 0.02% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 80 0.11% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 93 0.12% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 10 0.01% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 11 0.01% 93.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 90 0.12% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 212 0.28% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 1 0.00% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 27 0.04% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 11 0.01% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39872-39879 1 0.00% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 144 0.19% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 21 0.03% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 1 0.00% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 25 0.03% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 269 0.36% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 2 0.00% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 10 0.01% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 23 0.03% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 21 0.03% 94.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 11 0.01% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 1 0.00% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 31 0.04% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 219 0.29% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43072-43079 1 0.00% 95.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 87 0.12% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 11 0.01% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 80 0.11% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 18 0.02% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 149 0.20% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 71 0.10% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 78 0.10% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 1 0.00% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 27 0.04% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 99 0.13% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 83 0.11% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46656-46663 1 0.00% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 11 0.01% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 90 0.12% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 82 0.11% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 83 0.11% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 18 0.02% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 130 0.17% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 2 0.00% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 100 0.13% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48576-48583 1 0.00% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 6 0.01% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 79 0.11% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 5 0.01% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2052 2.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74541 # Bytes accessed per row activation -system.physmem.totQLat 159547739500 # Total ticks spent queuing -system.physmem.totMemAccLat 202481649500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33270135000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9663775000 # Total ticks spent accessing banks -system.physmem.avgQLat 23977.62 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1452.32 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 427748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.884371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 962.233746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 147.681447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5003 1.17% 1.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 3928 0.92% 2.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2092 0.49% 2.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1312 0.31% 2.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1079 0.25% 3.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 787 0.18% 3.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 742 0.17% 3.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 447 0.10% 3.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 412358 96.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 427748 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5121 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1299.254638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 29808.283067 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 5114 99.86% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 3 0.06% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.57286e+06-1.6384e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5121 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5121 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.793986 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.383938 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.006526 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2131 41.61% 41.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 296 5.78% 47.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 286 5.58% 52.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1314 25.66% 78.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 15 0.29% 78.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.10% 79.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 79.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.04% 79.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 79.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.06% 79.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.02% 79.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 79.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 953 18.61% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 61 1.19% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 17 0.33% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 33 0.64% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5121 # Writes before turning the bus around for reads +system.physmem.totQLat 249828830750 # Total ticks spent queuing +system.physmem.totMemAccLat 297299498250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33267495000 # Total ticks spent in databus transfers +system.physmem.totBankLat 14203172500 # Total ticks spent accessing banks +system.physmem.avgQLat 37548.49 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 2134.69 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30429.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44683.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 355.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.60 # Average write queue length when enqueuing -system.physmem.readRowHits 6598250 # Number of row buffer hits during reads -system.physmem.writeRowHits 94811 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes -system.physmem.avgGap 160005.31 # Average gap between requests -system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.94 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 59942042 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703387 # Transaction distribution -system.membus.trans_dist::ReadResp 7703387 # Transaction distribution -system.membus.trans_dist::WriteReq 767577 # Transaction distribution -system.membus.trans_dist::WriteResp 767577 # Transaction distribution -system.membus.trans_dist::Writeback 64268 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31533 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17272 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12040 # Transaction distribution -system.membus.trans_dist::ReadExReq 137758 # Transaction distribution -system.membus.trans_dist::ReadExResp 137334 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382660 # Packet count per connected master and slave (bytes) +system.physmem.avgRdQLen 4.56 # Average read queue length when enqueuing +system.physmem.avgWrQLen 29.44 # Average write queue length when enqueuing +system.physmem.readRowHits 6202256 # Number of row buffer hits during reads +system.physmem.writeRowHits 93908 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.12 # Row buffer hit rate for writes +system.physmem.avgGap 160032.28 # Average gap between requests +system.physmem.pageHitRate 93.07 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 6.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 59898120 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703395 # Transaction distribution +system.membus.trans_dist::ReadResp 7703395 # Transaction distribution +system.membus.trans_dist::WriteReq 767585 # Transaction distribution +system.membus.trans_dist::WriteResp 767585 # Transaction distribution +system.membus.trans_dist::Writeback 63942 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31730 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17317 # Transaction distribution +system.membus.trans_dist::UpgradeResp 11979 # Transaction distribution +system.membus.trans_dist::ReadExReq 137317 # Transaction distribution +system.membus.trans_dist::ReadExResp 136921 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382690 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972105 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366005 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4365038 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17342133 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390026 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17341166 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390070 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17382228 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19794734 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17334548 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19747126 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71699246 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71699246 # Total data (bytes) +system.membus.tot_pkt_size::total 71651638 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71651638 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224801500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224825500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9220500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9234000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 786000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9211496500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9208108500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5081612097 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5075173558 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657936499 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 16181474500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69480 # number of replacements -system.l2c.tags.tagsinuse 52958.538682 # Cycle average of tags in use -system.l2c.tags.total_refs 1674406 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134639 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.436263 # Average number of references to valid blocks. +system.l2c.tags.replacements 69062 # number of replacements +system.l2c.tags.tagsinuse 52959.899517 # Cycle average of tags in use +system.l2c.tags.total_refs 1674433 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134270 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.470641 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40140.336267 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001545 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3711.388388 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4232.378884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742427 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2812.770235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2058.918835 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.612493 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 40142.433744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.003238 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3707.808501 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4231.213775 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742447 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2816.465022 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2059.232379 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.612525 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056631 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064581 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056577 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064563 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042919 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031417 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808083 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042976 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031421 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808104 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65154 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.218290 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10017.630473 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.364979 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.045933 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54359.154437 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62553.446065 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58607.238626 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62634.983898 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65245.961117 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61051.226425 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.996270 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.171207 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10007.333255 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.378284 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.778261 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.664403 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54298.300803 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61205.868133 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58038.759616 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1128,62 +788,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119544694 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2535779 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535779 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767577 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767577 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 570959 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30837 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17592 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48429 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260947 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260947 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1227966 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6129 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12680 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940064 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600791 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6258 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15477 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7673967 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27250848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41432384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30058932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39583066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22216 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138377350 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138377350 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4615184 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4759626187 # Layer occupancy (ticks) +system.toL2Bus.throughput 119642613 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2536412 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2536412 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767585 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767585 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 572475 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30937 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17621 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48558 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260776 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260776 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 723469 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1059051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4339 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 7907 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1082141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4772543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7929 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 20256 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7677635 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 22743520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35146882 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6636 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 11992 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 34596404 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 46050592 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7620 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 25500 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138589146 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138589146 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4530356 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4766758175 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1926082966 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1756498781 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1607753214 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1517597206 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 2680000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 4909499 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2116921475 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2437223968 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2926499865 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 3163938724 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer8.occupancy 6024000 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 9923499 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 13881500 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45391348 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671431 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671431 # Transaction distribution -system.iobus.trans_dist::WriteReq 7963 # Transaction distribution -system.iobus.trans_dist::WriteResp 7963 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8056 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45388263 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671442 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671442 # Transaction distribution +system.iobus.trans_dist::WriteReq 7967 # Transaction distribution +system.iobus.trans_dist::WriteResp 7967 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8070 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1205,12 +865,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382660 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382690 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358788 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358818 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16140 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1232,14 +892,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390026 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390070 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294538 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294538 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294582 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294582 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21430000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4034000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4041000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1285,10 +945,10 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374697000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374723000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17777962501 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.respLayer1.occupancy 16195242500 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1312,25 +972,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070497 # DTB read hits -system.cpu0.dtb.read_misses 3747 # DTB read misses -system.cpu0.dtb.write_hits 5655659 # DTB write hits -system.cpu0.dtb.write_misses 806 # DTB write misses +system.cpu0.dtb.read_hits 5879584 # DTB read hits +system.cpu0.dtb.read_misses 2138 # DTB read misses +system.cpu0.dtb.write_hits 4838515 # DTB write hits +system.cpu0.dtb.write_misses 406 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1708 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1387 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7074244 # DTB read accesses -system.cpu0.dtb.write_accesses 5656465 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 5881722 # DTB read accesses +system.cpu0.dtb.write_accesses 4838921 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12726156 # DTB hits -system.cpu0.dtb.misses 4553 # DTB misses -system.cpu0.dtb.accesses 12730709 # DTB accesses +system.cpu0.dtb.hits 10718099 # DTB hits +system.cpu0.dtb.misses 2544 # DTB misses +system.cpu0.dtb.accesses 10720643 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1352,8 +1012,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 29571351 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.itb.inst_hits 24773464 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1362,95 +1022,94 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 963 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29573556 # ITB inst accesses -system.cpu0.itb.hits 29571351 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29573556 # DTB accesses -system.cpu0.numCycles 2392285746 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 24774814 # ITB inst accesses +system.cpu0.itb.hits 24773464 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 24774814 # DTB accesses +system.cpu0.numCycles 2391604989 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28873226 # Number of instructions committed -system.cpu0.committedOps 37212709 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33137047 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1242091 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373605 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33137047 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 192300691 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36265278 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13394015 # number of memory refs -system.cpu0.num_load_insts 7407936 # Number of load instructions -system.cpu0.num_store_insts 5986079 # Number of store instructions -system.cpu0.num_idle_cycles 2246427166.466122 # Number of idle cycles -system.cpu0.num_busy_cycles 145858579.533878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060970 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939030 # Percentage of idle cycles -system.cpu0.Branches 5601726 # Number of branches fetched +system.cpu0.committedInsts 24375312 # Number of instructions committed +system.cpu0.committedOps 31460856 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28085533 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses +system.cpu0.num_func_calls 1070699 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3751745 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28085533 # number of integer instructions +system.cpu0.num_fp_insts 4364 # number of float instructions +system.cpu0.num_int_register_reads 162520351 # number of times the integer registers were read +system.cpu0.num_int_register_writes 30535592 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written +system.cpu0.num_mem_refs 11309766 # number of memory refs +system.cpu0.num_load_insts 6158982 # Number of load instructions +system.cpu0.num_store_insts 5150784 # Number of store instructions +system.cpu0.num_idle_cycles 2265857607.135565 # Number of idle cycles +system.cpu0.num_busy_cycles 125747381.864435 # Number of busy cycles +system.cpu0.not_idle_fraction 0.052579 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.947421 # Percentage of idle cycles +system.cpu0.Branches 4778581 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46915 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 425414 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.356883 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29145407 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425926 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.428335 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76234819000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.356883 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994838 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994838 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 39137 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 354708 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.352361 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 24418226 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 355220 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.741135 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76254991000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352361 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994829 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994829 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29997261 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29997261 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29145407 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29145407 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29145407 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29145407 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29145407 # number of overall hits -system.cpu0.icache.overall_hits::total 29145407 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425927 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425927 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425927 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425927 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425927 # number of overall misses -system.cpu0.icache.overall_misses::total 425927 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899388216 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5899388216 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5899388216 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5899388216 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5899388216 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5899388216 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29571334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29571334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29571334 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29571334 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29571334 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29571334 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014403 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014403 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014403 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014403 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014403 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014403 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13850.702623 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13850.702623 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13850.702623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13850.702623 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 25128668 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 25128668 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 24418226 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 24418226 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 24418226 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 24418226 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 24418226 # number of overall hits +system.cpu0.icache.overall_hits::total 24418226 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 355221 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 355221 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 355221 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 355221 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 355221 # number of overall misses +system.cpu0.icache.overall_misses::total 355221 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4963623214 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 4963623214 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 4963623214 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 4963623214 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 4963623214 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 4963623214 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 24773447 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 24773447 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 24773447 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 24773447 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 24773447 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 24773447 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014339 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014339 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014339 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014339 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014339 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014339 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13973.338327 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13973.338327 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13973.338327 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13973.338327 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1459,128 +1118,126 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425927 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425927 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425927 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425927 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425927 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425927 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045293784 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045293784 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045293784 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5045293784 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045293784 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5045293784 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 437016250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 437016250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014403 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014403 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014403 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11845.442491 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355221 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 355221 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 355221 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 355221 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 355221 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 355221 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4251043786 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4251043786 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4251043786 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4251043786 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4251043786 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4251043786 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 443885000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 443885000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 443885000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 443885000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014339 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014339 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014339 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11967.321149 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 330503 # number of replacements -system.cpu0.dcache.tags.tagsinuse 455.093016 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12270625 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 331015 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.069695 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 667204250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.093016 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.888854 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.888854 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50903218 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50903218 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6600273 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6600273 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5350518 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5350518 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147975 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147975 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149621 # 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number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369480 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369480 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369480 # number of overall misses -system.cpu0.dcache.overall_misses::total 369480 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3309712250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3309712250 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5686464712 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5686464712 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92538750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 92538750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44740069 # 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Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 279247 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.956379 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 673996250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.142717 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.885044 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.885044 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 379 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 42855830 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 42855830 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5473702 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5473702 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4567964 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4567964 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129389 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 129389 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130155 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 130155 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10041666 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10041666 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10041666 # number of overall hits +system.cpu0.dcache.overall_hits::total 10041666 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 191503 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 191503 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 126416 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 126416 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8708 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8708 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7742 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7742 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 317919 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 317919 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 317919 # number of overall misses +system.cpu0.dcache.overall_misses::total 317919 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2845005745 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 2845005745 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5278408391 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5278408391 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82648500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 82648500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45599070 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45599070 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8123414136 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8123414136 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8123414136 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8123414136 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5665205 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5665205 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4694380 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4694380 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138097 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 138097 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137897 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 137897 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10359585 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10359585 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10359585 # 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miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030688 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030688 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.194133 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.194133 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41754.274704 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41754.274704 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9491.100138 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9491.100138 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5889.830793 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5889.830793 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25551.835958 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25551.835958 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1589,62 +1246,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306085 # number of writebacks -system.cpu0.dcache.writebacks::total 306085 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227769 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227769 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141711 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141711 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9370 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9370 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7530 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7530 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369480 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369480 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369480 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369480 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2852244750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2852244750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372105288 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5372105288 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73750250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73750250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29678931 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29678931 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8224350038 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8224350038 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8224350038 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8224350038 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13565968500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13565968500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170779500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170779500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14736748000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14736748000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033358 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033358 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025802 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025802 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059551 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059551 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047915 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047915 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029990 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029990 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.532698 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.532698 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37908.879960 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37908.879960 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7870.891142 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7870.891142 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3941.425100 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3941.425100 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 257140 # number of writebacks +system.cpu0.dcache.writebacks::total 257140 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191503 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 191503 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126416 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 126416 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8708 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8708 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7738 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7738 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 317919 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 317919 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 317919 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 317919 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2460118255 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2460118255 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4997663609 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4997663609 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65185500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65185500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30121930 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30121930 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7457781864 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7457781864 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7457781864 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7457781864 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12214482000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12214482000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1164635000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1164635000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13379117000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13379117000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033803 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033803 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063057 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063057 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056114 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056114 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030688 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030688 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12846.369274 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12846.369274 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39533.473682 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39533.473682 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7485.702802 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7485.702802 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3892.728095 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3892.728095 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1675,25 +1332,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8312417 # DTB read hits -system.cpu1.dtb.read_misses 3644 # DTB read misses -system.cpu1.dtb.write_hits 5828126 # DTB write hits -system.cpu1.dtb.write_misses 1438 # DTB write misses +system.cpu1.dtb.read_hits 9507781 # DTB read hits +system.cpu1.dtb.read_misses 5255 # DTB read misses +system.cpu1.dtb.write_hits 6647969 # DTB write hits +system.cpu1.dtb.write_misses 1834 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1864 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2187 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 188 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8316061 # DTB read accesses -system.cpu1.dtb.write_accesses 5829564 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 9513036 # DTB read accesses +system.cpu1.dtb.write_accesses 6649803 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14140543 # DTB hits -system.cpu1.dtb.misses 5082 # DTB misses -system.cpu1.dtb.accesses 14145625 # DTB accesses +system.cpu1.dtb.hits 16155750 # DTB hits +system.cpu1.dtb.misses 7089 # DTB misses +system.cpu1.dtb.accesses 16162839 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1715,8 +1372,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 33196912 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.itb.inst_hits 38008437 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1725,94 +1382,95 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1485 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33199083 # ITB inst accesses -system.cpu1.itb.hits 33196912 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33199083 # DTB accesses -system.cpu1.numCycles 2390815191 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 38011454 # ITB inst accesses +system.cpu1.itb.hits 38008437 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 38011454 # DTB accesses +system.cpu1.numCycles 2392450295 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32585929 # Number of instructions committed -system.cpu1.committedOps 41097454 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37620588 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962436 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3733629 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37620588 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 218203394 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39762349 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14678716 # number of memory refs -system.cpu1.num_load_insts 8634369 # Number of load instructions -system.cpu1.num_store_insts 6044347 # Number of store instructions -system.cpu1.num_idle_cycles 1874341984.155535 # Number of idle cycles -system.cpu1.num_busy_cycles 516473206.844465 # Number of busy cycles -system.cpu1.not_idle_fraction 0.216024 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.783976 # Percentage of idle cycles -system.cpu1.Branches 4945874 # Number of branches fetched +system.cpu1.committedInsts 37097446 # Number of instructions committed +system.cpu1.committedOps 46867102 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 42687988 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1134316 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4357000 # number of instructions that are conditional controls +system.cpu1.num_int_insts 42687988 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 248074220 # number of times the integer registers were read +system.cpu1.num_int_register_writes 45509439 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 16770062 # number of memory refs +system.cpu1.num_load_insts 9887948 # Number of load instructions +system.cpu1.num_store_insts 6882114 # Number of store instructions +system.cpu1.num_idle_cycles 1855714829.552449 # Number of idle cycles +system.cpu1.num_busy_cycles 536735465.447551 # Number of busy cycles +system.cpu1.not_idle_fraction 0.224346 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.775654 # Percentage of idle cycles +system.cpu1.Branches 5771094 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469670 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.560169 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32726726 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 470182 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.604379 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 94003216500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.560169 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934688 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934688 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 52097 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 540849 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.554171 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 37467072 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 541361 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.209034 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 94011084500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.554171 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934676 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934676 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33667090 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33667090 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32726726 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32726726 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32726726 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32726726 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32726726 # number of overall hits -system.cpu1.icache.overall_hits::total 32726726 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 470182 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 470182 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 470182 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 470182 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 470182 # number of overall misses -system.cpu1.icache.overall_misses::total 470182 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6443403725 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6443403725 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6443403725 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6443403725 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6443403725 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6443403725 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196908 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33196908 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33196908 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33196908 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33196908 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33196908 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014163 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014163 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014163 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014163 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014163 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014163 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13704.062948 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13704.062948 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13704.062948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13704.062948 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 38549794 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 38549794 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 37467072 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 37467072 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 37467072 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 37467072 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 37467072 # number of overall hits +system.cpu1.icache.overall_hits::total 37467072 # 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number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 38008433 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 38008433 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 38008433 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 38008433 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 38008433 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 38008433 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014243 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014243 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014243 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014243 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014243 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5501099275 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5501099275 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5501099275 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6820250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6820250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6820250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6820250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014163 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014163 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014163 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11699.935929 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 541361 # 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mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11635.146939 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # 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miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108436 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026522 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026522 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026522 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026522 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13002.735221 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13002.735221 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43767.721489 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 43767.721489 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8600.877584 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8600.877584 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5168.932823 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5168.932823 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27394.501587 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27394.501587 # average overall miss latency +system.cpu1.dcache.tags.replacements 343803 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.607785 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 13921652 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 344315 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.432894 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 85311468250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.607785 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923062 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923062 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 57519242 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 57519242 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 8078143 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8078143 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5612875 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5612875 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100617 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 100617 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102310 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 102310 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 13691018 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 13691018 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 13691018 # number of overall hits +system.cpu1.dcache.overall_hits::total 13691018 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 207066 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 207066 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 165297 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 165297 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11987 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11987 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9884 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9884 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 372363 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 372363 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 372363 # number of overall misses +system.cpu1.dcache.overall_misses::total 372363 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2696827750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2696827750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6860807042 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6860807042 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 107474000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 107474000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50841959 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50841959 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9557634792 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9557634792 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9557634792 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9557634792 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8285209 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8285209 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5778172 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5778172 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112604 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 112604 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112194 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 112194 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14063381 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14063381 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14063381 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14063381 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024992 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.024992 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106453 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106453 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.088097 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088097 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026477 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026477 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026477 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026477 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13024.000802 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13024.000802 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41505.938051 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41505.938051 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8965.879703 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8965.879703 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5143.864731 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5143.864731 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25667.520113 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 25667.520113 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1949,62 +1608,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 264874 # number of writebacks -system.cpu1.dcache.writebacks::total 264874 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170735 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170735 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150073 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150073 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11224 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11224 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320808 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320808 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320808 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320808 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877877002 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877877002 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6244849733 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6244849733 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74077750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74077750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31889029 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31889029 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8122726735 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8122726735 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8122726735 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8122726735 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168606064250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168606064250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182609871 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182609871 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193788674121 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193788674121 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023986 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023986 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030149 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030149 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120378 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120378 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108426 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108426 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026522 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026522 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10998.781749 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10998.781749 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41612.080341 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41612.080341 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6599.942088 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6599.942088 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3169.253528 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3169.253528 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 315335 # number of writebacks +system.cpu1.dcache.writebacks::total 315335 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207066 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 207066 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165297 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 165297 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11987 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11987 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 372363 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 372363 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 372363 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 372363 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2282040250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2282040250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6506824958 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6506824958 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 83489000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83489000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31075041 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31075041 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8788865208 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8788865208 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8788865208 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8788865208 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169960243250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169960243250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25194386277 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25194386277 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195154629527 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195154629527 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106453 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106453 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088088 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088088 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026477 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026477 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11020.835144 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11020.835144 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39364.446772 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39364.446772 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6964.962042 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6964.962042 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3144.292320 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3144.292320 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2028,10 +1687,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651823594501 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651823594501 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651823594501 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651823594501 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 746722879500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 746722879500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 746722879500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 746722879500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 524da38ff..823848f29 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,146 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616552 # Number of seconds simulated -sim_ticks 2616552083000 # Number of ticks simulated -final_tick 2616552083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616536 # Number of seconds simulated +sim_ticks 2616536215000 # Number of ticks simulated +final_tick 2616536215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 423166 # Simulator instruction rate (inst/s) -host_op_rate 538494 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18392483259 # Simulator tick rate (ticks/s) -host_mem_usage 421292 # Number of bytes of host memory used -host_seconds 142.26 # Real time elapsed on the host -sim_insts 60200379 # Number of instructions simulated -sim_ops 76607188 # Number of ops (including micro ops) simulated +host_inst_rate 594955 # Simulator instruction rate (inst/s) +host_op_rate 757104 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25859148121 # Simulator tick rate (ticks/s) +host_mem_usage 420956 # Number of bytes of host memory used +host_seconds 101.18 # Real time elapsed on the host +sim_insts 60200059 # Number of instructions simulated +sim_ops 76606878 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9089880 # Number of bytes read from this memory -system.physmem.bytes_read::total 132477664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089816 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477600 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3706240 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory +system.physmem.bytes_written::total 6722312 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142065 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494707 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 142064 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494706 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57910 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46887426 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811928 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46887710 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3473992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50630624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1416484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1152689 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2569173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1416484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46887426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3473988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50630906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1416468 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2569165 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1416468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46887710 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4626681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53199797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494707 # Number of read requests accepted -system.physmem.writeReqs 811929 # Number of write requests accepted -system.physmem.readBursts 15494707 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991550144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 111104 # Total number of bytes read from write queue -system.physmem.bytesWritten 6844864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132477664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1736 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704958 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4626685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53200071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494706 # Number of read requests accepted +system.physmem.writeReqs 811928 # Number of write requests accepted +system.physmem.readBursts 15494706 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811928 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991531648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 129536 # Total number of bytes read from write queue +system.physmem.bytesWritten 6740736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132477600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6722312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2024 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706583 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 967983 # Per bank write bursts +system.physmem.perBankRdBursts::0 967775 # Per bank write bursts system.physmem.perBankRdBursts::1 967715 # Per bank write bursts system.physmem.perBankRdBursts::2 967672 # Per bank write bursts -system.physmem.perBankRdBursts::3 967769 # Per bank write bursts -system.physmem.perBankRdBursts::4 974609 # Per bank write bursts -system.physmem.perBankRdBursts::5 968229 # Per bank write bursts -system.physmem.perBankRdBursts::6 967819 # Per bank write bursts -system.physmem.perBankRdBursts::7 967736 # Per bank write bursts -system.physmem.perBankRdBursts::8 968546 # Per bank write bursts +system.physmem.perBankRdBursts::3 967748 # Per bank write bursts +system.physmem.perBankRdBursts::4 974561 # Per bank write bursts +system.physmem.perBankRdBursts::5 968173 # Per bank write bursts +system.physmem.perBankRdBursts::6 967769 # Per bank write bursts +system.physmem.perBankRdBursts::7 967703 # Per bank write bursts +system.physmem.perBankRdBursts::8 968545 # Per bank write bursts system.physmem.perBankRdBursts::9 968137 # Per bank write bursts system.physmem.perBankRdBursts::10 967949 # Per bank write bursts system.physmem.perBankRdBursts::11 967746 # Per bank write bursts system.physmem.perBankRdBursts::12 967851 # Per bank write bursts system.physmem.perBankRdBursts::13 967741 # Per bank write bursts -system.physmem.perBankRdBursts::14 967672 # Per bank write bursts +system.physmem.perBankRdBursts::14 967800 # Per bank write bursts system.physmem.perBankRdBursts::15 967797 # Per bank write bursts -system.physmem.perBankWrBursts::0 6609 # Per bank write bursts -system.physmem.perBankWrBursts::1 6410 # Per bank write bursts -system.physmem.perBankWrBursts::2 6425 # Per bank write bursts -system.physmem.perBankWrBursts::3 6343 # Per bank write bursts -system.physmem.perBankWrBursts::4 6914 # Per bank write bursts -system.physmem.perBankWrBursts::5 7103 # Per bank write bursts -system.physmem.perBankWrBursts::6 6905 # Per bank write bursts -system.physmem.perBankWrBursts::7 6899 # Per bank write bursts -system.physmem.perBankWrBursts::8 7185 # Per bank write bursts -system.physmem.perBankWrBursts::9 6844 # Per bank write bursts -system.physmem.perBankWrBursts::10 6668 # Per bank write bursts -system.physmem.perBankWrBursts::11 6551 # Per bank write bursts -system.physmem.perBankWrBursts::12 6595 # Per bank write bursts -system.physmem.perBankWrBursts::13 6390 # Per bank write bursts -system.physmem.perBankWrBursts::14 6535 # Per bank write bursts -system.physmem.perBankWrBursts::15 6575 # Per bank write bursts +system.physmem.perBankWrBursts::0 6510 # Per bank write bursts +system.physmem.perBankWrBursts::1 6313 # Per bank write bursts +system.physmem.perBankWrBursts::2 6323 # Per bank write bursts +system.physmem.perBankWrBursts::3 6241 # Per bank write bursts +system.physmem.perBankWrBursts::4 6804 # Per bank write bursts +system.physmem.perBankWrBursts::5 6995 # Per bank write bursts +system.physmem.perBankWrBursts::6 6800 # Per bank write bursts +system.physmem.perBankWrBursts::7 6791 # Per bank write bursts +system.physmem.perBankWrBursts::8 7084 # Per bank write bursts +system.physmem.perBankWrBursts::9 6747 # Per bank write bursts +system.physmem.perBankWrBursts::10 6568 # Per bank write bursts +system.physmem.perBankWrBursts::11 6457 # Per bank write bursts +system.physmem.perBankWrBursts::12 6495 # Per bank write bursts +system.physmem.perBankWrBursts::13 6295 # Per bank write bursts +system.physmem.perBankWrBursts::14 6428 # Per bank write bursts +system.physmem.perBankWrBursts::15 6473 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2616547722000 # Total gap between requests +system.physmem.totGap 2616531854000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15335424 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152619 # Read request sizes (log2) +system.physmem.readPktSize::6 152618 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57911 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1246677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1099488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1103361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2684438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2678406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2686634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 54458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20429 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 160 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57910 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1116573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 975907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 963056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 965451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2812276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2805674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3709925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 42008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 34639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 36264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 33338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 31474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 22310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 21858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -156,563 +144,198 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11129.630393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1027.657053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16709.623735 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23265 25.93% 25.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14539 16.21% 42.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2841 3.17% 45.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2049 2.28% 47.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1384 1.54% 49.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1206 1.34% 50.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 956 1.07% 51.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1124 1.25% 52.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 653 0.73% 53.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 549 0.61% 54.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 562 0.63% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 672 0.75% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 328 0.37% 55.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 247 0.28% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 203 0.23% 56.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 737 0.82% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 166 0.19% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 147 0.16% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 151 0.17% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 100 0.11% 58.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2290 2.55% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 54 0.06% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 47 0.05% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 132 0.15% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 20 0.02% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 24 0.03% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 30 0.03% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 15 0.02% 61.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 101 0.11% 61.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 16 0.02% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 24 0.03% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 89 0.10% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 8 0.01% 61.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 22 0.02% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 154 0.17% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 15 0.02% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 13 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 380 0.42% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 15 0.02% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 13 0.01% 62.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 16 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 17 0.02% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 10 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 98 0.11% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 14 0.02% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 34 0.04% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 92 0.10% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 11 0.01% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 10 0.01% 63.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 228 0.25% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 8 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 164 0.18% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 10 0.01% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 80 0.09% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 9 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 8 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 90 0.10% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 8 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 9 0.01% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 436 0.49% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 10 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 7 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 8 0.01% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 28 0.03% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 68 0.08% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 11 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 279 0.31% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 70 0.08% 65.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 270 0.30% 65.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 65.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 82 0.09% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 3 0.00% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 143 0.16% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 1 0.00% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 2 0.00% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 411 0.46% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 87 0.10% 66.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 21 0.02% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 78 0.09% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 402 0.45% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 81 0.09% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 23 0.03% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 84 0.09% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 405 0.45% 67.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 148 0.16% 67.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 87 0.10% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 20 0.02% 67.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 273 0.30% 68.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10311 1 0.00% 68.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 69 0.08% 68.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 145 0.16% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 1 0.00% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 18 0.02% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 7 0.01% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 431 0.48% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 83 0.09% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 80 0.09% 68.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 159 0.18% 69.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 2 0.00% 69.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 208 0.23% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 3 0.00% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 82 0.09% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 88 0.10% 69.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 148 0.16% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 354 0.39% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13447 2 0.00% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 141 0.16% 70.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13639 1 0.00% 70.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 73 0.08% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 83 0.09% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 279 0.31% 70.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 93 0.10% 70.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 1 0.00% 70.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 91 0.10% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 15 0.02% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 4 0.00% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 490 0.55% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 72 0.08% 71.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 2 0.00% 71.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 143 0.16% 71.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 77 0.09% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 10 0.01% 71.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 534 0.60% 72.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 75 0.08% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 145 0.16% 72.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 76 0.08% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 3 0.00% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 492 0.55% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 16 0.02% 73.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 2 0.00% 73.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 87 0.10% 73.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 95 0.11% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 2 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 275 0.31% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 81 0.09% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 73 0.08% 74.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 143 0.16% 74.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 347 0.39% 74.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 2 0.00% 74.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 136 0.15% 74.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19776-19783 1 0.00% 74.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 88 0.10% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 84 0.09% 74.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 5 0.01% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 216 0.24% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20544-20551 1 0.00% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 155 0.17% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 77 0.09% 75.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 79 0.09% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 5 0.01% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 419 0.47% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 21 0.02% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 147 0.16% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 72 0.08% 76.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 4 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 265 0.30% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 21 0.02% 76.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 84 0.09% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 141 0.16% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 5 0.01% 76.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 410 0.46% 77.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 87 0.10% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 18 0.02% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 80 0.09% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 395 0.44% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 76 0.08% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 19 0.02% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25287 1 0.00% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 88 0.10% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25927 2 0.00% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 88 0.10% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 20 0.02% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 3 0.00% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 274 0.31% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 69 0.08% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 144 0.16% 79.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 23 0.03% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 414 0.46% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27776-27783 1 0.00% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 80 0.09% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 2 0.00% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 76 0.08% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 158 0.18% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 213 0.24% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 78 0.09% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 89 0.10% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 137 0.15% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 346 0.39% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 142 0.16% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 1 0.00% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 72 0.08% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 82 0.09% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 276 0.31% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 91 0.10% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 88 0.10% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 20 0.02% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 482 0.54% 82.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 73 0.08% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 142 0.16% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 2 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 83 0.09% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32704-32711 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 535 0.60% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 89 0.10% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 149 0.17% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 76 0.08% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 481 0.54% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 15 0.02% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 88 0.10% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 92 0.10% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34624-34631 1 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 3 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 267 0.30% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 2 0.00% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 81 0.09% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 74 0.08% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 144 0.16% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 346 0.39% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 134 0.15% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 86 0.10% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 1 0.00% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 79 0.09% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 207 0.23% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37056-37063 1 0.00% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 154 0.17% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 75 0.08% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 87 0.10% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 418 0.47% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 20 0.02% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38208-38215 1 0.00% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 142 0.16% 87.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 3 0.00% 87.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 69 0.08% 87.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 267 0.30% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 18 0.02% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39303 2 0.00% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 85 0.09% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 2 0.00% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 145 0.16% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 411 0.46% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 83 0.09% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40263 1 0.00% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 2 0.00% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 16 0.02% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 79 0.09% 88.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 395 0.44% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 17 0.02% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 3 0.00% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 89 0.10% 89.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 405 0.45% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42048-42055 1 0.00% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 142 0.16% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 82 0.09% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 22 0.02% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 265 0.30% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 69 0.08% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 144 0.16% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 21 0.02% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 417 0.46% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 79 0.09% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 77 0.09% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 154 0.17% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 203 0.23% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 82 0.09% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45504-45511 1 0.00% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 88 0.10% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 135 0.15% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 2 0.00% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 348 0.39% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 145 0.16% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 73 0.08% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 84 0.09% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 268 0.30% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 92 0.10% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47680-47687 1 0.00% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 19 0.02% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48064-48071 1 0.00% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 511 0.57% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 2 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 2 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 90 0.10% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 140 0.16% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 6 0.01% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 6 0.01% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5078 5.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89706 # Bytes accessed per row activation -system.physmem.totQLat 373696644500 # Total ticks spent queuing -system.physmem.totMemAccLat 469604897000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77464855000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18443397500 # Total ticks spent accessing banks -system.physmem.avgQLat 24120.40 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1190.44 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 977394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1014.625651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1002.644045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 87.222028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3543 0.36% 0.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 3286 0.34% 0.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1787 0.18% 0.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1165 0.12% 1.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 902 0.09% 1.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 711 0.07% 1.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 580 0.06% 1.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 432 0.04% 1.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 964988 98.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 977394 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4784 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3238.435619 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 134294.504205 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 4779 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.06% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8.9129e+06-9.43718e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4784 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4784 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.015886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.524536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.242033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2224 46.49% 46.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 36 0.75% 47.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 227 4.74% 51.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1224 25.59% 77.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 8 0.17% 77.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.08% 77.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 77.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 77.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.02% 77.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 945 19.75% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 67 1.40% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 15 0.31% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 31 0.65% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4784 # Writes before turning the bus around for reads +system.physmem.totQLat 588095657500 # Total ticks spent queuing +system.physmem.totMemAccLat 694960871250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77463410000 # Total ticks spent in databus transfers +system.physmem.totBankLat 29401803750 # Total ticks spent accessing banks +system.physmem.avgQLat 37959.58 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1897.79 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30310.84 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44857.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 378.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.98 # Data bus utilization in percentage system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.55 # Average write queue length when enqueuing -system.physmem.readRowHits 15419069 # Number of row buffer hits during reads -system.physmem.writeRowHits 91147 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.21 # Row buffer hit rate for writes -system.physmem.avgGap 160459.07 # Average gap between requests -system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54116372 # Throughput (bytes/s) +system.physmem.avgRdQLen 7.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 29.46 # Average write queue length when enqueuing +system.physmem.readRowHits 14490606 # Number of row buffer hits during reads +system.physmem.writeRowHits 90101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.53 # Row buffer hit rate for writes +system.physmem.avgGap 160458.12 # Average gap between requests +system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 3.85 # Percentage of time for which DRAM has all the banks in precharge state +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54116651 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16546597 # Transaction distribution system.membus.trans_dist::ReadResp 16546597 # Transaction distribution system.membus.trans_dist::WriteReq 763385 # Transaction distribution system.membus.trans_dist::WriteResp 763385 # Transaction distribution -system.membus.trans_dist::Writeback 57911 # Transaction distribution +system.membus.trans_dist::Writeback 57910 # Transaction distribution system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution -system.membus.trans_dist::ReadExReq 132218 # Transaction distribution -system.membus.trans_dist::ReadExResp 132218 # Transaction distribution +system.membus.trans_dist::ReadExReq 132217 # Transaction distribution +system.membus.trans_dist::ReadExResp 132217 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383088 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893543 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280490 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951341 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34951338 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390542 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914914 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516520 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914786 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141598306 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141598306 # Total data (bytes) +system.membus.tot_pkt_size::total 141598178 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141598178 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206226000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206225000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17910626500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17911294000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4950468826 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4951349139 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34635984750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 38238689000 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47801049 # Throughput (bytes/s) +system.iobus.throughput 47801339 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16518785 # Transaction distribution system.iobus.trans_dist::ReadResp 16518785 # Transaction distribution system.iobus.trans_dist::WriteReq 8183 # Transaction distribution @@ -822,8 +445,8 @@ system.iobus.reqLayer25.occupancy 15335424000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374905000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42035727250 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.iobus.respLayer1.occupancy 38265059000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -848,25 +471,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996193 # DTB read hits -system.cpu.dtb.read_misses 7334 # DTB read misses -system.cpu.dtb.write_hits 11230326 # DTB write hits -system.cpu.dtb.write_misses 2212 # DTB write misses +system.cpu.dtb.read_hits 14996179 # DTB read hits +system.cpu.dtb.read_misses 7337 # DTB read misses +system.cpu.dtb.write_hits 11230334 # DTB write hits +system.cpu.dtb.write_misses 2213 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3411 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003527 # DTB read accesses -system.cpu.dtb.write_accesses 11232538 # DTB write accesses +system.cpu.dtb.read_accesses 15003516 # DTB read accesses +system.cpu.dtb.write_accesses 11232547 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226519 # DTB hits -system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 26236065 # DTB accesses +system.cpu.dtb.hits 26226513 # DTB hits +system.cpu.dtb.misses 9550 # DTB misses +system.cpu.dtb.accesses 26236063 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -888,7 +511,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61494253 # ITB inst hits +system.cpu.itb.inst_hits 61493932 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -905,88 +528,88 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61498724 # ITB inst accesses -system.cpu.itb.hits 61494253 # DTB hits +system.cpu.itb.inst_accesses 61498403 # ITB inst accesses +system.cpu.itb.hits 61493932 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61498724 # DTB accesses -system.cpu.numCycles 5233104166 # number of cpu cycles simulated +system.cpu.itb.accesses 61498403 # DTB accesses +system.cpu.numCycles 5233072430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60200379 # Number of instructions committed -system.cpu.committedOps 76607188 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69208982 # Number of integer alu accesses +system.cpu.committedInsts 60200059 # Number of instructions committed +system.cpu.committedOps 76606878 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69208659 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140473 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948700 # number of instructions that are conditional controls -system.cpu.num_int_insts 69208982 # number of integer instructions +system.cpu.num_func_calls 2140468 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948676 # number of instructions that are conditional controls +system.cpu.num_int_insts 69208659 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 401369988 # number of times the integer registers were read -system.cpu.num_int_register_writes 74519463 # number of times the integer registers were written +system.cpu.num_int_register_reads 401368432 # number of times the integer registers were read +system.cpu.num_int_register_writes 74518953 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394064 # number of memory refs -system.cpu.num_load_insts 15660288 # Number of load instructions -system.cpu.num_store_insts 11733776 # Number of store instructions -system.cpu.num_idle_cycles 4581523252.608249 # Number of idle cycles -system.cpu.num_busy_cycles 651580913.391751 # Number of busy cycles -system.cpu.not_idle_fraction 0.124511 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875489 # Percentage of idle cycles -system.cpu.Branches 10308817 # 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Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19998571250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.867590 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997788 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997788 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 856277 # number of replacements +system.cpu.icache.tags.tagsinuse 510.865256 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60637143 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856789 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.772551 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20019652250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.865256 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997784 # 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11774299750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11774299750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61494253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61494253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61494253 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61494253 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61494253 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61494253 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 62350721 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62350721 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60637143 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60637143 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11768796500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11768796500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11768796500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61493932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61493932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61493932 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61493932 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61493932 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61493932 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13735.933234 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13735.933234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13735.933234 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -995,186 +618,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 351469750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664489250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167015959000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706272596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706272596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 351469750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370761846 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183722231596 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025849 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991138 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991138 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541335 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541335 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991129 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58593.930090 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62701.498624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60566.810450 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59379.438498 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59379.438498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58065.800661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62844.046284 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58957.810786 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58896.901730 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1278,86 +901,87 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626146 # 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.747333 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 671680250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.875243 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999756 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999756 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # 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number of overall hits +system.cpu.dcache.overall_hits::total 23168959 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368088 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368088 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250156 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250156 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11382 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11382 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 618244 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618244 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618244 # number of overall misses +system.cpu.dcache.overall_misses::total 618244 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5418733500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5418733500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11526229765 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11526229765 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157891250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 157891250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16944963265 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16944963265 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16944963265 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16944963265 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564293 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564293 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222910 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222910 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787209 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787209 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787209 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787209 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027134 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027134 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14716.679934 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14716.679934 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46464.899699 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46464.899699 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13908.484103 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13908.484103 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27563.080535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27563.080535 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 23787203 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787203 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787203 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787203 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027137 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027137 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045936 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045936 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025991 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025991 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025991 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025991 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14721.298983 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14721.298983 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46076.167531 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46076.167531 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13872.012827 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13872.012827 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27408.213044 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27408.213044 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1366,54 +990,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595238 # number of writebacks -system.cpu.dcache.writebacks::total 595238 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250147 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250147 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618206 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618206 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618206 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618206 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678192500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678192500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11070820735 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11070820735 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135536000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135536000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15749013235 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15749013235 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15749013235 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15749013235 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058328250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058328250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26237936841 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26237936841 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208296265091 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208296265091 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027134 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027134 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045952 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12710.441804 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12710.441804 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44257.259671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44257.259671 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11903.741437 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11903.741437 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595273 # number of writebacks +system.cpu.dcache.writebacks::total 595273 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368088 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368088 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250156 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250156 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618244 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618244 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618244 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618244 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4680319500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4680319500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10976351235 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10976351235 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135073750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135073750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15656670735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15656670735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15656670735 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15656670735 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058625250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058625250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242395404 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242395404 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301020654 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301020654 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045936 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045936 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025991 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025991 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12715.218915 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12715.218915 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43878.025052 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43878.025052 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11867.312423 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11867.312423 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1421,37 +1045,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52965248 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454635 # Transaction distribution +system.cpu.toL2Bus.throughput 52967752 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454681 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247213 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749474 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7514534 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755228 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615814 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138420018 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138420018 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3008633500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 595273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247225 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247225 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725204 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27438 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514680 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54756316 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83620422 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138425734 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138425734 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166308 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3008713250 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295454000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295332250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2534439174 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2533285861 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18724250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use @@ -1469,10 +1093,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1538398399250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1538398399250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1763840630000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1763840630000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 64ad0ab7f..03f4934d5 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196390 # Number of seconds simulated -sim_ticks 5196390180000 # Number of ticks simulated -final_tick 5196390180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.200402 # Number of seconds simulated +sim_ticks 5200402495000 # Number of ticks simulated +final_tick 5200402495000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 991078 # Simulator instruction rate (inst/s) -host_op_rate 1910460 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40129605273 # Simulator tick rate (ticks/s) -host_mem_usage 591204 # Number of bytes of host memory used -host_seconds 129.49 # Real time elapsed on the host -sim_insts 128334813 # Number of instructions simulated -sim_ops 247385808 # Number of ops (including micro ops) simulated +host_inst_rate 1256922 # Simulator instruction rate (inst/s) +host_op_rate 2423033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50949381192 # Simulator tick rate (ticks/s) +host_mem_usage 591984 # Number of bytes of host memory used +host_seconds 102.07 # Real time elapsed on the host +sim_insts 128294014 # Number of instructions simulated +sim_ops 247318948 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2883712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 2869888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8989184 # Number of bytes read from this memory -system.physmem.bytes_read::total 12697856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8110912 # Number of bytes written to this memory -system.physmem.bytes_written::total 8110912 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45058 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 826752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8970624 # Number of bytes read from this memory +system.physmem.bytes_read::total 12667648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 826752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 826752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8094016 # Number of bytes written to this memory +system.physmem.bytes_written::total 8094016 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44842 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140456 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198404 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126733 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126733 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 554945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12918 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140166 # Number of read requests responded to by this memory +system.physmem.num_reads::total 197932 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126469 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126469 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 551859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1729890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2443592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560874 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1560874 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 554945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1724986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2435898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1556421 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1556421 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1556421 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 551859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1729890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4004466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198404 # Number of read requests accepted -system.physmem.writeReqs 126733 # Number of write requests accepted -system.physmem.readBursts 198404 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 126733 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12694144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue -system.physmem.bytesWritten 8109888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12697856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8110912 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 158978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1724986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3992319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197932 # Number of read requests accepted +system.physmem.writeReqs 126469 # Number of write requests accepted +system.physmem.readBursts 197932 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 126469 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12654528 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 13120 # Total number of bytes read from write queue +system.physmem.bytesWritten 8092032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12667648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8094016 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 205 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1616 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12580 # Per bank write bursts -system.physmem.perBankRdBursts::1 12146 # Per bank write bursts -system.physmem.perBankRdBursts::2 12820 # Per bank write bursts -system.physmem.perBankRdBursts::3 12639 # Per bank write bursts -system.physmem.perBankRdBursts::4 12420 # Per bank write bursts -system.physmem.perBankRdBursts::5 12033 # Per bank write bursts -system.physmem.perBankRdBursts::6 12032 # Per bank write bursts -system.physmem.perBankRdBursts::7 12154 # Per bank write bursts -system.physmem.perBankRdBursts::8 12328 # Per bank write bursts -system.physmem.perBankRdBursts::9 11842 # Per bank write bursts -system.physmem.perBankRdBursts::10 12289 # Per bank write bursts -system.physmem.perBankRdBursts::11 12385 # Per bank write bursts -system.physmem.perBankRdBursts::12 12618 # Per bank write bursts -system.physmem.perBankRdBursts::13 13039 # Per bank write bursts -system.physmem.perBankRdBursts::14 12508 # Per bank write bursts -system.physmem.perBankRdBursts::15 12513 # Per bank write bursts -system.physmem.perBankWrBursts::0 8180 # Per bank write bursts -system.physmem.perBankWrBursts::1 7837 # Per bank write bursts -system.physmem.perBankWrBursts::2 8283 # Per bank write bursts -system.physmem.perBankWrBursts::3 8150 # Per bank write bursts -system.physmem.perBankWrBursts::4 7961 # Per bank write bursts -system.physmem.perBankWrBursts::5 7589 # Per bank write bursts -system.physmem.perBankWrBursts::6 7480 # Per bank write bursts -system.physmem.perBankWrBursts::7 7728 # Per bank write bursts -system.physmem.perBankWrBursts::8 7696 # Per bank write bursts -system.physmem.perBankWrBursts::9 7447 # Per bank write bursts -system.physmem.perBankWrBursts::10 7846 # Per bank write bursts -system.physmem.perBankWrBursts::11 7788 # Per bank write bursts -system.physmem.perBankWrBursts::12 8080 # Per bank write bursts -system.physmem.perBankWrBursts::13 8539 # Per bank write bursts -system.physmem.perBankWrBursts::14 8032 # Per bank write bursts -system.physmem.perBankWrBursts::15 8081 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1622 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12706 # Per bank write bursts +system.physmem.perBankRdBursts::1 12058 # Per bank write bursts +system.physmem.perBankRdBursts::2 12568 # Per bank write bursts +system.physmem.perBankRdBursts::3 12134 # Per bank write bursts +system.physmem.perBankRdBursts::4 12521 # Per bank write bursts +system.physmem.perBankRdBursts::5 12218 # Per bank write bursts +system.physmem.perBankRdBursts::6 12048 # Per bank write bursts +system.physmem.perBankRdBursts::7 12245 # Per bank write bursts +system.physmem.perBankRdBursts::8 12013 # Per bank write bursts +system.physmem.perBankRdBursts::9 12113 # Per bank write bursts +system.physmem.perBankRdBursts::10 12409 # Per bank write bursts +system.physmem.perBankRdBursts::11 12495 # Per bank write bursts +system.physmem.perBankRdBursts::12 12992 # Per bank write bursts +system.physmem.perBankRdBursts::13 12976 # Per bank write bursts +system.physmem.perBankRdBursts::14 12442 # Per bank write bursts +system.physmem.perBankRdBursts::15 11789 # Per bank write bursts +system.physmem.perBankWrBursts::0 8349 # Per bank write bursts +system.physmem.perBankWrBursts::1 7660 # Per bank write bursts +system.physmem.perBankWrBursts::2 8054 # Per bank write bursts +system.physmem.perBankWrBursts::3 7772 # Per bank write bursts +system.physmem.perBankWrBursts::4 8164 # Per bank write bursts +system.physmem.perBankWrBursts::5 7804 # Per bank write bursts +system.physmem.perBankWrBursts::6 7601 # Per bank write bursts +system.physmem.perBankWrBursts::7 7742 # Per bank write bursts +system.physmem.perBankWrBursts::8 7412 # Per bank write bursts +system.physmem.perBankWrBursts::9 7677 # Per bank write bursts +system.physmem.perBankWrBursts::10 8006 # Per bank write bursts +system.physmem.perBankWrBursts::11 7919 # Per bank write bursts +system.physmem.perBankWrBursts::12 8539 # Per bank write bursts +system.physmem.perBankWrBursts::13 8375 # Per bank write bursts +system.physmem.perBankWrBursts::14 8051 # Per bank write bursts +system.physmem.perBankWrBursts::15 7313 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 5196390116500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 5200402431500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 198404 # Read request sizes (log2) +system.physmem.readPktSize::6 197932 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126733 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 155323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 52 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126469 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 153822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2836 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1775 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -141,215 +141,131 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 20 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 53708 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.265063 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.541838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1283.636288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 22377 41.66% 41.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 8801 16.39% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 5780 10.76% 68.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 3435 6.40% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2322 4.32% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1859 3.46% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1339 2.49% 85.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1034 1.93% 87.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 806 1.50% 88.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 663 1.23% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 546 1.02% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 427 0.80% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 325 0.61% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 307 0.57% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 277 0.52% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 550 1.02% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 185 0.34% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 190 0.35% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 112 0.21% 95.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 109 0.20% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 125 0.23% 96.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 422 0.79% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 149 0.28% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 87 0.16% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 55 0.10% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 85 0.16% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 52 0.10% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 36 0.07% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 25 0.05% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 24 0.04% 97.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 18 0.03% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 26 0.05% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 25 0.05% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 20 0.04% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 13 0.02% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.02% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 14 0.03% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 11 0.02% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 14 0.03% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 11 0.02% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 9 0.02% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 10 0.02% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 13 0.02% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 26 0.05% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 12 0.02% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 9 0.02% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 19 0.04% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 10 0.02% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 9 0.02% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 12 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 12 0.02% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 15 0.03% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 10 0.02% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 20 0.04% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 13 0.02% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 24 0.04% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 13 0.02% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 11 0.02% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 19 0.04% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 10 0.02% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 13 0.02% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 7 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 9 0.02% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 11 0.02% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 7 0.01% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 9 0.02% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 9 0.02% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 10 0.02% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 9 0.02% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 7 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 9 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 7 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 5 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 13 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 8 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 7 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 8 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 10 0.02% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 5 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 9 0.02% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 151 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 2 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 2 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 2 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 4 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 2 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 19 0.04% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 4 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 14 0.03% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 4 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 4 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 6 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 3 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 7 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 32 0.06% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 3 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 178 0.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 53708 # Bytes accessed per row activation -system.physmem.totQLat 5080719250 # Total ticks spent queuing -system.physmem.totMemAccLat 8752324250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 991730000 # Total ticks spent in databus transfers -system.physmem.totBankLat 2679875000 # Total ticks spent accessing banks -system.physmem.avgQLat 25615.44 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13511.11 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 36378 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 449.321238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 264.022911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 400.116091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 9783 26.89% 26.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7520 20.67% 47.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3398 9.34% 56.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1958 5.38% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1470 4.04% 66.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 950 2.61% 68.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 669 1.84% 70.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 516 1.42% 72.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10114 27.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 36378 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6806 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.049956 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 579.203336 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6805 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6806 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6806 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.577432 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.979234 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.072144 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 4358 64.03% 64.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1673 24.58% 88.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 85 1.25% 89.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 45 0.66% 90.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 78 1.15% 91.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 127 1.87% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 53 0.78% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 38 0.56% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 25 0.37% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 74 1.09% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 52 0.76% 97.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 16 0.24% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 72 1.06% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 19 0.28% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 28 0.41% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 13 0.19% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 8 0.12% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 5 0.07% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 7 0.10% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 5 0.07% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 5 0.07% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 13 0.19% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::74-75 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6806 # Writes before turning the bus around for reads +system.physmem.totQLat 5807464000 # Total ticks spent queuing +system.physmem.totMemAccLat 9465482750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 988635000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2669383750 # Total ticks spent accessing banks +system.physmem.avgQLat 29371.12 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13500.35 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44126.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47871.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.43 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s @@ -357,99 +273,99 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.98 # Average write queue length when enqueuing -system.physmem.readRowHits 173438 # Number of row buffer hits during reads -system.physmem.writeRowHits 97917 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.26 # Row buffer hit rate for writes -system.physmem.avgGap 15982155.57 # Average gap between requests -system.physmem.pageHitRate 83.47 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.27 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 4365247 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 623514 # Transaction distribution -system.membus.trans_dist::ReadResp 623514 # Transaction distribution -system.membus.trans_dist::WriteReq 13775 # Transaction distribution -system.membus.trans_dist::WriteResp 13775 # Transaction distribution -system.membus.trans_dist::Writeback 126733 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1634 # Transaction distribution -system.membus.trans_dist::ReadExReq 159484 # Transaction distribution -system.membus.trans_dist::ReadExResp 159484 # Transaction distribution -system.membus.trans_dist::MessageReq 1655 # Transaction distribution -system.membus.trans_dist::MessageResp 1655 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.17 # Average write queue length when enqueuing +system.physmem.readRowHits 167067 # Number of row buffer hits during reads +system.physmem.writeRowHits 99118 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.37 # Row buffer hit rate for writes +system.physmem.avgGap 16030784.22 # Average gap between requests +system.physmem.pageHitRate 82.11 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.28 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 4355532 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 623246 # Transaction distribution +system.membus.trans_dist::ReadResp 623246 # Transaction distribution +system.membus.trans_dist::WriteReq 13777 # Transaction distribution +system.membus.trans_dist::WriteResp 13777 # Transaction distribution +system.membus.trans_dist::Writeback 126469 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2149 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1640 # Transaction distribution +system.membus.trans_dist::ReadExReq 159500 # Transaction distribution +system.membus.trans_dist::ReadExResp 159500 # Transaction distribution +system.membus.trans_dist::MessageReq 1656 # Transaction distribution +system.membus.trans_dist::MessageResp 1656 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391174 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139281 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 139281 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1724207 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 139069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1723230 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14938368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16605037 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5870400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5870400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22482057 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22482057 # Total data (bytes) -system.membus.snoop_data_through_bus 201472 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 256796500 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420233 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14905088 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16571765 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5856576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5856576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22434965 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22434965 # Total data (bytes) +system.membus.snoop_data_through_bus 215552 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 256796000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 359316000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 359324000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3312000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1352149000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1349763000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2612327754 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2610332746 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 428873750 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429200500 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47501 # number of replacements -system.iocache.tags.tagsinuse 0.113099 # Cycle average of tags in use +system.iocache.tags.replacements 47505 # number of replacements +system.iocache.tags.tagsinuse 0.134382 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47521 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5049776837000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.113099 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007069 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007069 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5049788540000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.134382 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008399 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.008399 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428004 # Number of tag accesses -system.iocache.tags.data_accesses 428004 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses -system.iocache.ReadReq_misses::total 836 # number of ReadReq misses +system.iocache.tags.tag_accesses 428040 # Number of tag accesses +system.iocache.tags.data_accesses 428040 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 840 # number of ReadReq misses +system.iocache.ReadReq_misses::total 840 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses -system.iocache.demand_misses::total 47556 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses -system.iocache.overall_misses::total 47556 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144134686 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144134686 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12487439330 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12487439330 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 12631574016 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12631574016 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 12631574016 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12631574016 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47560 # number of demand (read+write) misses +system.iocache.demand_misses::total 47560 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47560 # number of overall misses +system.iocache.overall_misses::total 47560 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142383686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 142383686 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12484793248 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12484793248 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 12627176934 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12627176934 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 12627176934 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12627176934 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 840 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 840 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47560 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47560 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47560 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47560 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -458,40 +374,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 172409.911483 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 172409.911483 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267282.519906 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 267282.519906 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 265614.728236 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 265614.728236 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 216457 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169504.388095 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 169504.388095 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267225.882877 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 267225.882877 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265499.935534 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 265499.935534 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265499.935534 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 265499.935534 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 224342 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11594 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 18183 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 18.669743 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.338008 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 840 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 840 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100637686 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100637686 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 10056284830 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10056284830 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10156922516 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10156922516 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47560 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47560 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47560 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47560 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98678186 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 98678186 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 10053057748 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10053057748 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10151735934 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10151735934 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10151735934 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10151735934 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -500,14 +416,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120380.007177 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 120380.007177 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215245.822560 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 215245.822560 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117474.030952 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117474.030952 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215176.749743 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 215176.749743 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 213451.134020 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 213451.134020 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -521,13 +437,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 631264 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 230141 # Transaction distribution -system.iobus.trans_dist::ReadResp 230141 # Transaction distribution +system.iobus.throughput 630784 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 230145 # Transaction distribution +system.iobus.trans_dist::ReadResp 230145 # Transaction distribution system.iobus.trans_dist::WriteReq 57579 # Transaction distribution system.iobus.trans_dist::WriteResp 57579 # Transaction distribution -system.iobus.trans_dist::MessageReq 1655 # Transaction distribution -system.iobus.trans_dist::MessageResp 1655 # Transaction distribution +system.iobus.trans_dist::MessageReq 1656 # Transaction distribution +system.iobus.trans_dist::MessageResp 1656 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -547,11 +463,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 578760 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -571,13 +487,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3280296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3280296 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3948164 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3280332 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3280332 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3953400 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -613,98 +529,98 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424033266 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 425604434 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52989250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53343500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10392780360 # number of cpu cycles simulated +system.cpu.numCycles 10400804990 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128334813 # Number of instructions committed -system.cpu.committedOps 247385808 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231978567 # Number of integer alu accesses +system.cpu.committedInsts 128294014 # Number of instructions committed +system.cpu.committedOps 247318948 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231911784 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2299773 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23169265 # number of instructions that are conditional controls -system.cpu.num_int_insts 231978567 # number of integer instructions +system.cpu.num_func_calls 2299833 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23159249 # number of instructions that are conditional controls +system.cpu.num_int_insts 231911784 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434513747 # number of times the integer registers were read -system.cpu.num_int_register_writes 197852200 # number of times the integer registers were written +system.cpu.num_int_register_reads 434400113 # number of times the integer registers were read +system.cpu.num_int_register_writes 197801183 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132813019 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95534921 # number of times the CC registers were written -system.cpu.num_mem_refs 22245363 # number of memory refs -system.cpu.num_load_insts 13878746 # Number of load instructions -system.cpu.num_store_insts 8366617 # Number of store instructions -system.cpu.num_idle_cycles 9785238216.998117 # Number of idle cycles -system.cpu.num_busy_cycles 607542143.001883 # Number of busy cycles -system.cpu.not_idle_fraction 0.058458 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941542 # Percentage of idle cycles -system.cpu.Branches 26307103 # Number of branches fetched +system.cpu.num_cc_register_reads 132752064 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95494911 # number of times the CC registers were written +system.cpu.num_mem_refs 22235692 # number of memory refs +system.cpu.num_load_insts 13875118 # Number of load instructions +system.cpu.num_store_insts 8360574 # Number of store instructions +system.cpu.num_idle_cycles 9794078774.998117 # Number of idle cycles +system.cpu.num_busy_cycles 606726215.001883 # Number of busy cycles +system.cpu.not_idle_fraction 0.058335 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941665 # Percentage of idle cycles +system.cpu.Branches 26297154 # Number of branches fetched system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 788090 # number of replacements -system.cpu.icache.tags.tagsinuse 510.351939 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144584753 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 788602 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 183.343122 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161436066250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.351939 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996781 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996781 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 791422 # number of replacements +system.cpu.icache.tags.tagsinuse 510.352385 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144521518 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791934 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.491872 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161455178250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.352385 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996782 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996782 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146161971 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146161971 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144584753 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144584753 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144584753 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144584753 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144584753 # number of overall hits -system.cpu.icache.overall_hits::total 144584753 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 788609 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 788609 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 788609 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 788609 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 788609 # number of overall misses -system.cpu.icache.overall_misses::total 788609 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11107362758 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11107362758 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11107362758 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11107362758 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11107362758 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11107362758 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145373362 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145373362 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145373362 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145373362 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145373362 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145373362 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005425 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005425 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005425 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005425 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005425 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005425 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14084.752720 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14084.752720 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14084.752720 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14084.752720 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146105400 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146105400 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144521518 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144521518 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144521518 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144521518 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144521518 # number of overall hits +system.cpu.icache.overall_hits::total 144521518 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791941 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791941 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791941 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791941 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791941 # number of overall misses +system.cpu.icache.overall_misses::total 791941 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11119349759 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11119349759 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11119349759 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11119349759 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11119349759 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11119349759 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145313459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145313459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145313459 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145313459 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145313459 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145313459 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14040.628985 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14040.628985 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14040.628985 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14040.628985 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14040.628985 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14040.628985 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -713,88 +629,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788609 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 788609 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 788609 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 788609 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 788609 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 788609 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9525299242 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9525299242 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9525299242 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9525299242 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9525299242 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9525299242 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005425 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005425 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005425 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12078.608337 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12078.608337 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791941 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791941 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791941 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791941 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791941 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791941 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9530763241 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9530763241 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9530763241 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9530763241 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9530763241 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9530763241 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12034.688494 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12034.688494 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12034.688494 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12034.688494 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12034.688494 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12034.688494 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3741 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.069761 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7617 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3752 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.030117 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5169682535000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069761 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191860 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191860 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3448 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.074851 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7916 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3460 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.287861 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5178780288000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.074851 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192178 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.192178 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29050 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29050 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7617 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7617 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 28763 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 28763 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7916 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7916 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7619 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7619 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7619 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7619 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4604 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4604 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4604 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4604 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4604 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4604 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 44886750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 44886750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7918 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7918 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7918 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7918 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4309 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4309 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4309 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4309 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4309 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4309 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42842750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42842750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42842750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 42842750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42842750 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 42842750 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376729 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376729 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376667 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.376667 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376667 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.376667 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9749.511295 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9749.511295 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9749.511295 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352474 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352474 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352417 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.352417 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352417 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.352417 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9942.620097 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9942.620097 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9942.620097 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9942.620097 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9942.620097 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9942.620097 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -803,86 +719,86 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 621 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 621 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4604 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4604 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4604 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4604 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4604 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4604 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35677750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35677750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35677750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35677750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35677750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35677750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376729 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376729 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376667 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376667 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7749.294092 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 776 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 776 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4309 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4309 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4309 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4309 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4309 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4309 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34223750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34223750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34223750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34223750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34223750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34223750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352474 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352474 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352417 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352417 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352417 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352417 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7942.388025 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7942.388025 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7942.388025 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7942.388025 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7942.388025 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7942.388025 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7948 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.052475 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12793 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7961 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.606959 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5168018375000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052475 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315780 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315780 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 8116 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.061830 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12619 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 8130 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.552153 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5165732872000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061830 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316364 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316364 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53026 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53026 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12806 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12806 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12806 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12806 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12806 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12806 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9138 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9138 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9138 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9138 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9138 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9138 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97347500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97347500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97347500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 97347500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97347500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 97347500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21944 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21944 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21944 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21944 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21944 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21944 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.416424 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.416424 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.416424 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.416424 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.416424 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.416424 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10653.042241 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10653.042241 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10653.042241 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53134 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53134 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12626 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12626 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12626 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12626 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12626 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12626 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9294 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9294 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9294 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9294 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9294 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9294 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 98603000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 98603000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 98603000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 98603000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 98603000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 98603000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21920 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21920 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21920 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21920 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21920 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21920 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.423996 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.423996 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.423996 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.423996 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.423996 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.423996 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10609.317839 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10609.317839 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10609.317839 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10609.317839 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10609.317839 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10609.317839 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -891,98 +807,98 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9138 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9138 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9138 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9138 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9138 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9138 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 79071000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 79071000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 79071000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 79071000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 79071000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 79071000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.416424 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.416424 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.416424 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8652.987525 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3085 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3085 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9294 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9294 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9294 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9294 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9294 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9294 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 80015000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 80015000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 80015000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 80015000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 80015000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 80015000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.423996 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.423996 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.423996 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.423996 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.423996 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.423996 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8609.317839 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8609.317839 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8609.317839 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8609.317839 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8609.317839 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8609.317839 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1621547 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997026 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20035701 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622059 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.352017 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 50992250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997026 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1620672 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997242 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20026945 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1621184 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.353283 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 51279250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997242 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88253354 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88253354 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11993197 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11993197 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8040328 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8040328 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20033525 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20033525 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20033525 # number of overall hits -system.cpu.dcache.overall_hits::total 20033525 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308312 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308312 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315974 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315974 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624286 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624286 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624286 # number of overall misses -system.cpu.dcache.overall_misses::total 1624286 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18913909300 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18913909300 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11002078938 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11002078938 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29915988238 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29915988238 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29915988238 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29915988238 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13301509 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13301509 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8356302 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8356302 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21657811 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21657811 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21657811 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21657811 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098358 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098358 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074998 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074998 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074998 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074998 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14456.726912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14456.726912 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34819.570401 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34819.570401 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18417.931471 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18417.931471 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 88213750 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88213750 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11989262 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11989262 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035472 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035472 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20024734 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20024734 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20024734 # number of overall hits +system.cpu.dcache.overall_hits::total 20024734 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308613 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308613 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314792 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314792 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623405 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623405 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623405 # number of overall misses +system.cpu.dcache.overall_misses::total 1623405 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18824282553 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18824282553 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10745506942 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10745506942 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29569789495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29569789495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29569789495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29569789495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13297875 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13297875 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8350264 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350264 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21648139 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21648139 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21648139 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21648139 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098408 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098408 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037698 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037698 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074991 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074991 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074991 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074991 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14384.911775 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14384.911775 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34135.260559 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34135.260559 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18214.671936 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18214.671936 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18214.671936 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18214.671936 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -991,46 +907,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538973 # number of writebacks -system.cpu.dcache.writebacks::total 1538973 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308312 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1308312 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315974 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315974 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1624286 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1624286 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1624286 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1624286 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16288101700 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16288101700 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10316379062 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10316379062 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26604480762 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26604480762 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26604480762 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26604480762 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214673000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214673000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537491500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537491500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752164500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752164500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098358 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098358 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12449.707486 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12449.707486 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32649.455531 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32649.455531 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1537729 # number of writebacks +system.cpu.dcache.writebacks::total 1537729 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308613 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308613 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314792 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314792 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1623405 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1623405 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1623405 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1623405 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16198393447 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16198393447 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10064156058 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10064156058 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26262549505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26262549505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26262549505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26262549505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537739500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537739500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752412000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752412000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098408 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098408 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037698 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037698 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074991 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12378.291708 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12378.291708 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31970.812657 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31970.812657 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16177.447713 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16177.447713 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16177.447713 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16177.447713 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1038,184 +954,184 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 49185341 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2692945 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2692419 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1542700 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 360518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313820 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5977035 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8133 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18986 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7581359 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50470144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203948077 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 225856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 630272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 255274349 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 255253101 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 333120 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3831866500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 49161645 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2696443 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2695917 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13777 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13777 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1541590 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 359301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 312590 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583869 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5973994 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19197 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7584957 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203806901 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 229632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 633792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 255353717 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 255333045 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 327296 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3831359500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 498000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 484500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1185336258 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1190263759 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3054054238 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3051445995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6906500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6464000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13707250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13941000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 86910 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64731.196890 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3488433 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151626 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.006826 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 86417 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64729.830083 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3490254 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151212 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.081859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50120.476905 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.033461 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141258 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3445.447212 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.098054 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.764778 # 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