diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/quick/fs | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/quick/fs')
13 files changed, 8552 insertions, 8461 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index a85398f56..59ee1a74c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2452265 # Simulator instruction rate (inst/s) -host_op_rate 2452264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70524991939 # Simulator tick rate (ticks/s) -host_mem_usage 374768 # Number of bytes of host memory used -host_seconds 26.51 # Real time elapsed on the host +host_inst_rate 2397277 # Simulator instruction rate (inst/s) +host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68943602925 # Simulator tick rate (ticks/s) +host_mem_usage 377676 # Number of bytes of host memory used +host_seconds 27.11 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 763584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68173952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 763584 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 869824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065218 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 408474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36469170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 408474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465306 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 408474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40660828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -737,20 +737,20 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999684 # number of replacements +system.l2c.tags.replacements 999687 # number of replacements system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use -system.l2c.tags.total_refs 4588619 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064734 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.309639 # Average number of references to valid blocks. +system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55911.037805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4939.570238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.759225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.853135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy @@ -761,8 +761,8 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 # system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 49101323 # Number of tag accesses -system.l2c.tags.data_accesses 49101323 # Number of data accesses +system.l2c.tags.tag_accesses 46365678 # Number of tag accesses +system.l2c.tags.data_accesses 46365678 # Number of data accesses system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits system.l2c.Writeback_hits::total 777520 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits @@ -774,22 +774,22 @@ system.l2c.SCUpgradeReq_hits::total 50 # nu system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 606993 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986545 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 606993 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910322 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606993 # number of overall hits +system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits system.l2c.overall_hits::cpu0.data 738161 # number of overall hits system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910322 # number of overall hits +system.l2c.overall_hits::total 1910319 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses @@ -799,22 +799,22 @@ system.l2c.SCUpgradeReq_misses::total 2285 # nu system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11931 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13591 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11931 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066177 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11931 # number of overall misses +system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses system.l2c.overall_misses::cpu1.data 12102 # number of overall misses -system.l2c.overall_misses::total 1066177 # number of overall misses +system.l2c.overall_misses::total 1066180 # number of overall misses system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) @@ -851,22 +851,22 @@ system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # mi system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019277 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013589 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358198 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019277 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358198 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -879,49 +879,55 @@ system.l2c.writebacks::writebacks 80913 # nu system.l2c.writebacks::total 80913 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948863 # Transaction distribution +system.membus.trans_dist::ReadResp 948866 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution system.membus.trans_dist::Writeback 122433 # Transaction distribution -system.membus.trans_dist::CleanEvict 922490 # Transaction distribution +system.membus.trans_dist::CleanEvict 917961 # Transaction distribution system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution system.membus.trans_dist::ReadExReq 126472 # Transaction distribution system.membus.trans_dist::ReadExResp 124247 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941414 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3178369 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3222443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3347604 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369280 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73455442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76124178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2210194 # Request fanout histogram +system.membus.snoop_fanout::samples 2205834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2210194 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2210194 # Request fanout histogram +system.membus.snoop_fanout::total 2205834 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2204578 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution @@ -929,30 +935,30 @@ system.toL2Bus.trans_dist::ReadExReq 295246 # Tr system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450155 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143095 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1705094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5410979 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41895 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 6099689 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.006841 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.082430 # Request fanout histogram +system.toL2Bus.snoops 1083281 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 6057958 99.32% 99.32% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41731 0.68% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 6099689 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 60a4f6e98..34e6d6348 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2495393 # Simulator instruction rate (inst/s) -host_op_rate 2495392 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76033049021 # Simulator tick rate (ticks/s) -host_mem_usage 371696 # Number of bytes of host memory used -host_seconds 24.06 # Real time elapsed on the host +host_inst_rate 2390951 # Simulator instruction rate (inst/s) +host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72850763127 # Simulator tick rate (ticks/s) +host_mem_usage 374092 # Number of bytes of host memory used +host_seconds 25.11 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -338,9 +338,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 992219 # number of replacements system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4561879 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.314315 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor @@ -356,8 +356,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48768396 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48768396 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits @@ -429,36 +429,42 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks system.cpu.l2cache.writebacks::total 74334 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2128840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163286 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8923355 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5984570 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.006972 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.083208 # Request fanout histogram +system.cpu.toL2Bus.snoops 1075788 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5942844 99.30% 99.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 0.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5984570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -561,7 +567,7 @@ system.membus.trans_dist::ReadResp 948374 # Tr system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution system.membus.trans_dist::Writeback 115846 # Transaction distribution -system.membus.trans_dist::CleanEvict 918371 # Transaction distribution +system.membus.trans_dist::CleanEvict 917156 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution system.membus.trans_dist::ReadExReq 116946 # Transaction distribution @@ -570,11 +576,11 @@ system.membus.trans_dist::ReadSharedReq 941190 # Tr system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3108719 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3142763 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3267901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) @@ -582,17 +588,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2151059 # Request fanout histogram +system.membus.snoop_fanout::samples 2150005 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2151059 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2151059 # Request fanout histogram +system.membus.snoop_fanout::total 2150005 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 67605a567..69fe46592 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962608 # Number of seconds simulated -sim_ticks 1962608482500 # Number of ticks simulated -final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.982585 # Number of seconds simulated +sim_ticks 1982585357000 # Number of ticks simulated +final_tick 1982585357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019388 # Simulator instruction rate (inst/s) -host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32859851956 # Simulator tick rate (ticks/s) -host_mem_usage 375280 # Number of bytes of host memory used -host_seconds 59.73 # Real time elapsed on the host -sim_insts 60884587 # Number of instructions simulated -sim_ops 60884587 # Number of ops (including micro ops) simulated +host_inst_rate 1043358 # Simulator instruction rate (inst/s) +host_op_rate 1043358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33918612914 # Simulator tick rate (ticks/s) +host_mem_usage 377952 # Number of bytes of host memory used +host_seconds 58.45 # Real time elapsed on the host +sim_insts 60985541 # Number of instructions simulated +sim_ops 60985541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 804544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24689088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 59456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 522432 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory -system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26076480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 804544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 59456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7738240 # Number of bytes written to this memory +system.physmem.bytes_written::total 7738240 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12571 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8163 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406729 # Number of read requests accepted -system.physmem.writeReqs 120393 # Number of write requests accepted -system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 407445 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120910 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120910 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 405805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12452976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13152765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29989 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 435795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3903106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3903106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3903106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 405805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12452976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17055871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407445 # Number of read requests accepted +system.physmem.writeReqs 120910 # Number of write requests accepted +system.physmem.readBursts 407445 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120910 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26068672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue +system.physmem.bytesWritten 7736640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26076480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7738240 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25025 # Per bank write bursts -system.physmem.perBankRdBursts::1 25421 # Per bank write bursts -system.physmem.perBankRdBursts::2 25447 # Per bank write bursts -system.physmem.perBankRdBursts::3 24899 # Per bank write bursts -system.physmem.perBankRdBursts::4 25181 # Per bank write bursts -system.physmem.perBankRdBursts::5 25235 # Per bank write bursts -system.physmem.perBankRdBursts::6 25799 # Per bank write bursts -system.physmem.perBankRdBursts::7 25539 # Per bank write bursts -system.physmem.perBankRdBursts::8 25681 # Per bank write bursts -system.physmem.perBankRdBursts::9 25348 # Per bank write bursts -system.physmem.perBankRdBursts::10 25259 # Per bank write bursts -system.physmem.perBankRdBursts::11 25592 # Per bank write bursts -system.physmem.perBankRdBursts::12 25653 # Per bank write bursts -system.physmem.perBankRdBursts::13 25554 # Per bank write bursts -system.physmem.perBankRdBursts::14 25887 # Per bank write bursts -system.physmem.perBankRdBursts::15 25094 # Per bank write bursts -system.physmem.perBankWrBursts::0 7701 # Per bank write bursts -system.physmem.perBankWrBursts::1 7641 # Per bank write bursts -system.physmem.perBankWrBursts::2 7454 # Per bank write bursts -system.physmem.perBankWrBursts::3 6926 # Per bank write bursts -system.physmem.perBankWrBursts::4 7165 # Per bank write bursts -system.physmem.perBankWrBursts::5 7117 # Per bank write bursts -system.physmem.perBankWrBursts::6 7626 # Per bank write bursts -system.physmem.perBankWrBursts::7 7252 # Per bank write bursts -system.physmem.perBankWrBursts::8 7527 # Per bank write bursts -system.physmem.perBankWrBursts::9 7238 # Per bank write bursts -system.physmem.perBankWrBursts::10 7225 # Per bank write bursts -system.physmem.perBankWrBursts::11 7418 # Per bank write bursts -system.physmem.perBankWrBursts::12 7843 # Per bank write bursts -system.physmem.perBankWrBursts::13 8207 # Per bank write bursts -system.physmem.perBankWrBursts::14 8447 # Per bank write bursts -system.physmem.perBankWrBursts::15 7584 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25232 # Per bank write bursts +system.physmem.perBankRdBursts::1 25377 # Per bank write bursts +system.physmem.perBankRdBursts::2 25433 # Per bank write bursts +system.physmem.perBankRdBursts::3 24853 # Per bank write bursts +system.physmem.perBankRdBursts::4 25156 # Per bank write bursts +system.physmem.perBankRdBursts::5 25421 # Per bank write bursts +system.physmem.perBankRdBursts::6 25501 # Per bank write bursts +system.physmem.perBankRdBursts::7 25341 # Per bank write bursts +system.physmem.perBankRdBursts::8 25248 # Per bank write bursts +system.physmem.perBankRdBursts::9 25578 # Per bank write bursts +system.physmem.perBankRdBursts::10 25745 # Per bank write bursts +system.physmem.perBankRdBursts::11 25922 # Per bank write bursts +system.physmem.perBankRdBursts::12 25991 # Per bank write bursts +system.physmem.perBankRdBursts::13 25558 # Per bank write bursts +system.physmem.perBankRdBursts::14 25312 # Per bank write bursts +system.physmem.perBankRdBursts::15 25655 # Per bank write bursts +system.physmem.perBankWrBursts::0 7850 # Per bank write bursts +system.physmem.perBankWrBursts::1 7774 # Per bank write bursts +system.physmem.perBankWrBursts::2 7467 # Per bank write bursts +system.physmem.perBankWrBursts::3 6887 # Per bank write bursts +system.physmem.perBankWrBursts::4 7102 # Per bank write bursts +system.physmem.perBankWrBursts::5 7345 # Per bank write bursts +system.physmem.perBankWrBursts::6 7434 # Per bank write bursts +system.physmem.perBankWrBursts::7 7145 # Per bank write bursts +system.physmem.perBankWrBursts::8 7156 # Per bank write bursts +system.physmem.perBankWrBursts::9 7306 # Per bank write bursts +system.physmem.perBankWrBursts::10 7741 # Per bank write bursts +system.physmem.perBankWrBursts::11 8153 # Per bank write bursts +system.physmem.perBankWrBursts::12 8257 # Per bank write bursts +system.physmem.perBankWrBursts::13 7909 # Per bank write bursts +system.physmem.perBankWrBursts::14 7539 # Per bank write bursts +system.physmem.perBankWrBursts::15 7820 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 1962561950500 # Total gap between requests +system.physmem.numWrRetry 21 # Number of times write queue was full causing retry +system.physmem.totGap 1982577992500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406729 # Read request sizes (log2) +system.physmem.readPktSize::6 407445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120393 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120910 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,181 +158,177 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 500.345036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 302.441164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.330516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16348 24.20% 24.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12278 18.17% 42.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5298 7.84% 50.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3150 4.66% 54.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2433 3.60% 58.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4298 6.36% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1531 2.27% 67.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2195 3.25% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20033 29.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67564 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5409 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.303198 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2854.593157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5406 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads -system.physmem.totQLat 2204423500 # Total ticks spent queuing -system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5409 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5409 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.348863 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.981514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.757339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4806 88.85% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 190 3.51% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 24 0.44% 92.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 50 0.92% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 37 0.68% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.11% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 18 0.33% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 42 0.78% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 29 0.54% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.06% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 162 3.00% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 4 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.07% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 10 0.18% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::312-319 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5409 # Writes before turning the bus around for reads +system.physmem.totQLat 2792890500 # Total ticks spent queuing +system.physmem.totMemAccLat 10430196750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6856.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25606.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing -system.physmem.readRowHits 363741 # Number of row buffer hits during reads -system.physmem.writeRowHits 96228 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes -system.physmem.avgGap 3723164.56 # Average gap between requests -system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.630269 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states -system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 363877 # Number of row buffer hits during reads +system.physmem.writeRowHits 96767 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes +system.physmem.avgGap 3752359.67 # Average gap between requests +system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 243303480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132754875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578049200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382345920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72929786580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1125575674500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1330334513115 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.011108 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1872213779250 # Time in different power states +system.physmem_0.memoryStateTime::REF 66202760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 44165427000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.683332 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states -system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states +system.physmem_1.actEnergy 267480360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145946625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1599070200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 400988880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74043413820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124598800250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1330548298695 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.118945 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1870589115500 # Time in different power states +system.physmem_1.memoryStateTime::REF 66202760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45790077000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7500026 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 7416955 # DTB read hits +system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5074087 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.read_accesses 490672 # DTB read accesses +system.cpu0.dtb.write_hits 5004564 # DTB write hits +system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12574113 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.write_accesses 187451 # DTB write accesses +system.cpu0.dtb.data_hits 12421519 # DTB hits +system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3504450 # ITB hits +system.cpu0.dtb.data_accesses 678123 # DTB accesses +system.cpu0.itb.fetch_hits 3482641 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3508321 # ITB accesses +system.cpu0.itb.fetch_accesses 3486512 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -345,91 +341,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923838721 # number of cpu cycles simulated +system.cpu0.numCycles 3964851833 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47783493 # Number of instructions committed -system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses -system.cpu0.num_func_calls 1203861 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44315744 # number of integer instructions -system.cpu0.num_fp_insts 211234 # number of float instructions -system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written -system.cpu0.num_mem_refs 12614351 # number of memory refs -system.cpu0.num_load_insts 7527207 # Number of load instructions -system.cpu0.num_store_insts 5087144 # Number of store instructions -system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles -system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles -system.cpu0.Branches 7204257 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction -system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction -system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47325532 # Number of instructions committed +system.cpu0.committedOps 47325532 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43895499 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 207106 # Number of float alu accesses +system.cpu0.num_func_calls 1185742 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5567031 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43895499 # number of integer instructions +system.cpu0.num_fp_insts 207106 # number of float instructions +system.cpu0.num_int_register_reads 60349527 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32725613 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 100583 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 102386 # number of times the floating registers were written +system.cpu0.num_mem_refs 12461430 # number of memory refs +system.cpu0.num_load_insts 7443904 # Number of load instructions +system.cpu0.num_store_insts 5017526 # Number of store instructions +system.cpu0.num_idle_cycles 3700363584.987226 # Number of idle cycles +system.cpu0.num_busy_cycles 264488248.012774 # Number of busy cycles +system.cpu0.not_idle_fraction 0.066708 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.933292 # Percentage of idle cycles +system.cpu0.Branches 7135463 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2703242 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31183402 65.88% 71.59% # Class of executed instruction +system.cpu0.op_class::IntMult 51823 0.11% 71.70% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25571 0.05% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::MemRead 7617030 16.09% 87.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 5023630 10.61% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 727776 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47792093 # Class of executed instruction +system.cpu0.op_class::total 47334130 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6807 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 162813 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55930 40.12% 40.12% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1978 1.42% 41.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80947 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139423 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55420 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1978 1.75% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54986 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 112952 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1904955657000 96.09% 96.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92166000 0.00% 96.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 765642500 0.04% 96.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 319863500 0.02% 96.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 76292557500 3.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1982425886500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990881 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679284 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810139 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -461,124 +457,124 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 523 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3026 2.05% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132550 89.80% 92.24% # number of callpals executed +system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::rti 4327 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 150081 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches +system.cpu0.kern.callpal::total 147613 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6866 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1282 -system.cpu0.kern.mode_good::user 1282 +system.cpu0.kern.mode_good::kernel 1281 +system.cpu0.kern.mode_good::user 1281 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186572 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314472 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1977675856500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3900112000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3073 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1181794 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51530574 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51530574 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6418852 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6418852 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4665452 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4665452 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140662 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140662 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148383 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148383 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11084304 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11084304 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11084304 # number of overall hits -system.cpu0.dcache.overall_hits::total 11084304 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 939259 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 939259 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251797 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251797 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13671 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13671 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5399 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5399 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1191056 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1191056 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1191056 # number of overall misses -system.cpu0.dcache.overall_misses::total 1191056 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 28901225000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 28901225000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10875412500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10875412500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47710000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 47710000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 39776637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 39776637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 39776637500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 39776637500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7358111 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7358111 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4917249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4917249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154333 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154333 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153782 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153782 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12275360 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12275360 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12275360 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12275360 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127649 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127649 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051207 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051207 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035108 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035108 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097028 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097028 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097028 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097028 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # average overall miss latency +system.cpu0.kern.swap_context 3027 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1172695 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.333942 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11237582 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1173114 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.579275 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 143226500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333942 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50910847 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50910847 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6343242 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6343242 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4601243 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4601243 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138155 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138155 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145460 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 145460 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10944485 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10944485 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10944485 # number of overall hits +system.cpu0.dcache.overall_hits::total 10944485 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 934191 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 934191 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 249028 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 249028 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5734 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5734 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1183219 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1183219 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1183219 # number of overall misses +system.cpu0.dcache.overall_misses::total 1183219 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42879044000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42879044000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16797420000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16797420000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151036000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 151036000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 96889000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 96889000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 59676464000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 59676464000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 59676464000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 59676464000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277433 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7277433 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850271 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4850271 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151733 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 151733 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151194 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 151194 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12127704 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12127704 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12127704 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12127704 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128368 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128368 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051343 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051343 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037925 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037925 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097563 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097563 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097563 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097563 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45899.654353 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 45899.654353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67451.933116 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67451.933116 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11123.582265 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11123.582265 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16897.279386 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16897.279386 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50435.687730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50435.687730 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,126 +583,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 679941 # number of writebacks -system.cpu0.dcache.writebacks::total 679941 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939259 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939259 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251797 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251797 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13671 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13671 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191056 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1191056 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191056 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1191056 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10829 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17939 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27961966000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27961966000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10623615500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10623615500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136697000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136697000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42311000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42311000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38585581500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38585581500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38585581500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38585581500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1492228000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1492228000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2319869500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2319869500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3812097500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3812097500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127649 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127649 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 672708 # number of writebacks +system.cpu0.dcache.writebacks::total 672708 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934191 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 934191 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249028 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249028 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5734 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5734 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1183219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183219 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1183219 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41944853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41944853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16548392000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16548392000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137458000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137458000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58493245000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 58493245000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58493245000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 58493245000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1488672000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1488672000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2316060500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2316060500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3804732500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3804732500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097563 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097563 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44899.654353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44899.654353 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66451.933116 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66451.933116 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10123.582265 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10123.582265 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15897.279386 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15897.279386 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210086.367485 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210086.367485 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214768.221439 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214768.221439 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212911.723559 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212911.723559 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 700401 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.179347 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 686863 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.493433 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 46646633 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 687375 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.861987 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 58997592500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.493433 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989245 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.989245 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits -system.cpu0.icache.overall_hits::total 47091062 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses -system.cpu0.icache.overall_misses::total 701031 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48021627 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48021627 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 46646633 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46646633 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46646633 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46646633 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46646633 # number of overall hits +system.cpu0.icache.overall_hits::total 46646633 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687497 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687497 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687497 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687497 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687497 # number of overall misses +system.cpu0.icache.overall_misses::total 687497 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10629492500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10629492500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10629492500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10629492500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10629492500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10629492500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47334130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47334130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47334130 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47334130 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47334130 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47334130 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15461.147467 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15461.147467 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15461.147467 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15461.147467 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -715,51 +711,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 701031 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 701031 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 701031 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 701031 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 701031 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 701031 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9316608000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9316608000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9316608000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9316608000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9316608000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9316608000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687497 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687497 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687497 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687497 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687497 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687497 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9941995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9941995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9941995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9941995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9941995500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9941995500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14461.147467 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2409623 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_hits 2508569 # DTB read hits +system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1749165 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.read_accesses 239364 # DTB read accesses +system.cpu1.dtb.write_hits 1828737 # DTB write hits +system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4158788 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.write_accesses 105248 # DTB write accesses +system.cpu1.dtb.data_hits 4337306 # DTB hits +system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1960477 # ITB hits +system.cpu1.dtb.data_accesses 344612 # DTB accesses +system.cpu1.itb.fetch_hits 1989876 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1961693 # ITB accesses +system.cpu1.itb.fetch_accesses 1991092 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -772,87 +768,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3925216965 # number of cpu cycles simulated +system.cpu1.numCycles 3965170714 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13101094 # Number of instructions committed -system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses -system.cpu1.num_func_calls 409417 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12083765 # number of integer instructions -system.cpu1.num_fp_insts 172106 # number of float instructions -system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written -system.cpu1.num_mem_refs 4182249 # number of memory refs -system.cpu1.num_load_insts 2423870 # Number of load instructions -system.cpu1.num_store_insts 1758379 # Number of store instructions -system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles -system.cpu1.Branches 1864071 # Number of branches fetched -system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction -system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction +system.cpu1.committedInsts 13660009 # Number of instructions committed +system.cpu1.committedOps 13660009 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12598388 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 178445 # Number of float alu accesses +system.cpu1.num_func_calls 429702 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1355296 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12598388 # number of integer instructions +system.cpu1.num_fp_insts 178445 # number of float instructions +system.cpu1.num_int_register_reads 17340989 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9240436 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 93179 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 95134 # number of times the floating registers were written +system.cpu1.num_mem_refs 4361445 # number of memory refs +system.cpu1.num_load_insts 2523214 # Number of load instructions +system.cpu1.num_store_insts 1838231 # Number of store instructions +system.cpu1.num_idle_cycles 3912374881.998026 # Number of idle cycles +system.cpu1.num_busy_cycles 52795832.001973 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013315 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986685 # Percentage of idle cycles +system.cpu1.Branches 1945174 # Number of branches fetched +system.cpu1.op_class::No_OpClass 733210 5.37% 5.37% # Class of executed instruction +system.cpu1.op_class::IntAlu 8079835 59.13% 64.50% # Class of executed instruction +system.cpu1.op_class::IntMult 22791 0.17% 64.67% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.67% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14367 0.11% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::MemRead 2597857 19.01% 83.80% # Class of executed instruction +system.cpu1.op_class::MemWrite 1839254 13.46% 97.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 374073 2.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13104456 # Class of executed instruction +system.cpu1.op_class::total 13663373 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2868 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 81018 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27534 38.52% 38.52% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 523 0.73% 42.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41447 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71475 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26667 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 523 0.95% 52.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26144 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55305 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1912303307000 96.46% 96.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705769500 0.04% 96.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 367699000 0.02% 96.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 69207844500 3.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1982584620000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968512 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.630781 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.773767 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -868,124 +864,124 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2064 2.79% 3.38% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed -system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65156 88.12% 91.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed +system.cpu1.kern.callpal::rti 3824 5.17% 99.76% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71137 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches -system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 889 -system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 424 -system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73942 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2112 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 911 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 447 +system.cpu1.kern.mode_switch_good::kernel 0.431345 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1986 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 165381 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.153030 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.331454 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 19415818500 0.98% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1728972000 0.09% 1.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1961439827500 98.93% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2065 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 173710 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.751289 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4161033 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 174222 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.883511 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90304766500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.751289 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940920 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940920 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1632527 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48591 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48591 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50409 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50409 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3878271 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3878271 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3878271 # number of overall hits -system.cpu1.dcache.overall_hits::total 3878271 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 117597 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 117597 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62279 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62279 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8857 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8857 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5813 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5813 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 179876 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 179876 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 179876 # number of overall misses -system.cpu1.dcache.overall_misses::total 179876 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1425631000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1425631000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1255840500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1255840500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80743500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1694806 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57448 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57448 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56222 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56222 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4058147 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4058147 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4058147 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4058147 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049759 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049759 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036747 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 17592927 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 17592927 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2337017 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2337017 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1705874 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1705874 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50407 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 50407 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53062 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 53062 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4042891 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4042891 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4042891 # number of overall hits +system.cpu1.dcache.overall_hits::total 4042891 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 123430 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 123430 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 65652 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 65652 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9249 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9249 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6101 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6101 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 189082 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 189082 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 189082 # number of overall misses +system.cpu1.dcache.overall_misses::total 189082 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1554368000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1554368000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1876323500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1876323500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84244000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84244000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 98989500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 98989500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3430691500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3430691500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3430691500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3430691500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2460447 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2460447 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1771526 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1771526 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59656 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 59656 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4231973 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4231973 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4231973 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4231973 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050166 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050166 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.037060 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.037060 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155039 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155039 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103122 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103122 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044679 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044679 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044679 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044679 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12593.113506 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12593.113506 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28579.837629 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28579.837629 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.444156 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.444156 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16225.127028 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16225.127028 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18143.934907 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18143.934907 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -994,128 +990,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 113645 # number of writebacks -system.cpu1.dcache.writebacks::total 113645 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117597 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 117597 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62279 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62279 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8857 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8857 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5813 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5813 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 179876 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 179876 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 179876 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 179876 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 119711 # number of writebacks +system.cpu1.dcache.writebacks::total 119711 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123430 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 123430 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65652 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 65652 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9249 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9249 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6101 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6101 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 189082 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 189082 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 189082 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 189082 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3347 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1430938000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1430938000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810671500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1810671500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74995000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74995000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 92888500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 92888500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3241609500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3241609500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3241609500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3241609500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 747400000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 747400000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 771114500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 771114500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050166 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037060 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037060 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155039 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155039 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103122 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103122 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044679 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044679 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11593.113506 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11593.113506 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27579.837629 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27579.837629 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.444156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.444156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15225.127028 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15225.127028 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200970.338983 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 200970.338983 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223304.451748 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 223304.451748 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222543.867244 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222543.867244 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 313887 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 331160 # number of replacements +system.cpu1.icache.tags.tagsinuse 442.919388 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13331662 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 331672 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.195319 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1976558526500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.919388 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865077 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.865077 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 31 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits -system.cpu1.icache.overall_hits::total 12790016 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses -system.cpu1.icache.overall_misses::total 314441 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13995086 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13995086 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13331662 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13331662 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13331662 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13331662 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13331662 # number of overall hits +system.cpu1.icache.overall_hits::total 13331662 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 331712 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 331712 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 331712 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 331712 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 331712 # number of overall misses +system.cpu1.icache.overall_misses::total 331712 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4531331500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4531331500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4531331500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4531331500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4531331500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4531331500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13663374 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13663374 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13663374 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13663374 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13663374 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13663374 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024277 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024277 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024277 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024277 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024277 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024277 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13660.438875 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13660.438875 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13660.438875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13660.438875 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1124,30 +1120,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331712 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 331712 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 331712 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 331712 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 331712 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 331712 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4199619500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4199619500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4199619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4199619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4199619500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4199619500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024277 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024277 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024277 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12660.438875 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1161,45 +1157,45 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55595 # Transaction distribution -system.iobus.trans_dist::WriteResp 55595 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7379 # Transaction distribution +system.iobus.trans_dist::ReadResp 7379 # Transaction distribution +system.iobus.trans_dist::WriteReq 55683 # Transaction distribution +system.iobus.trans_dist::WriteResp 55683 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42670 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 82499 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2744123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13414000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1209,9 +1205,9 @@ system.iobus.reqLayer22.occupancy 155000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2454000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1219,52 +1215,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215099489 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28539000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.566806 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1775098751000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.566806 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035425 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035425 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses -system.iocache.demand_misses::total 174 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 174 # number of overall misses -system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22127883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22127883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428057606 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5428057606 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22127883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22127883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22127883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22127883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1273,40 +1269,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126445.045714 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126445.045714 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130632.884241 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130632.884241 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126445.045714 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126445.045714 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 18.333333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13044883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13044883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2830447616 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2830447616 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13044883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13044883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13044883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13044883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13377883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13377883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350457606 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350457606 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13377883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13377883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13377883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13377883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1315,195 +1311,195 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76445.045714 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80632.884241 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80632.884241 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341250 # number of replacements -system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use -system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35905885 # Number of tag accesses -system.l2c.tags.data_accesses 35905885 # Number of data accesses -system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits -system.l2c.Writeback_hits::total 793586 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits +system.l2c.tags.replacements 341926 # number of replacements +system.l2c.tags.tagsinuse 65167.982973 # Cycle average of tags in use +system.l2c.tags.total_refs 3685196 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.056049 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 12918028000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 54774.174056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.572445 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5374.369214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 120.511186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 38.356073 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.835788 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.082006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001839 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000585 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994385 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 516 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6300 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52705 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35906123 # Number of tag accesses +system.l2c.tags.data_accesses 35906123 # Number of data accesses +system.l2c.Writeback_hits::writebacks 792419 # number of Writeback hits +system.l2c.Writeback_hits::total 792419 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 557 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 39 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126818 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 46992 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173810 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 688011 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 313935 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1001946 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 665063 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 108615 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 773678 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 688011 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 791881 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 313935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155607 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949434 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 688011 # number of overall hits -system.l2c.overall_hits::cpu0.data 791881 # number of overall hits -system.l2c.overall_hits::cpu1.inst 313935 # number of overall hits -system.l2c.overall_hits::cpu1.data 155607 # number of overall hits -system.l2c.overall_hits::total 1949434 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2935 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4668 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 882 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 893 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1775 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115542 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6588 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122130 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 12999 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 505 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 271618 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 236 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 271854 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 12999 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387160 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6824 # number of demand (read+write) misses -system.l2c.demand_misses::total 407488 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941009 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764482 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.865350 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959544 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974816 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967136 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480915 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139213 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415606 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291677 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260159 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172987 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172987 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71556.285811 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71793.694690 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71646.178010 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71034.054054 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71513.455328 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71274.271845 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117140.858485 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121861.139369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117443.057297 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121479.185185 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113999.243205 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 119537.091988 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114006.107541 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197585.944115 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188466.101695 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197436.563021 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203268.082344 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 211804.152973 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205289.894558 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201014.941242 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 211009.379509 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202638.129834 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 292720 # Transaction distribution -system.membus.trans_dist::WriteReq 14043 # Transaction distribution -system.membus.trans_dist::WriteResp 14043 # Transaction distribution -system.membus.trans_dist::Writeback 120393 # Transaction distribution -system.membus.trans_dist::CleanEvict 261901 # Transaction distribution -system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution -system.membus.trans_dist::ReadExReq 122456 # Transaction distribution -system.membus.trans_dist::ReadExResp 121630 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution +system.membus.trans_dist::ReadReq 7204 # Transaction distribution +system.membus.trans_dist::ReadResp 292756 # Transaction distribution +system.membus.trans_dist::WriteReq 14131 # Transaction distribution +system.membus.trans_dist::WriteResp 14131 # Transaction distribution +system.membus.trans_dist::Writeback 120910 # Transaction distribution +system.membus.trans_dist::CleanEvict 262059 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16821 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11772 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7147 # Transaction distribution +system.membus.trans_dist::ReadExReq 123180 # Transaction distribution +system.membus.trans_dist::ReadExResp 122316 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285552 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42670 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1235830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1360657 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82499 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31156480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31238979 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21449 # Total snoops (count) -system.membus.snoop_fanout::samples 880387 # Request fanout histogram +system.membus.pkt_size::total 33897219 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22736 # Total snoops (count) +system.membus.snoop_fanout::samples 883364 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 883364 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 880387 # Request fanout histogram -system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 883364 # Request fanout histogram +system.membus.reqLayer0.occupancy 40609000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1325313892 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2193032106 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69837727 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 4790600 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2395468 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361643 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1180 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107021 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 913350 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1503335 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17046 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11835 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28881 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297634 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297634 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019209 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1080623 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 480853 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1918193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544327 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867106 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539630 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6869256 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43998144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118001405 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21229504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604166 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201833219 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 484490 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5237304 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.138719 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.345885 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4511205 86.14% 86.14% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 725687 13.86% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 408 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5237304 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3205453497 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1031366757 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1802104925 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 498533066 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 293884764 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5922aa080..2decdfb20 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922397 # Number of seconds simulated -sim_ticks 1922397182500 # Number of ticks simulated -final_tick 1922397182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.941266 # Number of seconds simulated +sim_ticks 1941266487500 # Number of ticks simulated +final_tick 1941266487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1085217 # Simulator instruction rate (inst/s) -host_op_rate 1085217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37124537063 # Simulator tick rate (ticks/s) -host_mem_usage 372212 # Number of bytes of host memory used -host_seconds 51.78 # Real time elapsed on the host -sim_insts 56195121 # Number of instructions simulated -sim_ops 56195121 # Number of ops (including micro ops) simulated +host_inst_rate 1056307 # Simulator instruction rate (inst/s) +host_op_rate 1056307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36524098946 # Simulator tick rate (ticks/s) +host_mem_usage 374096 # Number of bytes of host memory used +host_seconds 53.15 # Real time elapsed on the host +sim_insts 56143021 # Number of instructions simulated +sim_ops 56143021 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 848768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 848832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24855488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25707776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7409088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7409088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388407 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25705280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7407552 # Number of bytes written to this memory +system.physmem.bytes_written::total 7407552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13263 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388367 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401684 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115767 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115767 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 441515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12930756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13372770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3854088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 441515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12930756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17226858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401684 # Number of read requests accepted -system.physmem.writeReqs 115767 # Number of write requests accepted -system.physmem.readBursts 401684 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115767 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25700352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7407168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25707776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7409088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 401645 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115743 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115743 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 437257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12803749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13241500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3815835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 437257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12803749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17057335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401645 # Number of read requests accepted +system.physmem.writeReqs 115743 # Number of write requests accepted +system.physmem.readBursts 401645 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115743 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25697728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 7406016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25705280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7407552 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25233 # Per bank write bursts -system.physmem.perBankRdBursts::1 25641 # Per bank write bursts -system.physmem.perBankRdBursts::2 25574 # Per bank write bursts -system.physmem.perBankRdBursts::3 25503 # Per bank write bursts -system.physmem.perBankRdBursts::4 24973 # Per bank write bursts -system.physmem.perBankRdBursts::5 24969 # Per bank write bursts -system.physmem.perBankRdBursts::6 24206 # Per bank write bursts -system.physmem.perBankRdBursts::7 24501 # Per bank write bursts -system.physmem.perBankRdBursts::8 25169 # Per bank write bursts -system.physmem.perBankRdBursts::9 24770 # Per bank write bursts -system.physmem.perBankRdBursts::10 25259 # Per bank write bursts -system.physmem.perBankRdBursts::11 24898 # Per bank write bursts -system.physmem.perBankRdBursts::12 24500 # Per bank write bursts -system.physmem.perBankRdBursts::13 25360 # Per bank write bursts -system.physmem.perBankRdBursts::14 25653 # Per bank write bursts -system.physmem.perBankRdBursts::15 25359 # Per bank write bursts -system.physmem.perBankWrBursts::0 7624 # Per bank write bursts -system.physmem.perBankWrBursts::1 7642 # Per bank write bursts -system.physmem.perBankWrBursts::2 7864 # Per bank write bursts -system.physmem.perBankWrBursts::3 7542 # Per bank write bursts -system.physmem.perBankWrBursts::4 7123 # Per bank write bursts -system.physmem.perBankWrBursts::5 6988 # Per bank write bursts -system.physmem.perBankWrBursts::6 6319 # Per bank write bursts -system.physmem.perBankWrBursts::7 6328 # Per bank write bursts -system.physmem.perBankWrBursts::8 7314 # Per bank write bursts -system.physmem.perBankWrBursts::9 6525 # Per bank write bursts -system.physmem.perBankWrBursts::10 7109 # Per bank write bursts -system.physmem.perBankWrBursts::11 6927 # Per bank write bursts -system.physmem.perBankWrBursts::12 7069 # Per bank write bursts -system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7867 # Per bank write bursts -system.physmem.perBankWrBursts::15 7675 # Per bank write bursts +system.physmem.perBankRdBursts::0 25168 # Per bank write bursts +system.physmem.perBankRdBursts::1 25510 # Per bank write bursts +system.physmem.perBankRdBursts::2 25518 # Per bank write bursts +system.physmem.perBankRdBursts::3 25527 # Per bank write bursts +system.physmem.perBankRdBursts::4 25065 # Per bank write bursts +system.physmem.perBankRdBursts::5 24960 # Per bank write bursts +system.physmem.perBankRdBursts::6 24241 # Per bank write bursts +system.physmem.perBankRdBursts::7 24604 # Per bank write bursts +system.physmem.perBankRdBursts::8 25078 # Per bank write bursts +system.physmem.perBankRdBursts::9 24653 # Per bank write bursts +system.physmem.perBankRdBursts::10 25359 # Per bank write bursts +system.physmem.perBankRdBursts::11 24824 # Per bank write bursts +system.physmem.perBankRdBursts::12 24407 # Per bank write bursts +system.physmem.perBankRdBursts::13 25357 # Per bank write bursts +system.physmem.perBankRdBursts::14 25770 # Per bank write bursts +system.physmem.perBankRdBursts::15 25486 # Per bank write bursts +system.physmem.perBankWrBursts::0 7561 # Per bank write bursts +system.physmem.perBankWrBursts::1 7519 # Per bank write bursts +system.physmem.perBankWrBursts::2 7810 # Per bank write bursts +system.physmem.perBankWrBursts::3 7560 # Per bank write bursts +system.physmem.perBankWrBursts::4 7221 # Per bank write bursts +system.physmem.perBankWrBursts::5 6978 # Per bank write bursts +system.physmem.perBankWrBursts::6 6351 # Per bank write bursts +system.physmem.perBankWrBursts::7 6424 # Per bank write bursts +system.physmem.perBankWrBursts::8 7248 # Per bank write bursts +system.physmem.perBankWrBursts::9 6410 # Per bank write bursts +system.physmem.perBankWrBursts::10 7207 # Per bank write bursts +system.physmem.perBankWrBursts::11 6855 # Per bank write bursts +system.physmem.perBankWrBursts::12 6980 # Per bank write bursts +system.physmem.perBankWrBursts::13 7819 # Per bank write bursts +system.physmem.perBankWrBursts::14 7982 # Per bank write bursts +system.physmem.perBankWrBursts::15 7794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 1922385313500 # Total gap between requests +system.physmem.numWrRetry 23 # Number of times write queue was full causing retry +system.physmem.totGap 1941254508500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401684 # Read request sizes (log2) +system.physmem.readPktSize::6 401645 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115767 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401554 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115743 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401513 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,195 +148,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 514.603333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 307.690032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.700723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15764 24.50% 24.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11265 17.51% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5118 7.96% 49.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3016 4.69% 54.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2317 3.60% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1789 2.78% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1464 2.28% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1374 2.14% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22229 34.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64336 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.750735 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2955.508201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5096 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64921 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.908104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.461658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.215984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15228 23.46% 23.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11644 17.94% 41.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4997 7.70% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2980 4.59% 53.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2446 3.77% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4228 6.51% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1452 2.24% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19883 30.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64921 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5102 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.697570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2954.645683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5099 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5099 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5099 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.697980 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.062005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.025558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4477 87.80% 87.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 19 0.37% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 190 3.73% 91.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 14 0.27% 92.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 27 0.53% 92.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 1.04% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.27% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.06% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.12% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.16% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.04% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.20% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.08% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 16 0.31% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 21 0.41% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 18 0.35% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 148 2.90% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.24% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.06% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.10% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 4 0.08% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 5 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 5 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5099 # Writes before turning the bus around for reads -system.physmem.totQLat 2147063750 # Total ticks spent queuing -system.physmem.totMemAccLat 9676463750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5346.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5102 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5102 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.681105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.154688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.203626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4492 88.04% 88.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 201 3.94% 91.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 29 0.57% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 48 0.94% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 38 0.74% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.12% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.22% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 38 0.74% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 34 0.67% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.02% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 159 3.12% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.10% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 8 0.16% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.08% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5102 # Writes before turning the bus around for reads +system.physmem.totQLat 2705942000 # Total ticks spent queuing +system.physmem.totMemAccLat 10234573250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6739.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24096.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25489.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing -system.physmem.readRowHits 359411 # Number of row buffer hits during reads -system.physmem.writeRowHits 93558 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes -system.physmem.avgGap 3715106.00 # Average gap between requests -system.physmem.pageHitRate 87.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236030760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128786625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564680000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372146400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64059295815 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097244171000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289166540360 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.604667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1825128497250 # Time in different power states -system.physmem_0.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing +system.physmem.readRowHits 358859 # Number of row buffer hits during reads +system.physmem.writeRowHits 93466 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.75 # Row buffer hit rate for writes +system.physmem.avgGap 3752028.47 # Average gap between requests +system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239349600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130597500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1564625400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 372107520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 71640444015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101913691250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302654485925 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.035450 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832853481750 # Time in different power states +system.physmem_0.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33072782750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43583902000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250349400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136599375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567550400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377829360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65774789190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1095739352250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289407899735 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.730219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1822618194250 # Time in different power states -system.physmem_1.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem_1.actEnergy 251453160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 137201625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567285200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 377751600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72584952255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101085183500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302797497980 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.109115 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831469435000 # Time in different power states +system.physmem_1.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35583085750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 44967962500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066440 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9058452 # DTB read hits +system.cpu.dtb.read_misses 10327 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6357400 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728858 # DTB read accesses +system.cpu.dtb.write_hits 6353129 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15423840 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15411581 # DTB hits +system.cpu.dtb.data_misses 11470 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973902 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020790 # DTB accesses +system.cpu.itb.fetch_hits 4975133 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978899 # ITB accesses +system.cpu.itb.fetch_accesses 4980143 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -349,37 +333,37 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3844794365 # number of cpu cycles simulated +system.cpu.numCycles 3882532975 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195121 # Number of instructions committed -system.cpu.committedOps 56195121 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066883 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483708 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469750 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066883 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71341331 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530727 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15476411 # number of memory refs -system.cpu.num_load_insts 9103258 # Number of load instructions -system.cpu.num_store_insts 6373153 # Number of store instructions -system.cpu.num_idle_cycles 3587818415.000134 # Number of idle cycles -system.cpu.num_busy_cycles 256975949.999866 # Number of busy cycles -system.cpu.not_idle_fraction 0.066837 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933163 # Percentage of idle cycles -system.cpu.Branches 8423975 # Number of branches fetched -system.cpu.op_class::No_OpClass 3201032 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36240615 64.48% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61007 0.11% 70.28% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.committedInsts 56143021 # Number of instructions committed +system.cpu.committedOps 56143021 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52016582 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1482534 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6465507 # number of instructions that are conditional controls +system.cpu.num_int_insts 52016582 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71267420 # number of times the integer registers were read +system.cpu.num_int_register_writes 38489507 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15464199 # number of memory refs +system.cpu.num_load_insts 9095305 # Number of load instructions +system.cpu.num_store_insts 6368894 # Number of store instructions +system.cpu.num_idle_cycles 3584401371.998154 # Number of idle cycles +system.cpu.num_busy_cycles 298131603.001846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076788 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923212 # Percentage of idle cycles +system.cpu.Branches 8418668 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199011 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36202225 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61032 0.11% 70.27% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction @@ -402,34 +386,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9330336 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6379227 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953006 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9322424 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6374975 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56206940 # Class of executed instruction +system.cpu.op_class::total 56154858 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211964 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74896 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73529 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212043 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74906 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106248 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183220 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73539 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73529 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149121 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858096797000 96.66% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 92317000 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 743733500 0.04% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 63463601000 3.30% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1922396448500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73539 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149144 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860736112500 95.85% 95.85% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92522000 0.00% 95.86% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 746030500 0.04% 95.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79691088500 4.11% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1941265753500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692253 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814086 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692145 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814016 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -465,113 +449,113 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175955 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175993 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192899 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu.kern.callpal::total 192944 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5907 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323509 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323345 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46413360000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5233781000 0.27% 2.69% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1870749305500 97.31% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390740 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14051600 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391252 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099968 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392117 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 48524962500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5595783500 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887145005500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1390004 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.973850 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14040102 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390516 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.097045 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 143374500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.973850 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999949 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999949 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63162665 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63162665 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816092 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816092 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853262 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853262 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669354 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669354 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669354 # number of overall hits -system.cpu.dcache.overall_hits::total 13669354 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069466 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069466 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304560 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304560 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374026 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374026 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374026 # number of overall misses -system.cpu.dcache.overall_misses::total 1374026 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42406775500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42406775500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043380 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043380 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043380 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043380 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28733.719913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28733.719913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38340.684923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38340.684923 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30863.153608 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63112993 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63112993 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7808536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7808536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5849272 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5849272 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199252 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199252 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13657808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13657808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13657808 # number of overall hits +system.cpu.dcache.overall_hits::total 13657808 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069028 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069028 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304257 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304257 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17249 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17249 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373285 # number of overall misses +system.cpu.dcache.overall_misses::total 1373285 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62364550500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62364550500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15031093 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15031093 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15031093 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15031093 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091363 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091363 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091363 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091363 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41861.052751 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41861.052751 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57891.562068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57891.562068 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45412.678723 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,120 +564,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835293 # number of writebacks -system.cpu.dcache.writebacks::total 835293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304560 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29660270500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11372479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11372479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 211647000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 211647000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41032749500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41032749500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41032749500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41032749500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450110500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450110500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2049565500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2049565500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3499676000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3499676000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120360 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120360 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27733.719913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27733.719913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37340.684923 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37340.684923 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12273.660404 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12273.660404 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212390.207254 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212390.207254 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211078.166466 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211078.166466 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43681609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43681609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17309656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17309656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215258000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215258000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60991265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 60991265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60991265500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 60991265500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450109500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450109500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2050243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2050243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3500353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3500353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049444 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049444 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091363 # 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average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.010101 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.010101 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212394.436963 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212394.436963 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211080.805644 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211080.805644 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 55225516 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929183 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.434488 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 58555927500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 506.358595 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.988982 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.988982 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # 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number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929343 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929343 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929343 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929343 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929343 # number of overall misses +system.cpu.icache.overall_misses::total 929343 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13682743000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13682743000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13682743000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13682743000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13682743000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13682743000 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125211.424805 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125211.424805 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -845,125 +829,131 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74255 # number of writebacks -system.cpu.l2cache.writebacks::total 74255 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74231 # number of writebacks +system.cpu.l2cache.writebacks::total 74231 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 280 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 280 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116823 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116823 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13262 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13262 # 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number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 364500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 364500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7775812500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7775812500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 929982000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 929982000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16967384500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16967384500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 929982000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24743197000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25673179000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 929982000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24743197000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25673179000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363485500 # 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number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 922500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 922500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13715906000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13715906000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1604809000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1604809000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30996582000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30996582000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1604809000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44712488000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46317297000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1604809000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44712488000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46317297000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363484500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363484500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1939234000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1939234000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302718500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302718500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014276 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250273 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250273 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173286 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173286 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 28038.461538 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 28038.461538 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66560.630184 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66560.630184 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199160.193004 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199160.193004 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173296 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173296 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199162.907797 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199162.907797 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4638553 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2318842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1135 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1135 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 951075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1744381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 950299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1744757 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 928977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929343 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086450 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2786015 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205333 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6991348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59453248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142553556 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 202006804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419801 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5075497 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.082676 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.275393 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787117 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4203130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6990247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142457836 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201934508 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419768 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5074727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029056 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4655873 91.73% 91.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 419624 8.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5070439 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4288 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5075497 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3168054500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5074727 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3166927500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1393465500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394014500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098643000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2097540500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -979,9 +969,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 51202 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51205 # Transaction distribution +system.iobus.trans_dist::WriteResp 51205 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -993,11 +983,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1009,11 +999,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4773000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1035,23 +1025,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216066756 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215085744 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342844 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.339381 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756461860000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342844 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083928 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083928 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1774103808000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.339381 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083711 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083711 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1065,14 +1055,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21632883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21632883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907244873 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907244873 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21632883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21632883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21632883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21632883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21913883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21913883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427871861 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427871861 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21913883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21913883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21913883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21913883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1089,14 +1079,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125045.566474 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125045.566474 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118098.885084 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118098.885084 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125045.566474 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126669.843931 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126669.843931 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130628.414059 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130628.414059 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126669.843931 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1115,14 +1105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12982883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12982883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12982883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12982883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13263883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13263883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13263883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13263883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1131,59 +1121,59 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75045.566474 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76669.843931 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292339 # Transaction distribution -system.membus.trans_dist::WriteReq 9650 # Transaction distribution -system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115767 # Transaction distribution -system.membus.trans_dist::CleanEvict 261512 # Transaction distribution +system.membus.trans_dist::ReadResp 292325 # Transaction distribution +system.membus.trans_dist::WriteReq 9653 # Transaction distribution +system.membus.trans_dist::WriteResp 9653 # Transaction distribution +system.membus.trans_dist::Writeback 115743 # Transaction distribution +system.membus.trans_dist::CleanEvict 261495 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116704 # Transaction distribution -system.membus.trans_dist::ReadExResp 116704 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285409 # Transaction distribution +system.membus.trans_dist::ReadExReq 116679 # Transaction distribution +system.membus.trans_dist::ReadExResp 116679 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285395 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139625 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172785 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172672 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30503700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1297489 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499692 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33161428 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33157420 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837831 # Request fanout histogram +system.membus.snoop_fanout::samples 837762 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837831 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837762 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837831 # Request fanout histogram -system.membus.reqLayer0.occupancy 30056000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837762 # Request fanout histogram +system.membus.reqLayer0.occupancy 30061000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1285352189 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1285186893 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143948368 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143459620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72076390 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69854947 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 80deda855..14fab3b83 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 714694 # Simulator instruction rate (inst/s) -host_op_rate 870026 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13935517761 # Simulator tick rate (ticks/s) -host_mem_usage 573808 # Number of bytes of host memory used -host_seconds 199.77 # Real time elapsed on the host +host_inst_rate 1159279 # Simulator instruction rate (inst/s) +host_op_rate 1411237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22604281025 # Simulator tick rate (ticks/s) +host_mem_usage 628452 # Number of bytes of host memory used +host_seconds 123.16 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,9 +403,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor @@ -428,8 +428,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits @@ -535,12 +535,18 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks system.cpu.l2cache.writebacks::total 101949 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -548,28 +554,28 @@ system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Tr system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram +system.cpu.toL2Bus.snoops 182974 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -678,7 +684,7 @@ system.membus.trans_dist::ReadResp 74202 # Tr system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::Writeback 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -692,9 +698,9 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -746,13 +752,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index b13c4e56a..6c9ee9f79 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,66 +4,70 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1155692 # Simulator instruction rate (inst/s) -host_op_rate 1408193 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22061708570 # Simulator tick rate (ticks/s) -host_mem_usage 584036 # Number of bytes of host memory used -host_seconds 127.05 # Real time elapsed on the host +host_inst_rate 1151168 # Simulator instruction rate (inst/s) +host_op_rate 1402682 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21975358508 # Simulator tick rate (ticks/s) +host_mem_usage 637292 # Number of bytes of host memory used +host_seconds 127.55 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1090916 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9418084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146388 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1083988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1095972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9418276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 148052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1084052 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11740912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1090916 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146388 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1237304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8475264 # Number of bytes written to this memory +system.physmem.bytes_read::total 11747952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1095972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 148052 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1244024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8467328 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8492828 # Number of bytes written to this memory +system.physmem.bytes_written::total 8484892 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147677 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147680 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16959 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192600 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132426 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192710 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132302 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136817 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136693 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 389210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3360128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 391014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3360196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386762 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4188852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3023754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4191364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 391014 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3020923 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3030020 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3023754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3027189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3020923 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3366380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 391014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3366448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386776 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7218873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7218553 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -367,8 +371,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511204 # number of writebacks -system.cpu0.dcache.writebacks::total 511204 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511149 # number of writebacks +system.cpu0.dcache.writebacks::total 511149 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use @@ -427,9 +431,9 @@ system.cpu0.l2cache.prefetcher.pfRemovedFull 0 system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 252605 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3093887 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.total_refs 3066089 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.510039 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.406624 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor @@ -454,13 +458,13 @@ system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 60120327 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 60120327 # Number of data accesses +system.cpu0.l2cache.tags.tag_accesses 59674327 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59674327 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511204 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511204 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::writebacks 511149 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511149 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits @@ -505,8 +509,8 @@ system.cpu0.l2cache.overall_misses::total 348765 # n system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511204 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511204 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511149 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511149 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses) @@ -558,15 +562,21 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192999 # number of writebacks -system.cpu0.l2cache.writebacks::total 192999 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192992 # number of writebacks +system.cpu0.l2cache.writebacks::total 192992 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720205 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860284 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 118049 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 117943 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511204 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1292017 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511149 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1264197 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution @@ -574,28 +584,28 @@ system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # T system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348291 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402034 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395204 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5791961 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5764086 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887684 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80884164 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152063428 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 327822 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4022806 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.061160 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.239623 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152059908 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 522626 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4217611 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.044172 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.205599 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3776773 93.88% 93.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 246033 6.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031417 95.59% 95.59% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 186088 4.41% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 106 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4022806 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4217611 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -873,8 +883,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120813 # number of writebacks -system.cpu1.dcache.writebacks::total 120813 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120812 # number of writebacks +system.cpu1.dcache.writebacks::total 120812 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use @@ -932,9 +942,9 @@ system.cpu1.l2cache.prefetcher.pfRemovedFull 0 system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 48465 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1307502 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.total_refs 1296358 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.648137 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.472151 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor @@ -957,13 +967,13 @@ system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24723530 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24723530 # Number of data accesses +system.cpu1.l2cache.tags.tag_accesses 24545002 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24545002 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120813 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120813 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::writebacks 120812 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120812 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits @@ -1008,8 +1018,8 @@ system.cpu1.l2cache.overall_misses::total 131449 # n system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120813 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120813 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120812 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120812 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) @@ -1061,15 +1071,21 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32917 # number of writebacks -system.cpu1.l2cache.writebacks::total 32917 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32915 # number of writebacks +system.cpu1.l2cache.writebacks::total 32915 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533423 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773258 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 88765 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 88649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 116 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120813 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 594498 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120812 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 583341 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution @@ -1077,28 +1093,28 @@ system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # T system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571497 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778746 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776513 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2368937 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2357779 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873326 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873262 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56440062 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 568500 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2040956 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.248991 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.432428 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56439998 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 273409 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1745865 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.067447 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.251059 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1532777 75.10% 75.10% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 508179 24.90% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1628228 93.26% 93.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 117521 6.73% 99.99% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 116 0.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2040956 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1745865 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1202,109 +1218,114 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 106825 # number of replacements -system.l2c.tags.tagsinuse 62089.721630 # Cycle average of tags in use -system.l2c.tags.total_refs 288805 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167355 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.725703 # Average number of references to valid blocks. +system.l2c.tags.replacements 106968 # number of replacements +system.l2c.tags.tagsinuse 62096.352232 # Cycle average of tags in use +system.l2c.tags.total_refs 248810 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167499 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.485442 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 47734.864298 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 47767.595021 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.041981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7941.182718 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4069.651943 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1613.022165 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 726.922600 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.728376 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7914.071704 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4068.609194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1612.456889 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 728.691105 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.728876 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.121173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.062098 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.024613 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011092 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.947414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.120759 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.062082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.024604 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.947515 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60523 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60524 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1889 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45532 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1892 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13030 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45506 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.923508 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5581048 # Number of tag accesses -system.l2c.tags.data_accesses 5581048 # Number of data accesses -system.l2c.Writeback_hits::writebacks 225916 # number of Writeback hits -system.l2c.Writeback_hits::total 225916 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 72 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 362 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 60 # number of SCUpgradeReq hits +system.l2c.tags.occ_task_id_percent::1024 0.923523 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5237373 # Number of tag accesses +system.l2c.tags.data_accesses 5237373 # Number of data accesses +system.l2c.Writeback_hits::writebacks 225907 # number of Writeback hits +system.l2c.Writeback_hits::total 225907 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 289 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 360 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 59 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 14091 # number of ReadExReq hits +system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 14099 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17178 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17186 # number of ReadExReq hits system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28425 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76409 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 28346 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76399 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11464 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11380 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 127912 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11438 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11382 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 127799 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28425 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 90500 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28346 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 90498 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11464 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14467 # number of demand (read+write) hits -system.l2c.demand_hits::total 145090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11438 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14469 # number of demand (read+write) hits +system.l2c.demand_hits::total 144985 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28425 # number of overall hits -system.l2c.overall_hits::cpu0.data 90500 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28346 # number of overall hits +system.l2c.overall_hits::cpu0.data 90498 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11464 # number of overall hits -system.l2c.overall_hits::cpu1.data 14467 # number of overall hits -system.l2c.overall_hits::total 145090 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9984 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3297 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13281 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses +system.l2c.overall_hits::cpu1.inst 11438 # number of overall hits +system.l2c.overall_hits::cpu1.data 14469 # number of overall hits +system.l2c.overall_hits::total 144985 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9985 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3298 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13283 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1936 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136573 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::total 1937 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136565 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152409 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152401 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 16484 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 11221 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2277 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1138 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 31129 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 16563 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 11232 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2303 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1139 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 31247 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16484 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 147794 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2277 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16974 # number of demand (read+write) misses -system.l2c.demand_misses::total 183538 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 147797 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2303 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16975 # number of demand (read+write) misses +system.l2c.demand_misses::total 183648 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16484 # number of overall misses -system.l2c.overall_misses::cpu0.data 147794 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2277 # number of overall misses -system.l2c.overall_misses::cpu1.data 16974 # number of overall misses -system.l2c.overall_misses::total 183538 # number of overall misses -system.l2c.Writeback_accesses::writebacks 225916 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225916 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 16563 # number of overall misses +system.l2c.overall_misses::cpu0.data 147797 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2303 # number of overall misses +system.l2c.overall_misses::cpu1.data 16975 # number of overall misses +system.l2c.overall_misses::total 183648 # number of overall misses +system.l2c.Writeback_accesses::writebacks 225907 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225907 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 10274 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 3369 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13643 # number of UpgradeReq accesses(hits+misses) @@ -1317,60 +1338,63 @@ system.l2c.ReadExReq_accesses::total 169587 # nu system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.inst 44909 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 87630 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 42 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 87631 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 43 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.inst 13741 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12518 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 159041 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12521 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 159046 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 44909 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238294 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238295 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 13741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31441 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328628 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31444 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328633 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 44909 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238294 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238295 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 13741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31441 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328628 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971773 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978629 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.973466 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.926650 # miss rate for SCUpgradeReq accesses +system.l2c.overall_accesses::cpu1.data 31444 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328633 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971871 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978925 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.973613 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.927873 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.993255 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966068 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.906474 # miss rate for ReadExReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.966567 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.906421 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.836865 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.898707 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.898660 # miss rate for ReadExReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.367053 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128050 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.165708 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090909 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.195729 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.368812 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128174 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.167601 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090967 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.196465 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.367053 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.620217 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.165708 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.539868 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.558498 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.368812 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.620227 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.167601 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.539849 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.558824 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.367053 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.620217 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.165708 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.539868 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.558498 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.368812 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.620227 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.167601 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.539849 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.558824 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1379,51 +1403,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96236 # number of writebacks -system.l2c.writebacks::total 96236 # number of writebacks +system.l2c.writebacks::writebacks 96112 # number of writebacks +system.l2c.writebacks::total 96112 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 43997 # Transaction distribution -system.membus.trans_dist::ReadResp 75378 # Transaction distribution +system.membus.trans_dist::ReadResp 75496 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::Writeback 132426 # Transaction distribution -system.membus.trans_dist::CleanEvict 15452 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40917 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15653 # Transaction distribution -system.membus.trans_dist::ReadExReq 196055 # Transaction distribution -system.membus.trans_dist::ReadExResp 151973 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31381 # Transaction distribution +system.membus.trans_dist::Writeback 132302 # Transaction distribution +system.membus.trans_dist::CleanEvict 8413 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60363 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40918 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15656 # Transaction distribution +system.membus.trans_dist::ReadExReq 196047 # Transaction distribution +system.membus.trans_dist::ReadExResp 151965 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31499 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 666955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 788339 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 897733 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660257 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 781641 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 890796 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17934348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18124130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17933452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18123234 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20456418 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20455522 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 587659 # Request fanout histogram +system.membus.snoop_fanout::samples 580848 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 587659 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 580848 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 587659 # Request fanout histogram +system.membus.snoop_fanout::total 580848 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1455,45 +1479,51 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks +system.toL2Bus.snoop_filter.tot_requests 874927 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 450220 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 131568 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9077 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 8809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225916 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 84734 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225907 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 41761 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1184948 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 427892 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1612840 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417842 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45103662 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 998221 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.036541 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.187632 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1153838 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 416020 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1569858 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685372 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417714 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45103086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180140 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1129657 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.285654 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.452250 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 961745 96.35% 96.35% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36476 3.65% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 807234 71.46% 71.46% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 322155 28.52% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 268 0.02% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 998221 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1129657 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 33ede6cdf..8e10ef807 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1188421 # Simulator instruction rate (inst/s) -host_op_rate 1446712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23172506899 # Simulator tick rate (ticks/s) -host_mem_usage 571472 # Number of bytes of host memory used -host_seconds 120.14 # Real time elapsed on the host +host_inst_rate 1171566 # Simulator instruction rate (inst/s) +host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22843865684 # Simulator tick rate (ticks/s) +host_mem_usage 624228 # Number of bytes of host memory used +host_seconds 121.87 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,9 +403,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor @@ -428,8 +428,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits @@ -535,12 +535,18 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks system.cpu.l2cache.writebacks::total 101949 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -548,28 +554,28 @@ system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Tr system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram +system.cpu.toL2Bus.snoops 182974 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -678,7 +684,7 @@ system.membus.trans_dist::ReadResp 74202 # Tr system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::Writeback 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -692,9 +698,9 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -746,13 +752,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 2deca7899..719058a40 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868749 # Number of seconds simulated -sim_ticks 2868748596000 # Number of ticks simulated -final_tick 2868748596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871120 # Number of seconds simulated +sim_ticks 2871119862000 # Number of ticks simulated +final_tick 2871119862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 740337 # Simulator instruction rate (inst/s) -host_op_rate 895502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16150564794 # Simulator tick rate (ticks/s) -host_mem_usage 599396 # Number of bytes of host memory used -host_seconds 177.63 # Real time elapsed on the host -sim_insts 131502488 # Number of instructions simulated -sim_ops 159063828 # Number of ops (including micro ops) simulated +host_inst_rate 654504 # Simulator instruction rate (inst/s) +host_op_rate 791691 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14285860596 # Simulator tick rate (ticks/s) +host_mem_usage 653456 # Number of bytes of host memory used +host_seconds 200.98 # Real time elapsed on the host +sim_insts 131539806 # Number of instructions simulated +sim_ops 159111212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1184036 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1278116 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8584576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 111060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 568976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 412800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1136484 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1250788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8185344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 157844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 581136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 673536 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12141100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1184036 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 111060 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1295096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8715904 # Number of bytes written to this memory +system.physmem.bytes_read::total 11986604 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1136484 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 157844 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1294328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8637696 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8733468 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8655260 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20490 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134134 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1890 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 127896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 10524 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198852 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 136186 # Number of write requests responded to by this memory +system.physmem.num_reads::total 196438 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 134964 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140577 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139355 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 412736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 445531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2992446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 38714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 198336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 143895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4232194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 412736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 38714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 451450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3038225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395833 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 435645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2850924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 202407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 234590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4174888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395833 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3008476 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3044348 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3038225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3014594 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3008476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 412736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 451639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2992446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 38714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 198350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 143895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7276541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198852 # Number of read requests accepted -system.physmem.writeReqs 140577 # Number of write requests accepted -system.physmem.readBursts 198852 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140577 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12717568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue -system.physmem.bytesWritten 8745536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12141100 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8733468 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 395833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 441748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2850924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 202421 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 234590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7189482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 196438 # Number of read requests accepted +system.physmem.writeReqs 139355 # Number of write requests accepted +system.physmem.readBursts 196438 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 139355 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12561984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue +system.physmem.bytesWritten 8668288 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11986604 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8655260 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48892 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12039 # Per bank write bursts -system.physmem.perBankRdBursts::1 11932 # Per bank write bursts -system.physmem.perBankRdBursts::2 12219 # Per bank write bursts -system.physmem.perBankRdBursts::3 12193 # Per bank write bursts -system.physmem.perBankRdBursts::4 20606 # Per bank write bursts -system.physmem.perBankRdBursts::5 12429 # Per bank write bursts -system.physmem.perBankRdBursts::6 12151 # Per bank write bursts -system.physmem.perBankRdBursts::7 12313 # Per bank write bursts -system.physmem.perBankRdBursts::8 12521 # Per bank write bursts -system.physmem.perBankRdBursts::9 12643 # Per bank write bursts -system.physmem.perBankRdBursts::10 11981 # Per bank write bursts -system.physmem.perBankRdBursts::11 11107 # Per bank write bursts -system.physmem.perBankRdBursts::12 11212 # Per bank write bursts -system.physmem.perBankRdBursts::13 11639 # Per bank write bursts -system.physmem.perBankRdBursts::14 10708 # Per bank write bursts -system.physmem.perBankRdBursts::15 11019 # Per bank write bursts -system.physmem.perBankWrBursts::0 8788 # Per bank write bursts -system.physmem.perBankWrBursts::1 8813 # Per bank write bursts -system.physmem.perBankWrBursts::2 9145 # Per bank write bursts -system.physmem.perBankWrBursts::3 8891 # Per bank write bursts -system.physmem.perBankWrBursts::4 8356 # Per bank write bursts -system.physmem.perBankWrBursts::5 8969 # Per bank write bursts -system.physmem.perBankWrBursts::6 8864 # Per bank write bursts -system.physmem.perBankWrBursts::7 8722 # Per bank write bursts -system.physmem.perBankWrBursts::8 9036 # Per bank write bursts -system.physmem.perBankWrBursts::9 9148 # Per bank write bursts -system.physmem.perBankWrBursts::10 8611 # Per bank write bursts -system.physmem.perBankWrBursts::11 8177 # Per bank write bursts -system.physmem.perBankWrBursts::12 8063 # Per bank write bursts -system.physmem.perBankWrBursts::13 7981 # Per bank write bursts -system.physmem.perBankWrBursts::14 7509 # Per bank write bursts -system.physmem.perBankWrBursts::15 7576 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 49183 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11406 # Per bank write bursts +system.physmem.perBankRdBursts::1 11655 # Per bank write bursts +system.physmem.perBankRdBursts::2 11752 # Per bank write bursts +system.physmem.perBankRdBursts::3 11575 # Per bank write bursts +system.physmem.perBankRdBursts::4 20585 # Per bank write bursts +system.physmem.perBankRdBursts::5 12467 # Per bank write bursts +system.physmem.perBankRdBursts::6 12095 # Per bank write bursts +system.physmem.perBankRdBursts::7 12222 # Per bank write bursts +system.physmem.perBankRdBursts::8 12044 # Per bank write bursts +system.physmem.perBankRdBursts::9 12120 # Per bank write bursts +system.physmem.perBankRdBursts::10 11627 # Per bank write bursts +system.physmem.perBankRdBursts::11 11103 # Per bank write bursts +system.physmem.perBankRdBursts::12 11588 # Per bank write bursts +system.physmem.perBankRdBursts::13 11719 # Per bank write bursts +system.physmem.perBankRdBursts::14 10853 # Per bank write bursts +system.physmem.perBankRdBursts::15 11470 # Per bank write bursts +system.physmem.perBankWrBursts::0 8250 # Per bank write bursts +system.physmem.perBankWrBursts::1 8603 # Per bank write bursts +system.physmem.perBankWrBursts::2 8782 # Per bank write bursts +system.physmem.perBankWrBursts::3 8359 # Per bank write bursts +system.physmem.perBankWrBursts::4 8401 # Per bank write bursts +system.physmem.perBankWrBursts::5 9093 # Per bank write bursts +system.physmem.perBankWrBursts::6 8866 # Per bank write bursts +system.physmem.perBankWrBursts::7 8828 # Per bank write bursts +system.physmem.perBankWrBursts::8 8708 # Per bank write bursts +system.physmem.perBankWrBursts::9 8716 # Per bank write bursts +system.physmem.perBankWrBursts::10 8411 # Per bank write bursts +system.physmem.perBankWrBursts::11 8212 # Per bank write bursts +system.physmem.perBankWrBursts::12 8400 # Per bank write bursts +system.physmem.perBankWrBursts::13 8108 # Per bank write bursts +system.physmem.perBankWrBursts::14 7766 # Per bank write bursts +system.physmem.perBankWrBursts::15 7939 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 39 # Number of times write queue was full causing retry -system.physmem.totGap 2868748135500 # Total gap between requests +system.physmem.numWrRetry 25 # Number of times write queue was full causing retry +system.physmem.totGap 2871119474000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9731 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 189093 # Read request sizes (log2) +system.physmem.readPktSize::6 186679 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136186 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 134964 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 137894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -180,158 +180,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 133 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88033 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.806754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 138.095781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.392225 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45989 52.24% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18103 20.56% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5912 6.72% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3673 4.17% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2470 2.81% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 1.78% 88.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 995 1.13% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 958 1.09% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8368 9.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88033 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.243709 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 545.811163 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.110228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.616765 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.492638 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5748 84.59% 84.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 291 4.28% 88.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 178 2.62% 91.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 60 0.88% 92.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 79 1.16% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 156 2.30% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 28 0.41% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.18% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.10% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.13% 96.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 96.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 161 2.37% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.16% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.07% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads -system.physmem.totQLat 4722732900 # Total ticks spent queuing -system.physmem.totMemAccLat 8448582900 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 993560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23766.72 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.210195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.335340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.154059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46068 52.56% 52.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17715 20.21% 72.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6262 7.14% 79.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3427 3.91% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2480 2.83% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1647 1.88% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 825 0.94% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 930 1.06% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8298 9.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87652 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6626 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.622698 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 552.814463 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6624 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6626 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.440990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.878741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.359150 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5426 81.89% 81.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 462 6.97% 88.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 72 1.09% 89.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 157 2.37% 92.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.48% 92.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 137 2.07% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.62% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.26% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 26 0.39% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 21 0.32% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 152 2.29% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.38% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.06% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6626 # Writes before turning the bus around for reads +system.physmem.totQLat 4505900396 # Total ticks spent queuing +system.physmem.totMemAccLat 8186169146 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 981405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22956.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42516.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41706.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.76 # Average write queue length when enqueuing -system.physmem.readRowHits 166188 # Number of row buffer hits during reads -system.physmem.writeRowHits 81139 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes -system.physmem.avgGap 8451688.38 # Average gap between requests -system.physmem.pageHitRate 73.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 346580640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 189106500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 825871800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 457151040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84248156880 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647343810500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920782998080 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.555658 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740372132788 # Time in different power states -system.physmem_0.memoryStateTime::REF 95793620000 # Time in different power states +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing +system.physmem.readRowHits 163849 # Number of row buffer hits during reads +system.physmem.writeRowHits 80221 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.22 # Row buffer hit rate for writes +system.physmem.avgGap 8550266.01 # Average gap between requests +system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 338884560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 184907250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 809296800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 448299360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85706052435 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647489846750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1922504718675 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.601510 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740606830696 # Time in different power states +system.physmem_0.memoryStateTime::REF 95872920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32582747712 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34639965804 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 318948840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 174029625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 724074000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 428334480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83576818575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1647932703750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920527229990 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.466501 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2741353761866 # Time in different power states -system.physmem_1.memoryStateTime::REF 95793620000 # Time in different power states +system.physmem_1.actEnergy 323764560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 176657250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 721687200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 429364800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84711391605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648362356250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922252653185 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.513716 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742063716846 # Time in different power states +system.physmem_1.memoryStateTime::REF 95872920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31595469384 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33181034404 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -387,57 +390,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7824 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7824 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1442 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6382 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7824 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7824 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7824 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10325.194401 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9252.413387 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6597.669693 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 6417 99.80% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 7 0.11% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 5019 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5019 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1041 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 3978 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 5019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5019 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 4056 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10869.452663 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9826.177645 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7625.006320 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 4042 99.65% 99.65% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10 0.25% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.07% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1109412500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1109412500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1109412500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5027 78.18% 78.18% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1403 21.82% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6430 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7824 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 4056 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3032 74.75% 74.75% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1024 25.25% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4056 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5019 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7824 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6430 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5019 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4056 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6430 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14254 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4056 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9075 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25236580 # DTB read hits -system.cpu0.dtb.read_misses 6707 # DTB read misses -system.cpu0.dtb.write_hits 18793560 # DTB write hits -system.cpu0.dtb.write_misses 1117 # DTB write misses +system.cpu0.dtb.read_hits 23515104 # DTB read hits +system.cpu0.dtb.read_misses 4346 # DTB read misses +system.cpu0.dtb.write_hits 17278792 # DTB write hits +system.cpu0.dtb.write_misses 673 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3444 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2434 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1747 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1554 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25243287 # DTB read accesses -system.cpu0.dtb.write_accesses 18794677 # DTB write accesses +system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23519450 # DTB read accesses +system.cpu0.dtb.write_accesses 17279465 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 44030140 # DTB hits -system.cpu0.dtb.misses 7824 # DTB misses -system.cpu0.dtb.accesses 44037964 # DTB accesses +system.cpu0.dtb.hits 40793896 # DTB hits +system.cpu0.dtb.misses 5019 # DTB misses +system.cpu0.dtb.accesses 40798915 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -467,40 +469,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3348 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10655.874786 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9465.333686 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5846.917058 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 920 39.45% 39.45% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1284 55.06% 94.51% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 84 3.60% 98.11% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 8 0.34% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1109040500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1109040500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1109040500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2305 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 237 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2068 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 1509 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10774.022531 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9696.406116 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7256.111559 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 1436 95.16% 95.16% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 61 4.04% 99.20% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 10 0.66% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 1509 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1272 84.29% 84.29% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 237 15.71% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1509 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 119342617 # ITB inst hits -system.cpu0.itb.inst_misses 3348 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 3814 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 111711640 # ITB inst hits +system.cpu0.itb.inst_misses 2305 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -509,179 +509,178 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1402 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 119345965 # ITB inst accesses -system.cpu0.itb.hits 119342617 # DTB hits -system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 119345965 # DTB accesses -system.cpu0.numCycles 5737497192 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 111713945 # ITB inst accesses +system.cpu0.itb.hits 111711640 # DTB hits +system.cpu0.itb.misses 2305 # DTB misses +system.cpu0.itb.accesses 111713945 # DTB accesses +system.cpu0.numCycles 5741309822 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 115654281 # Number of instructions committed -system.cpu0.committedOps 139770289 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123734710 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 12768418 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15718242 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123734710 # number of integer instructions -system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 227859200 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85998639 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 506429091 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52352971 # number of times the CC registers were written -system.cpu0.num_mem_refs 45168124 # number of memory refs -system.cpu0.num_load_insts 25488908 # Number of load instructions -system.cpu0.num_store_insts 19679216 # Number of store instructions -system.cpu0.num_idle_cycles 5463941135.084096 # Number of idle cycles -system.cpu0.num_busy_cycles 273556056.915905 # Number of busy cycles -system.cpu0.not_idle_fraction 0.047679 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.952321 # Percentage of idle cycles -system.cpu0.Branches 29223626 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 98271812 68.45% 68.45% # Class of executed instruction -system.cpu0.op_class::IntMult 109732 0.08% 68.53% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8207 0.01% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::MemRead 25488908 17.75% 86.29% # Class of executed instruction -system.cpu0.op_class::MemWrite 19679216 13.71% 100.00% # Class of executed instruction +system.cpu0.committedInsts 108455216 # Number of instructions committed +system.cpu0.committedOps 130919966 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 115934267 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4495 # Number of float alu accesses +system.cpu0.num_func_calls 12371356 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14793634 # number of instructions that are conditional controls +system.cpu0.num_int_insts 115934267 # number of integer instructions +system.cpu0.num_fp_insts 4495 # number of float instructions +system.cpu0.num_int_register_reads 213655151 # number of times the integer registers were read +system.cpu0.num_int_register_writes 80737315 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3581 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 474775860 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 48809609 # number of times the CC registers were written +system.cpu0.num_mem_refs 41877995 # number of memory refs +system.cpu0.num_load_insts 23749275 # Number of load instructions +system.cpu0.num_store_insts 18128720 # Number of store instructions +system.cpu0.num_idle_cycles 5480212444.901863 # Number of idle cycles +system.cpu0.num_busy_cycles 261097377.098137 # Number of busy cycles +system.cpu0.not_idle_fraction 0.045477 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.954523 # Percentage of idle cycles +system.cpu0.Branches 27818534 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2172 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 92606456 68.80% 68.80% # Class of executed instruction +system.cpu0.op_class::IntMult 105045 0.08% 68.88% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 7793 0.01% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::MemRead 23749275 17.64% 86.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 18128720 13.47% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143560148 # Class of executed instruction +system.cpu0.op_class::total 134599461 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 696532 # number of replacements -system.cpu0.dcache.tags.tagsinuse 491.305468 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43154174 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 697044 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 61.910258 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1135377000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.305468 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959581 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.959581 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88699037 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88699037 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23972048 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23972048 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18061887 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18061887 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318120 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318120 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365603 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365603 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362648 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362648 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 42033935 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 42033935 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42352055 # number of overall hits -system.cpu0.dcache.overall_hits::total 42352055 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 398676 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 398676 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324664 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324664 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 128643 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 128643 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21706 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21706 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19707 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19707 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 723340 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 723340 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 851983 # number of overall misses -system.cpu0.dcache.overall_misses::total 851983 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5067389500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5067389500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5162627000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5162627000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330228000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330228000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435506500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 435506500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1585500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1585500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10230016500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10230016500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10230016500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10230016500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24370724 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24370724 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18386551 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18386551 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446763 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446763 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387309 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387309 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42757275 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42757275 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43204038 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43204038 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017658 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017658 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.287945 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.287945 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056043 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056043 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016917 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016917 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019720 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019720 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.545656 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.545656 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15901.445802 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15901.445802 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.673639 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.673639 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22099.076470 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22099.076470 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 1796 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 588364 # number of replacements +system.cpu0.dcache.tags.tagsinuse 493.639030 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 40011095 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 588715 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 67.963437 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1836356000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.639030 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964139 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.964139 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.685547 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 82121594 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 82121594 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 22367728 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22367728 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16608644 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16608644 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300494 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 300494 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 340955 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 340955 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 337105 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 337105 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 38976372 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 38976372 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 39276866 # number of overall hits +system.cpu0.dcache.overall_hits::total 39276866 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 340778 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 340778 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 289444 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 289444 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 113643 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6274722500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5086196500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086196500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11360919000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11360919000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013895 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013895 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.209667 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.209667 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017156 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017156 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015275 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015275 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017286 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.017286 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13147.901719 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.901719 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18722.378845 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18722.378845 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17896.649814 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17896.649814 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16374.314295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16374.314295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.857674 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.857674 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13091.866210 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13091.866210 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13450.264224 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13450.264224 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196761.976187 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196761.976187 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171898.725582 # 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average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179135.579192 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179135.579192 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188936.139429 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 188936.139429 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1105972 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.454897 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 118236124 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1106484 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 106.857509 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13516114000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.454897 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998935 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998935 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 987035 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.323984 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 110724084 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 987547 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 112.120318 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14346160000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.323984 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998680 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998680 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 239791727 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 239791727 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 118236124 # 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number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10938029500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10938029500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10938029500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10938029500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 119342617 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 119342617 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 119342617 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 119342617 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 119342617 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 119342617 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009272 # 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average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10916.277659 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10916.277659 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,448 +840,451 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1106493 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1106493 # 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average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10286657500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10286657500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10286657500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10286657500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10286657500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10286657500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841098 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1841106 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1606259 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1606313 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 46 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 237750 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 269395 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16110.328705 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3241181 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 285612 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.348196 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 209215 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 245604 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16082.851224 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2813687 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 260278 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.810314 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7729.941983 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.543117 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.104661 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4692.501202 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1977.796502 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1707.441239 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.471798 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000155 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.286408 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.120715 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983296 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1097 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15114 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 275 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 382 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 431 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3320 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7689 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3966 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.066956 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922485 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 60150726 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 60150726 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7925 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3539 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 11464 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 508356 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 508356 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28387 # 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number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365472000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365472000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1464493 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1464493 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2004346000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2004346000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2385304000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2385304000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2775342500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2775342500 # 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miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.475877 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.911860 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.911860 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 7782.048512 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.435939 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.142248 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4563.552019 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1967.112212 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1769.560295 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.474979 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1270 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 259 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1410 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 11666 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.813904 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 52809362 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 52809362 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 5209 # 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mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103665 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228935 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17971.556886 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56080.431658 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20097.617754 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.617754 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14895.796214 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14895.796214 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 107499.363636 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 107499.363636 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40970.516581 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40970.516581 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43657.624649 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23317.538103 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23317.538103 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32523.378397 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46005.871762 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188761.945261 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165310.539933 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164398.725582 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164398.725582 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 177301.806597 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 164936.854273 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.244353 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 16343.396226 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83027.252039 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31352.992194 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31352.992194 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16210.561722 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16210.561722 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 583500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 583500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58928.736033 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58928.736033 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69856.539725 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28234.315480 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28234.315480 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44993.304398 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66891.537242 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189703.746298 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176816.216879 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171635.579192 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171635.579192 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181172.215662 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 174689.138577 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 64646 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1697156 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28719 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 871288 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1384656 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 292494 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87584 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111017 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 299003 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 286103 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1106493 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 579158 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3315880 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2563217 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10051 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22351 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5911499 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70851640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84881644 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14612 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 32580 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 155780476 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1106596 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4822448 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.211081 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.408076 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3288140 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1656034 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 25235 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 165607 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165490 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 117 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 54153 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1498300 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 629767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1193646 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 275537 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87023 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42073 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 110674 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 255600 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 251928 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 987556 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 494836 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3354 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2960662 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2239612 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6956 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14519 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5221749 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 63239672 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 73903156 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10332 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22088 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 137175248 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 821565 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4077224 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.054943 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.227994 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3804521 78.89% 78.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1017927 21.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3853328 94.51% 94.51% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 223779 5.49% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 117 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4822448 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2435282990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4077224 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2138731998 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113496000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115020156 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1668761500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1490356000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1211060981 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1049276975 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 4373000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14212986 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 8998497 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1311,60 +1315,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3357 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3357 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 663 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3357 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2587 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9934.866641 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9080.760096 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4767.740714 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 19 0.73% 0.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 1032 39.89% 40.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1082 41.82% 82.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 330 12.76% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 64 2.47% 97.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 39 1.51% 99.19% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 16 0.62% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 5 0.19% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2587 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1655632468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1655632468 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1655632468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1932 74.68% 74.68% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 655 25.32% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2587 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3357 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 6206 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6206 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1170 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5036 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6206 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6206 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6206 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10147.252747 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9159.943965 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4842.286315 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 42 0.84% 0.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 2213 44.22% 45.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1504 30.05% 75.10% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 1077 21.52% 96.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 52 1.04% 97.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 27 0.54% 98.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 32 0.64% 98.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 42 0.84% 99.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.10% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 7 0.14% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1704519828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1704519828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1704519828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3865 77.22% 77.22% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1140 22.78% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5005 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6206 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3357 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2587 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6206 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5005 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2587 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5944 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5005 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11211 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3844486 # DTB read hits -system.cpu1.dtb.read_misses 2847 # DTB read misses -system.cpu1.dtb.write_hits 3369243 # DTB write hits -system.cpu1.dtb.write_misses 510 # DTB write misses +system.cpu1.dtb.read_hits 5575996 # DTB read hits +system.cpu1.dtb.read_misses 5233 # DTB read misses +system.cpu1.dtb.write_hits 4889133 # DTB write hits +system.cpu1.dtb.write_misses 973 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3067 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3847333 # DTB read accesses -system.cpu1.dtb.write_accesses 3369753 # DTB write accesses +system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5581229 # DTB read accesses +system.cpu1.dtb.write_accesses 4890106 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7213729 # DTB hits -system.cpu1.dtb.misses 3357 # DTB misses -system.cpu1.dtb.accesses 7217086 # DTB accesses +system.cpu1.dtb.hits 10465129 # DTB hits +system.cpu1.dtb.misses 6206 # DTB misses +system.cpu1.dtb.accesses 10471335 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1394,43 +1402,46 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1746 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10678.410117 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9623.001262 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5682.967955 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 356 32.16% 32.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 499 45.08% 77.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 93.59% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 17 1.54% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.71% 97.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 12 1.08% 99.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.45% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 5 0.45% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1655094468 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1655094468 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1655094468 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2787 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2787 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 249 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2538 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2787 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1928 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11234.439834 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9816.231267 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6428.442620 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 752 39.00% 39.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 479 24.84% 63.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 554 28.73% 92.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 71 3.68% 96.27% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.10% 96.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.78% 97.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 0.88% 98.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.26% 98.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 26 1.35% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.16% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.10% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1928 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1705600828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1705600828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1705600828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1679 87.09% 87.09% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 249 12.91% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1928 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2787 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2787 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16180944 # ITB inst hits -system.cpu1.itb.inst_misses 1746 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1928 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1928 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 4715 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 23850368 # ITB inst hits +system.cpu1.itb.inst_misses 2787 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1439,178 +1450,179 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1894 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16182690 # ITB inst accesses -system.cpu1.itb.hits 16180944 # DTB hits -system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 16182690 # DTB accesses -system.cpu1.numCycles 5736568944 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 23853155 # ITB inst accesses +system.cpu1.itb.hits 23850368 # DTB hits +system.cpu1.itb.misses 2787 # DTB misses +system.cpu1.itb.accesses 23853155 # DTB accesses +system.cpu1.numCycles 5742239724 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15848207 # Number of instructions committed -system.cpu1.committedOps 19293539 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17383760 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 938177 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1786282 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17383760 # number of integer instructions -system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 31469136 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12170371 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 70461385 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6330901 # number of times the CC registers were written -system.cpu1.num_mem_refs 7446495 # number of memory refs -system.cpu1.num_load_insts 3955836 # Number of load instructions -system.cpu1.num_store_insts 3490659 # Number of store instructions -system.cpu1.num_idle_cycles 5686521745.715384 # Number of idle cycles -system.cpu1.num_busy_cycles 50047198.284615 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008724 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991276 # Percentage of idle cycles -system.cpu1.Branches 2803460 # Number of branches fetched -system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12144730 61.90% 61.90% # Class of executed instruction -system.cpu1.op_class::IntMult 26187 0.13% 62.03% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3277 0.02% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::MemRead 3955836 20.16% 82.21% # Class of executed instruction -system.cpu1.op_class::MemWrite 3490659 17.79% 100.00% # Class of executed instruction +system.cpu1.committedInsts 23084590 # Number of instructions committed +system.cpu1.committedOps 28191246 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 25227117 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses +system.cpu1.num_func_calls 1341368 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2715447 # number of instructions that are conditional controls +system.cpu1.num_int_insts 25227117 # number of integer instructions +system.cpu1.num_fp_insts 6988 # number of float instructions +system.cpu1.num_int_register_reads 45751310 # number of times the integer registers were read +system.cpu1.num_int_register_writes 17465196 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102291851 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9890204 # number of times the CC registers were written +system.cpu1.num_mem_refs 10752307 # number of memory refs +system.cpu1.num_load_insts 5706058 # Number of load instructions +system.cpu1.num_store_insts 5046249 # Number of store instructions +system.cpu1.num_idle_cycles 5671495056.418025 # Number of idle cycles +system.cpu1.num_busy_cycles 70744667.581975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012320 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987680 # Percentage of idle cycles +system.cpu1.Branches 4219564 # Number of branches fetched +system.cpu1.op_class::No_OpClass 167 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 17843088 62.32% 62.32% # Class of executed instruction +system.cpu1.op_class::IntMult 31349 0.11% 62.43% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3702 0.01% 62.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.44% # Class of executed instruction +system.cpu1.op_class::MemRead 5706058 19.93% 82.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 5046249 17.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 19620755 # Class of executed instruction +system.cpu1.op_class::total 28630613 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 186869 # number of replacements -system.cpu1.dcache.tags.tagsinuse 468.718276 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6945303 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187221 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.096816 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104852682500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.718276 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915465 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.915465 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14648138 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14648138 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3533706 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3533706 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3181686 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3181686 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48716 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48716 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78610 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78610 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70554 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70554 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6715392 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6715392 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6764108 # number of overall hits -system.cpu1.dcache.overall_hits::total 6764108 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133537 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133537 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 91347 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 91347 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30388 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30388 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17048 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17048 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23285 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23285 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 224884 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 224884 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255272 # number of overall misses -system.cpu1.dcache.overall_misses::total 255272 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1938354000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1938354000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2351393500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2351393500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 319800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544967000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 544967000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2548000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2548000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4289747500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4289747500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4289747500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4289747500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3667243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3667243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3273033 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3273033 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79104 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79104 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95658 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95658 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93839 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93839 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6940276 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6940276 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7019380 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7019380 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036413 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036413 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027909 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027909 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.384153 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.384153 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178218 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178218 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248138 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248138 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032403 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.032403 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036367 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.036367 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14515.482600 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14515.482600 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25741.332501 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25741.332501 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18758.798686 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18758.798686 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23404.208718 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23404.208718 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2852 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 292035 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.567308 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 10109505 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 292547 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 34.556858 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105794397000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.567308 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917124 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.917124 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 21253597 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 21253597 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 5149175 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5149175 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4639914 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4639914 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 67630 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 67630 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103001 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 103001 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95778 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 95778 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9789089 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9789089 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9856719 # number of overall hits +system.cpu1.dcache.overall_hits::total 9856719 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 190277 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 190277 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 126690 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 126690 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 44121 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 44121 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18673 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18673 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23929 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23929 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 316967 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 316967 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 361088 # number of overall misses +system.cpu1.dcache.overall_misses::total 361088 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2557291000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2557291000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3433917500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3433917500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339355000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 339355000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 630190000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 630190000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5470500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5470500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5991208500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5991208500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5991208500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5991208500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 5339452 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 5339452 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4766604 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4766604 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 111751 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 111751 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 121674 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 121674 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 119707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 119707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 10106056 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 10106056 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 10217807 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 10217807 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035636 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035636 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.026579 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.026579 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.394815 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.394815 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153467 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.153467 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.199896 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.199896 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031364 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031364 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035339 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035339 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13439.832455 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13439.832455 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27104.881995 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27104.881995 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18173.566111 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18173.566111 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26335.826821 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26335.826821 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19075.378862 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19075.378862 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16804.614294 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16804.614294 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18901.679039 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18901.679039 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16592.100818 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16592.100818 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1619,147 +1631,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 116740 # number of writebacks -system.cpu1.dcache.writebacks::total 116740 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 267 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11810 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11810 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 267 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 267 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 267 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133270 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133270 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91347 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91347 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29613 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29613 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5238 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5238 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23285 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23285 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 224617 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 224617 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254230 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254230 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2508 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2508 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2155 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2155 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 4663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 4663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1799290500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1799290500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2260046500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2260046500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487726000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487726000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90112000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90112000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521727000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521727000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4059337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4059337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4547063000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4547063000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 302228000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 302228000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224553500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224553500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 526781500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 526781500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036341 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036341 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027909 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027909 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374355 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374355 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054758 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054758 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248138 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248138 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032364 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032364 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036218 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036218 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13501.091769 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13501.091769 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24741.332501 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24741.332501 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16469.996285 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16469.996285 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17203.512791 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17203.512791 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22406.141293 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22406.141293 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 180790 # number of writebacks +system.cpu1.dcache.writebacks::total 180790 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 404 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13063 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13063 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 404 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 404 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 404 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189873 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 189873 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 126690 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 126690 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 43074 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 43074 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5610 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5610 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23929 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23929 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 316563 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 316563 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 359637 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 359637 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3143 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3143 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2520 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5663 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5663 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2352437000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2352437000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3307227500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3307227500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 648806500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 648806500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97651500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97651500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606310000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606310000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5421500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5421500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5659664500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5659664500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6308471000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6308471000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 420340500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 420340500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 296300500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 296300500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 716641000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 716641000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035560 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035560 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026579 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026579 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.385446 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.385446 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046107 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046107 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.199896 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.199896 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031324 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031324 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035197 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035197 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12389.528790 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12389.528790 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26104.881995 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26104.881995 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15062.601569 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15062.601569 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17406.684492 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17406.684492 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25337.874546 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25337.874546 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18072.260782 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18072.260782 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17885.627188 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17885.627188 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120505.582137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120505.582137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104201.160093 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 104201.160093 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 112970.512546 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 112970.512546 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17878.477586 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17878.477586 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17541.217950 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17541.217950 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 133738.625517 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 133738.625517 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117579.563492 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 117579.563492 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 126547.942787 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 126547.942787 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 501529 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.573325 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15678898 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 502041 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.230314 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 84707327000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.573325 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973776 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973776 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 622414 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.397194 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 23227437 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 622926 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 37.287634 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 105696892000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.397194 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973432 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973432 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 32863919 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 32863919 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 15678898 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15678898 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15678898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15678898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15678898 # number of overall hits -system.cpu1.icache.overall_hits::total 15678898 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 502041 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 502041 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 502041 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 502041 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 502041 # number of overall misses -system.cpu1.icache.overall_misses::total 502041 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4374235500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4374235500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4374235500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4374235500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4374235500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4374235500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16180939 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16180939 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16180939 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16180939 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16180939 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16180939 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031027 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.031027 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031027 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.031027 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031027 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.031027 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8712.904922 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8712.904922 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8712.904922 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8712.904922 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 48323652 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 48323652 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 23227437 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 23227437 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 23227437 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 23227437 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 23227437 # number of overall hits +system.cpu1.icache.overall_hits::total 23227437 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 622926 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 622926 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 622926 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 622926 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 622926 # number of overall misses +system.cpu1.icache.overall_misses::total 622926 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5716886500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5716886500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5716886500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5716886500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5716886500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5716886500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23850363 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23850363 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23850363 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23850363 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23850363 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23850363 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026118 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.026118 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026118 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.026118 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026118 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.026118 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9177.472926 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9177.472926 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9177.472926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9177.472926 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1768,237 +1780,240 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 502041 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 502041 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 502041 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 502041 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 502041 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 502041 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622926 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 622926 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 622926 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 622926 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 622926 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 622926 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4123215000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4123215000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4123215000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4123215000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4123215000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4123215000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15225000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15225000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15225000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15225000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.031027 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.031027 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.031027 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8212.904922 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86016.949153 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86016.949153 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5405423500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5405423500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5405423500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5405423500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5405423500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5405423500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23975000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 23975000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026118 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.026118 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.026118 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8677.472926 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135451.977401 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135451.977401 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199800 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199800 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 437692 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 437708 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 61752 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 45885 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14962.501141 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1260771 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 60629 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.794851 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 85932 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 65711 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15078.335139 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1680940 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 81927 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.517534 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.992983 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.872865 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.082863 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2870.067957 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2148.313714 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 992.170760 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.546020 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000236 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 8770.071442 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.089565 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.088469 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3192.092107 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2103.725355 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1007.268201 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.535283 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000189 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.175175 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.131123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060557 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.913239 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1179 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13548 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 28 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1149 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.194830 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128401 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.061479 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.920309 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1082 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15126 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 297 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 350 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 424 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1569 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11689 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.071960 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2876390500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2001835233 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 5611466233 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22647500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 395196500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 417844000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 277400500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 277400500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22647500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 672597000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 695244500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041953 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950225 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950225 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962591 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962591 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.942414 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.942414 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954027 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.954027 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.550373 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.550373 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402728 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402728 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442608 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157133 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442608 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.386863 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.386863 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.030944 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.296596 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.296596 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132116 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189766 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14076.539101 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35399.651782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16132.527727 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16132.527727 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15482.397823 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15482.397823 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1082750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1082750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32240.143683 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32240.143683 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26963.756732 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15739.450869 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15739.450869 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21899.528115 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24221.103470 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112505.582137 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110264.990689 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 96701.160093 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 96701.160093 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 105201.586961 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 104225.723140 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168343 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15545.454545 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57126.740283 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22278.461810 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22278.461810 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18691.023788 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18691.023788 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2527000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2527000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44219.940604 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44219.940604 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37728.548454 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17293.844958 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17293.844958 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28246.142169 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34461.268734 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125738.625517 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125856.626506 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 110079.563492 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 110079.563492 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118770.439696 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 119048.715753 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 53417 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 719726 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2155 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 479672 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 677908 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 29213 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72925 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85236 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 84437 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66918 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 502041 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 506824 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1497175 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 834504 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5289 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9415 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2346383 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32131332 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24936310 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7860 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13456 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 57088958 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 1117653 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2525896 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.414848 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.492696 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1936586 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 978536 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 13921 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 103851 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 103732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 19887 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 919525 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 223940 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 770866 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 41722 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 69543 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86819 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 103431 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 101180 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 622926 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 309787 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 46 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1858177 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1153867 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8365 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17379 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3037788 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39867972 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35780458 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12160 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 75685138 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 354401 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2220337 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.063895 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.244785 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1478032 58.52% 58.52% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1047864 41.48% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 2078588 93.62% 93.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 141630 6.38% 99.99% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 119 0.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2525896 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 861521000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2220337 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1156529000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79810000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80617594 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 753238500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 934566000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 375346000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 534214495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 5325000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6051499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 11246990 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59423 # Transaction distribution -system.iobus.trans_dist::WriteResp 59423 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31011 # Transaction distribution +system.iobus.trans_dist::ReadResp 31011 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56596 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2232,11 +2253,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71540 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2257,11 +2278,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162790 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484054 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40088000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2301,52 +2322,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187554192 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186504974 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36780000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.390549 # Cycle average of tags in use +system.iocache.tags.replacements 36460 # number of replacements +system.iocache.tags.tagsinuse 14.383048 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36476 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 288373025000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.390549 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899409 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899409 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290140338000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.383048 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898940 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898940 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.tags.tag_accesses 328302 # Number of tag accesses +system.iocache.tags.data_accesses 328302 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 254 # number of ReadReq misses +system.iocache.ReadReq_misses::total 254 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses -system.iocache.demand_misses::total 255 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 255 # number of overall misses -system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32657877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32657877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4277536315 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4277536315 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32657877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32657877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32657877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32657877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 254 # number of demand (read+write) misses +system.iocache.demand_misses::total 254 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 254 # number of overall misses +system.iocache.overall_misses::total 254 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 33010877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33010877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4717790097 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4717790097 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 33010877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 33010877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 33010877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 33010877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 254 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 254 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 254 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 254 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 254 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 254 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2355,40 +2376,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128070.105882 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128070.105882 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.697742 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118085.697742 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128070.105882 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128070.105882 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129964.082677 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129964.082677 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130239.346759 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130239.346759 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129964.082677 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129964.082677 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.571429 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 254 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 254 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19907877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19907877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466336315 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2466336315 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19907877 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37500.688357 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 950.717991 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 465.629828 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2237.479906 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000046 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12055.995118 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.047185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7486.510812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2815.662270 # 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Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007105 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.975969 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32308 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.114235 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042964 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.570736 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.007474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033258 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.974142 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1819 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29951 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.492981 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2359 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30054 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.487183 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.489075 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5325589 # 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number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 33 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 23888 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 44855 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 41598 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 52 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 64 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 16804 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13921 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 9486 # number of demand (read+write) hits +system.l2c.demand_hits::total 150756 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 55 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 33 # number of overall hits +system.l2c.overall_hits::cpu0.inst 23888 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82110.544049 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170761.620535 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94661.741214 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143967.834597 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147398.638532 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 79700.928074 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142673.349744 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 159771.980542 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87741.682765 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 143434.329613 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.821593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.788756 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808854 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758929 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.877509 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.844389 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.754840 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.803361 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.774644 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.173299 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078610 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.536275 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.553759 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.553759 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 76013.832853 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73964.006630 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75238.376780 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77363.529412 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76840.694006 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76971.943296 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135438.267702 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121123.554024 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129379.232212 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126557.694531 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128658.644401 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133834.881063 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171703.525742 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107879.738770 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154992.229331 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154635.508752 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 93079.365079 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149617.507198 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163644.251717 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101289.008659 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 152776.587233 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44038 # Transaction distribution -system.membus.trans_dist::ReadResp 214387 # Transaction distribution -system.membus.trans_dist::WriteReq 30874 # Transaction distribution -system.membus.trans_dist::WriteResp 30874 # Transaction distribution -system.membus.trans_dist::Writeback 136186 # Transaction distribution -system.membus.trans_dist::CleanEvict 15507 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74602 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39992 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12685 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 39841 # Transaction distribution -system.membus.trans_dist::ReadExResp 19332 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170349 # Transaction distribution +system.membus.trans_dist::ReadReq 44076 # Transaction distribution +system.membus.trans_dist::ReadResp 212234 # Transaction distribution +system.membus.trans_dist::WriteReq 30913 # Transaction distribution +system.membus.trans_dist::WriteResp 30913 # Transaction distribution +system.membus.trans_dist::Writeback 134964 # Transaction distribution +system.membus.trans_dist::CleanEvict 15319 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74839 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40260 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12961 # Transaction distribution +system.membus.trans_dist::ReadExReq 39815 # Transaction distribution +system.membus.trans_dist::ReadExResp 19093 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 168158 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 670072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 791596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 900517 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664805 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 786483 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 895419 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162790 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18557448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18747458 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21064578 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123030 # Total snoops (count) -system.membus.snoop_fanout::samples 587901 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27468 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18323720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18514046 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20832190 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123434 # Total snoops (count) +system.membus.snoop_fanout::samples 584834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 587901 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 584834 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 587901 # Request fanout histogram -system.membus.reqLayer0.occupancy 88280499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 584834 # Request fanout histogram +system.membus.reqLayer0.occupancy 88258000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11327500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11355499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 983138119 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 974246641 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1138149025 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1126274005 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64374606 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64655929 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2973,56 +2993,62 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 44042 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 480570 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30874 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 362932 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 82945 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 77217 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 117510 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 92 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50721 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50721 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 436543 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 910965 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 460102 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 151032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21991 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 21404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 587 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44080 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 476819 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 359850 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 80476 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 77372 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40572 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 117944 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51046 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51046 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 432754 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1115711 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 276298 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1392009 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31905816 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4776938 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36682754 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 449881 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1195846 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.169748 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.375411 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1048506 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 332828 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1381334 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 29760096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6517470 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36277566 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 449108 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1186895 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.300945 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.459746 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 992854 83.03% 83.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 202992 16.97% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 830292 69.95% 69.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 356016 30.00% 99.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 587 0.05% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1195846 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 812251839 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1186895 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 806375018 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 359119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 627943021 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 593704114 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 221271516 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 252660411 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 2f0ebe667..79e3a7b0a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903468 # Number of seconds simulated -sim_ticks 2903467553500 # Number of ticks simulated -final_tick 2903467553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909343 # Number of seconds simulated +sim_ticks 2909343316500 # Number of ticks simulated +final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 455888 # Simulator instruction rate (inst/s) -host_op_rate 549660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11767164312 # Simulator tick rate (ticks/s) -host_mem_usage 571472 # Number of bytes of host memory used -host_seconds 246.74 # Real time elapsed on the host -sim_insts 112487279 # Number of instructions simulated -sim_ops 135624752 # Number of ops (including micro ops) simulated +host_inst_rate 666869 # Simulator instruction rate (inst/s) +host_op_rate 804035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17251437084 # Simulator tick rate (ticks/s) +host_mem_usage 624248 # Number of bytes of host memory used +host_seconds 168.64 # Real time elapsed on the host +sim_insts 112463069 # Number of instructions simulated +sim_ops 135595282 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1189412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9042916 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10233864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1189412 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189412 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7647616 # Number of bytes written to this memory +system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7665140 # Number of bytes written to this memory +system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119494 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123875 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 409652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3114523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3524704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 409652 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409652 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2633960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6036 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2639995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2633960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 409652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3120558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6164699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168877 # Number of read requests accepted -system.physmem.writeReqs 123875 # Number of write requests accepted -system.physmem.readBursts 168877 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123875 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10799552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7677760 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10233864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7665140 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166592 # Number of read requests accepted +system.physmem.writeReqs 121840 # Number of write requests accepted +system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10018 # Per bank write bursts -system.physmem.perBankRdBursts::1 9658 # Per bank write bursts -system.physmem.perBankRdBursts::2 10300 # Per bank write bursts -system.physmem.perBankRdBursts::3 9945 # Per bank write bursts -system.physmem.perBankRdBursts::4 18863 # Per bank write bursts -system.physmem.perBankRdBursts::5 10091 # Per bank write bursts -system.physmem.perBankRdBursts::6 10302 # Per bank write bursts -system.physmem.perBankRdBursts::7 10601 # Per bank write bursts -system.physmem.perBankRdBursts::8 9921 # Per bank write bursts -system.physmem.perBankRdBursts::9 10207 # Per bank write bursts -system.physmem.perBankRdBursts::10 9962 # Per bank write bursts -system.physmem.perBankRdBursts::11 9026 # Per bank write bursts -system.physmem.perBankRdBursts::12 9868 # Per bank write bursts -system.physmem.perBankRdBursts::13 10473 # Per bank write bursts -system.physmem.perBankRdBursts::14 9981 # Per bank write bursts -system.physmem.perBankRdBursts::15 9527 # Per bank write bursts -system.physmem.perBankWrBursts::0 7412 # Per bank write bursts -system.physmem.perBankWrBursts::1 7255 # Per bank write bursts -system.physmem.perBankWrBursts::2 8123 # Per bank write bursts -system.physmem.perBankWrBursts::3 7537 # Per bank write bursts -system.physmem.perBankWrBursts::4 7355 # Per bank write bursts -system.physmem.perBankWrBursts::5 7348 # Per bank write bursts -system.physmem.perBankWrBursts::6 7577 # Per bank write bursts -system.physmem.perBankWrBursts::7 7905 # Per bank write bursts -system.physmem.perBankWrBursts::8 7603 # Per bank write bursts -system.physmem.perBankWrBursts::9 7853 # Per bank write bursts -system.physmem.perBankWrBursts::10 7551 # Per bank write bursts -system.physmem.perBankWrBursts::11 6940 # Per bank write bursts -system.physmem.perBankWrBursts::12 7397 # Per bank write bursts -system.physmem.perBankWrBursts::13 7831 # Per bank write bursts -system.physmem.perBankWrBursts::14 7359 # Per bank write bursts -system.physmem.perBankWrBursts::15 6919 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10226 # Per bank write bursts +system.physmem.perBankRdBursts::1 9700 # Per bank write bursts +system.physmem.perBankRdBursts::2 10356 # Per bank write bursts +system.physmem.perBankRdBursts::3 10496 # Per bank write bursts +system.physmem.perBankRdBursts::4 18505 # Per bank write bursts +system.physmem.perBankRdBursts::5 10022 # Per bank write bursts +system.physmem.perBankRdBursts::6 10179 # Per bank write bursts +system.physmem.perBankRdBursts::7 10614 # Per bank write bursts +system.physmem.perBankRdBursts::8 9478 # Per bank write bursts +system.physmem.perBankRdBursts::9 10041 # Per bank write bursts +system.physmem.perBankRdBursts::10 9320 # Per bank write bursts +system.physmem.perBankRdBursts::11 9342 # Per bank write bursts +system.physmem.perBankRdBursts::12 9424 # Per bank write bursts +system.physmem.perBankRdBursts::13 10229 # Per bank write bursts +system.physmem.perBankRdBursts::14 9340 # Per bank write bursts +system.physmem.perBankRdBursts::15 9201 # Per bank write bursts +system.physmem.perBankWrBursts::0 7577 # Per bank write bursts +system.physmem.perBankWrBursts::1 7036 # Per bank write bursts +system.physmem.perBankWrBursts::2 7887 # Per bank write bursts +system.physmem.perBankWrBursts::3 8049 # Per bank write bursts +system.physmem.perBankWrBursts::4 7151 # Per bank write bursts +system.physmem.perBankWrBursts::5 7579 # Per bank write bursts +system.physmem.perBankWrBursts::6 7566 # Per bank write bursts +system.physmem.perBankWrBursts::7 7770 # Per bank write bursts +system.physmem.perBankWrBursts::8 7275 # Per bank write bursts +system.physmem.perBankWrBursts::9 7619 # Per bank write bursts +system.physmem.perBankWrBursts::10 6810 # Per bank write bursts +system.physmem.perBankWrBursts::11 7097 # Per bank write bursts +system.physmem.perBankWrBursts::12 7200 # Per bank write bursts +system.physmem.perBankWrBursts::13 7753 # Per bank write bursts +system.physmem.perBankWrBursts::14 6925 # Per bank write bursts +system.physmem.perBankWrBursts::15 6640 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 2903467231500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2909342872000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159305 # Read request sizes (log2) +system.physmem.readPktSize::6 157020 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119494 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117459 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,159 +159,152 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 170 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # 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What write queue length does an incoming req see system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.689209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.095727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.740944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21592 36.42% 36.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15113 25.49% 61.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5696 9.61% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3272 5.52% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2400 4.05% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1627 2.74% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1059 1.79% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 986 1.66% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7536 12.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59281 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5916 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.520960 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 582.774923 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5915 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5916 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5916 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.278059 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.578317 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.228760 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5122 86.58% 86.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 0.59% 87.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 194 3.28% 90.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 61 1.03% 91.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 61 1.03% 92.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 181 3.06% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.24% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.08% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.12% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.12% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.76% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.03% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.12% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.10% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.29% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5916 # Writes before turning the bus around for reads -system.physmem.totQLat 1515248250 # Total ticks spent queuing -system.physmem.totMemAccLat 4679179500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8979.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads +system.physmem.totQLat 1636363750 # Total ticks spent queuing +system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27729.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.93 # Average write queue length when enqueuing -system.physmem.readRowHits 138696 # Number of row buffer hits during reads -system.physmem.writeRowHits 90730 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.62 # Row buffer hit rate for writes -system.physmem.avgGap 9917839.10 # Average gap between requests -system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229068000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 124987500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 700268400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392117760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87025634640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665738759750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943850825810 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.494214 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770947478500 # Time in different power states -system.physmem_0.memoryStateTime::REF 96952960000 # Time in different power states +system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing +system.physmem.readRowHits 136200 # Number of row buffer hits during reads +system.physmem.writeRowHits 89619 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes +system.physmem.avgGap 10086754.84 # Average gap between requests +system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.621597 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35561301500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219096360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119546625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 615919200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385255440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85786607970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666825625250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943592040605 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.405084 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772773591250 # Time in different power states -system.physmem_1.memoryStateTime::REF 96952960000 # Time in different power states +system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.478544 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33740904250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -361,56 +354,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9548 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9548 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1269 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8279 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9548 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9548 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9548 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7384 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11763.949079 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9756.046308 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7392.958780 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 5809 78.67% 78.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1570 21.26% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7384 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 925393500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 925393500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 925393500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6162 83.45% 83.45% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1222 16.55% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7384 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9548 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 9555 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9548 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7384 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7384 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16932 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24527083 # DTB read hits -system.cpu.dtb.read_misses 8134 # DTB read misses -system.cpu.dtb.write_hits 19611642 # DTB write hits -system.cpu.dtb.write_misses 1414 # DTB write misses +system.cpu.dtb.read_hits 24521784 # DTB read hits +system.cpu.dtb.read_misses 8135 # DTB read misses +system.cpu.dtb.write_hits 19607400 # DTB write hits +system.cpu.dtb.write_misses 1420 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1680 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24535217 # DTB read accesses -system.cpu.dtb.write_accesses 19613056 # DTB write accesses +system.cpu.dtb.read_accesses 24529919 # DTB read accesses +system.cpu.dtb.write_accesses 19608820 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44138725 # DTB hits -system.cpu.dtb.misses 9548 # DTB misses -system.cpu.dtb.accesses 44148273 # DTB accesses +system.cpu.dtb.hits 44129184 # DTB hits +system.cpu.dtb.misses 9555 # DTB misses +system.cpu.dtb.accesses 44138739 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -440,38 +432,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 4762 # Table walker walks requested -system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walks 4763 # Table walker walks requested +system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11752.816221 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9620.437143 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7446.323545 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1417 45.61% 45.61% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1012 32.57% 78.18% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 676 21.76% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115585268 # ITB inst hits -system.cpu.itb.inst_misses 4762 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115560644 # ITB inst hits +system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -487,38 +477,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115590030 # ITB inst accesses -system.cpu.itb.hits 115585268 # DTB hits -system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115590030 # DTB accesses -system.cpu.numCycles 5806935107 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 115565407 # ITB inst accesses +system.cpu.itb.hits 115560644 # DTB hits +system.cpu.itb.misses 4763 # DTB misses +system.cpu.itb.accesses 115565407 # DTB accesses +system.cpu.numCycles 5818686633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112487279 # Number of instructions committed -system.cpu.committedOps 135624752 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119926396 # Number of integer alu accesses +system.cpu.committedInsts 112463069 # Number of instructions committed +system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9895067 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15234125 # number of instructions that are conditional controls -system.cpu.num_int_insts 119926396 # number of integer instructions +system.cpu.num_func_calls 9893453 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls +system.cpu.num_int_insts 119900050 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218121828 # number of times the integer registers were read -system.cpu.num_int_register_writes 82669566 # number of times the integer registers were written +system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read +system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489877250 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51907763 # number of times the CC registers were written -system.cpu.num_mem_refs 45420046 # number of memory refs -system.cpu.num_load_insts 24850080 # Number of load instructions -system.cpu.num_store_insts 20569966 # Number of store instructions -system.cpu.num_idle_cycles 5385437399.888144 # Number of idle cycles -system.cpu.num_busy_cycles 421497707.111855 # Number of busy cycles -system.cpu.not_idle_fraction 0.072585 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927415 # Percentage of idle cycles -system.cpu.Branches 25923230 # Number of branches fetched +system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written +system.cpu.num_mem_refs 45409486 # number of memory refs +system.cpu.num_load_insts 24844046 # Number of load instructions +system.cpu.num_store_insts 20565440 # Number of store instructions +system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles +system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924573 # Percentage of idle cycles +system.cpu.Branches 25918657 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93200379 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114573 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -546,110 +536,110 @@ system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24850080 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20569966 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138745790 # Class of executed instruction +system.cpu.op_class::total 138715716 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3030 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 820821 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.829842 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43246183 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821333 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.653653 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.829842 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999668 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 821347 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177159261 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177159261 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23117842 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23117842 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18828857 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18828857 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392869 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392869 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443457 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443457 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460420 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460420 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41946699 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41946699 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42339568 # number of overall hits -system.cpu.dcache.overall_hits::total 42339568 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401262 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401262 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298702 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298702 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118314 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118314 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22748 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22748 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177121649 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177121649 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112263 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112263 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18824569 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18824569 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392807 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392807 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443229 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460200 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460200 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41936832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41936832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329639 # number of overall hits +system.cpu.dcache.overall_hits::total 42329639 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 401818 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 401818 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298972 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298972 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118323 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22757 # 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average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13154.531148 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12894.927961 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12894.927961 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016414 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016414 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018914 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018914 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15169.085934 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15169.085934 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62897.783070 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62897.783070 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13910.384417 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13910.384417 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13553.716097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13553.716097 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25499.003266 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25499.003266 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23738.923670 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21652540000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21652540000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 676974000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 676974000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # 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average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75035.912215 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22566023500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22566023500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22566023500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22566023500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010606 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063749 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063749 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74277.777778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20795.429414 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20795.429414 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.434832 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.434832 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010581 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023362 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023362 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062853 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062853 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66422.426361 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66422.426361 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70080.452755 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70080.452755 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72705.316558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72705.316558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177208.865840 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 151449.992531 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154209.665145 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154209.665145 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166403.909017 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 152573.851058 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 67206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2292179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1805693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2736 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2738 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699351 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2579570 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12812 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7701560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108793272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96436737 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14388 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205272145 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 179423 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5300588 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.035792 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.185771 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175948 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5110870 96.42% 96.42% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 189718 3.58% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5300588 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3265127000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2558048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1278361999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17827000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::ReadReq 30177 # Transaction distribution +system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1211,9 +1207,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1236,9 +1232,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1279,52 +1275,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187438974 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134160 # Cycle average of tags in use +system.iocache.tags.replacements 36418 # number of replacements +system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 299040065000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134160 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070885 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070885 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.tags.tag_accesses 328068 # Number of tag accesses +system.iocache.tags.data_accesses 328068 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses +system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses -system.iocache.demand_misses::total 234 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 234 # number of overall misses -system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4271537097 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4271537097 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses +system.iocache.demand_misses::total 228 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 228 # number of overall misses +system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1333,14 +1329,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117920.083287 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117920.083287 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1351,22 +1347,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460337097 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2460337097 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1375,68 +1371,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67920.083287 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67920.083287 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 40164 # Transaction distribution -system.membus.trans_dist::ReadResp 70750 # Transaction distribution -system.membus.trans_dist::WriteReq 27594 # Transaction distribution -system.membus.trans_dist::WriteResp 27594 # Transaction distribution -system.membus.trans_dist::Writeback 119494 # Transaction distribution -system.membus.trans_dist::CleanEvict 6493 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::ReadReq 40160 # Transaction distribution +system.membus.trans_dist::ReadResp 70632 # Transaction distribution +system.membus.trans_dist::WriteReq 27589 # Transaction distribution +system.membus.trans_dist::WriteResp 27589 # Transaction distribution +system.membus.trans_dist::Writeback 117459 # Transaction distribution +system.membus.trans_dist::CleanEvict 6342 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 129215 # Transaction distribution -system.membus.trans_dist::ReadExResp 129215 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30586 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution +system.membus.trans_dist::ReadExReq 127038 # Transaction distribution +system.membus.trans_dist::ReadExResp 127038 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445567 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15581884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15745273 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18062393 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 394512 # Request fanout histogram +system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 492 # Total snoops (count) +system.membus.snoop_fanout::samples 390004 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394512 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394512 # Request fanout histogram -system.membus.reqLayer0.occupancy 90495000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390004 # Request fanout histogram +system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 834776313 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 964479239 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64484992 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1469,13 +1465,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 86f263873..83f940052 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1097147 # Simulator instruction rate (inst/s) -host_op_rate 1335600 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21392785088 # Simulator tick rate (ticks/s) -host_mem_usage 571732 # Number of bytes of host memory used -host_seconds 130.13 # Real time elapsed on the host +host_inst_rate 1174884 # Simulator instruction rate (inst/s) +host_op_rate 1430233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22908545755 # Simulator tick rate (ticks/s) +host_mem_usage 623708 # Number of bytes of host memory used +host_seconds 121.52 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -763,9 +763,9 @@ system.iocache.writebacks::total 36190 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 109907 # number of replacements system.l2c.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.l2c.tags.total_refs 4567770 # Total number of references to valid blocks. +system.l2c.tags.total_refs 4528496 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 175188 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 26.073532 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 25.849350 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 48764.072075 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor @@ -794,8 +794,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 10699 # system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40922425 # Number of tag accesses -system.l2c.tags.data_accesses 40922425 # Number of data accesses +system.l2c.tags.tag_accesses 40608233 # Number of tag accesses +system.l2c.tags.data_accesses 40608233 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits @@ -956,7 +956,7 @@ system.membus.trans_dist::ReadResp 74196 # Tr system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::Writeback 138133 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -970,9 +970,9 @@ system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506563 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 613923 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723054 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -1024,22 +1024,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks +system.toL2Bus.snoop_filter.tot_requests 5060706 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2541063 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 71244 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1836352 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1797078 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -1047,27 +1053,27 @@ system.toL2Bus.trans_dist::ReadExReq 298922 # Tr system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116722 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2582000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5084714 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574734 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7761036 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36631 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5176290 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.013064 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.113547 # Request fanout histogram +system.toL2Bus.snoops 182968 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.134877 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5108669 98.69% 98.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 67621 1.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5223970 98.15% 98.15% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 98657 1.85% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5176290 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5322627 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index cda6fdde5..a4264e923 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903518 # Number of seconds simulated -sim_ticks 2903517798500 # Number of ticks simulated -final_tick 2903517798500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909388 # Number of seconds simulated +sim_ticks 2909387991500 # Number of ticks simulated +final_tick 2909387991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 703123 # Simulator instruction rate (inst/s) -host_op_rate 847748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18151522616 # Simulator tick rate (ticks/s) -host_mem_usage 572756 # Number of bytes of host memory used -host_seconds 159.96 # Real time elapsed on the host -sim_insts 112471533 # Number of instructions simulated -sim_ops 135605825 # Number of ops (including micro ops) simulated +host_inst_rate 670421 # Simulator instruction rate (inst/s) +host_op_rate 808321 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17345176485 # Simulator tick rate (ticks/s) +host_mem_usage 625252 # Number of bytes of host memory used +host_seconds 167.73 # Real time elapsed on the host +sim_insts 112452815 # Number of instructions simulated +sim_ops 135583410 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 588836 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3938784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 600704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5102020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 538144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4761988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 646852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4138720 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10231944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 588836 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 600704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189540 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7646016 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7663540 # Number of bytes written to this memory +system.physmem.bytes_read::total 10087176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 538144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 646852 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 8860 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8664 # Number of bytes written to this memory +system.physmem.bytes_written::total 7534772 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17654 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 62062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 79720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 64683 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168847 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119469 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123850 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166585 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2215 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2166 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121838 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 202801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1356556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 206888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1757186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3523982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 202801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 206888 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409689 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2633363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6033 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2639398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2633363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 184968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1636766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 222333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1422540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 184968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 222333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2583790 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 3045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2978 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2589813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2583790 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 202801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1362589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 206888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1757188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6163380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168847 # Number of read requests accepted -system.physmem.writeReqs 123850 # Number of write requests accepted -system.physmem.readBursts 168847 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123850 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10798016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 7677504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10231944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7663540 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 184968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1639812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 222333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1425518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6056926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166585 # Number of read requests accepted +system.physmem.writeReqs 121838 # Number of write requests accepted +system.physmem.readBursts 166585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121838 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue +system.physmem.bytesWritten 7548800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10087176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7534772 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10014 # Per bank write bursts -system.physmem.perBankRdBursts::1 9659 # Per bank write bursts -system.physmem.perBankRdBursts::2 10299 # Per bank write bursts -system.physmem.perBankRdBursts::3 9948 # Per bank write bursts -system.physmem.perBankRdBursts::4 18863 # Per bank write bursts -system.physmem.perBankRdBursts::5 10091 # Per bank write bursts -system.physmem.perBankRdBursts::6 10301 # Per bank write bursts -system.physmem.perBankRdBursts::7 10599 # Per bank write bursts -system.physmem.perBankRdBursts::8 9915 # Per bank write bursts -system.physmem.perBankRdBursts::9 10209 # Per bank write bursts -system.physmem.perBankRdBursts::10 9947 # Per bank write bursts -system.physmem.perBankRdBursts::11 9027 # Per bank write bursts -system.physmem.perBankRdBursts::12 9869 # Per bank write bursts -system.physmem.perBankRdBursts::13 10471 # Per bank write bursts -system.physmem.perBankRdBursts::14 9980 # Per bank write bursts -system.physmem.perBankRdBursts::15 9527 # Per bank write bursts -system.physmem.perBankWrBursts::0 7419 # Per bank write bursts -system.physmem.perBankWrBursts::1 7262 # Per bank write bursts -system.physmem.perBankWrBursts::2 8122 # Per bank write bursts -system.physmem.perBankWrBursts::3 7539 # Per bank write bursts -system.physmem.perBankWrBursts::4 7355 # Per bank write bursts -system.physmem.perBankWrBursts::5 7348 # Per bank write bursts -system.physmem.perBankWrBursts::6 7576 # Per bank write bursts -system.physmem.perBankWrBursts::7 7905 # Per bank write bursts -system.physmem.perBankWrBursts::8 7603 # Per bank write bursts -system.physmem.perBankWrBursts::9 7846 # Per bank write bursts -system.physmem.perBankWrBursts::10 7540 # Per bank write bursts -system.physmem.perBankWrBursts::11 6940 # Per bank write bursts -system.physmem.perBankWrBursts::12 7394 # Per bank write bursts -system.physmem.perBankWrBursts::13 7835 # Per bank write bursts -system.physmem.perBankWrBursts::14 7358 # Per bank write bursts -system.physmem.perBankWrBursts::15 6919 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40727 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10228 # Per bank write bursts +system.physmem.perBankRdBursts::1 9700 # Per bank write bursts +system.physmem.perBankRdBursts::2 10356 # Per bank write bursts +system.physmem.perBankRdBursts::3 10495 # Per bank write bursts +system.physmem.perBankRdBursts::4 18506 # Per bank write bursts +system.physmem.perBankRdBursts::5 10022 # Per bank write bursts +system.physmem.perBankRdBursts::6 10178 # Per bank write bursts +system.physmem.perBankRdBursts::7 10614 # Per bank write bursts +system.physmem.perBankRdBursts::8 9477 # Per bank write bursts +system.physmem.perBankRdBursts::9 10047 # Per bank write bursts +system.physmem.perBankRdBursts::10 9317 # Per bank write bursts +system.physmem.perBankRdBursts::11 9342 # Per bank write bursts +system.physmem.perBankRdBursts::12 9423 # Per bank write bursts +system.physmem.perBankRdBursts::13 10228 # Per bank write bursts +system.physmem.perBankRdBursts::14 9339 # Per bank write bursts +system.physmem.perBankRdBursts::15 9201 # Per bank write bursts +system.physmem.perBankWrBursts::0 7595 # Per bank write bursts +system.physmem.perBankWrBursts::1 7036 # Per bank write bursts +system.physmem.perBankWrBursts::2 7887 # Per bank write bursts +system.physmem.perBankWrBursts::3 8047 # Per bank write bursts +system.physmem.perBankWrBursts::4 7152 # Per bank write bursts +system.physmem.perBankWrBursts::5 7580 # Per bank write bursts +system.physmem.perBankWrBursts::6 7566 # Per bank write bursts +system.physmem.perBankWrBursts::7 7770 # Per bank write bursts +system.physmem.perBankWrBursts::8 7275 # Per bank write bursts +system.physmem.perBankWrBursts::9 7619 # Per bank write bursts +system.physmem.perBankWrBursts::10 6806 # Per bank write bursts +system.physmem.perBankWrBursts::11 7096 # Per bank write bursts +system.physmem.perBankWrBursts::12 7204 # Per bank write bursts +system.physmem.perBankWrBursts::13 7753 # Per bank write bursts +system.physmem.perBankWrBursts::14 6924 # Per bank write bursts +system.physmem.perBankWrBursts::15 6640 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2903517476500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2909387547000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159275 # Read request sizes (log2) +system.physmem.readPktSize::6 157013 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119469 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117457 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -161,178 +161,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8053 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59278 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.674753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.487125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.482596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21806 36.79% 36.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14989 25.29% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5586 9.42% 71.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3267 5.51% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2330 3.93% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1628 2.75% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1108 1.87% 85.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1064 1.79% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7500 12.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59278 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5882 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.683781 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 547.352228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5880 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.902116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.522866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.172226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21290 36.36% 36.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14652 25.03% 61.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6083 10.39% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3178 5.43% 77.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2491 4.25% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1565 2.67% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1038 1.77% 85.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1041 1.78% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7211 12.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58549 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5743 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.986941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 548.492879 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5740 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5882 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.394594 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.624984 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.894436 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 8 0.14% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 7 0.12% 0.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 10 0.17% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4921 83.66% 84.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 66 1.12% 85.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 241 4.10% 89.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 88 1.50% 91.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 77 1.31% 92.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 178 3.03% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.24% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 13 0.22% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.09% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 174 2.96% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.24% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads -system.physmem.totQLat 1493162250 # Total ticks spent queuing -system.physmem.totMemAccLat 4656643500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8849.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5743 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5743 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.538046 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.602147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.025411 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 27 0.47% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 14 0.24% 0.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 12 0.21% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 14 0.24% 1.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4750 82.71% 83.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 125 2.18% 86.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 82 1.43% 87.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 205 3.57% 91.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.56% 91.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 152 2.65% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.19% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.31% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.16% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 172 2.99% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.10% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.37% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.05% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.24% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5743 # Writes before turning the bus around for reads +system.physmem.totQLat 1603192250 # Total ticks spent queuing +system.physmem.totMemAccLat 4724561000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9630.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27599.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28380.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.20 # Average write queue length when enqueuing -system.physmem.readRowHits 138806 # Number of row buffer hits during reads -system.physmem.writeRowHits 90595 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes -system.physmem.avgGap 9919874.40 # Average gap between requests -system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229302360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125115375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 700237200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392208480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87298782345 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665531858750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943921054190 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.505834 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770598960250 # Time in different power states -system.physmem_0.memoryStateTime::REF 96954780000 # Time in different power states +system.physmem.avgWrQLen 7.27 # Average write queue length when enqueuing +system.physmem.readRowHits 136293 # Number of row buffer hits during reads +system.physmem.writeRowHits 89580 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes +system.physmem.avgGap 10087224.48 # Average gap between requests +system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229158720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125037000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702772200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90369730305 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666360544250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948207148235 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.628037 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2771956641500 # Time in different power states +system.physmem_0.memoryStateTime::REF 97150820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35962503500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40279614750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 218839320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119406375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 615763200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385138800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 86123693430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666562638500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943669029305 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.419034 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772326743250 # Time in different power states -system.physmem_1.memoryStateTime::REF 96954780000 # Time in different power states +system.physmem_1.actEnergy 213471720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116477625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595709400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371414160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88357601520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668125569500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947807247845 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.490585 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774916457500 # Time in different power states +system.physmem_1.memoryStateTime::REF 97150820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34236177250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37320566000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -382,60 +379,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6827 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6827 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2216 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4610 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walks 6929 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6929 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2193 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4735 # Level at which table walker walks with short descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6826 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6826 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6826 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5786 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12342.983063 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10713.852920 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6703.217150 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4631 80.04% 80.04% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1152 19.91% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5786 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -1209080312 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.765375 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 925400000 -76.54% -76.54% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -2134480312 176.54% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -1209080312 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3595 62.14% 62.14% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2190 37.86% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5785 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6827 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::samples 6928 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6928 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6928 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5821 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12939.357499 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11196.384549 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7211.949482 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4588 78.82% 78.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1229 21.11% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5821 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1237488496 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean -0.616549 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2000461000 161.65% 161.65% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -762972504 -61.65% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1237488496 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3649 62.70% 62.70% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2171 37.30% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5820 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6929 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6827 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5785 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6929 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5820 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5785 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12612 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5820 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12749 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12507441 # DTB read hits -system.cpu0.dtb.read_misses 5917 # DTB read misses -system.cpu0.dtb.write_hits 9856816 # DTB write hits -system.cpu0.dtb.write_misses 910 # DTB write misses -system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12044488 # DTB read hits +system.cpu0.dtb.read_misses 5975 # DTB read misses +system.cpu0.dtb.write_hits 9654865 # DTB write hits +system.cpu0.dtb.write_misses 954 # DTB write misses +system.cpu0.dtb.flush_tlb 2940 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4603 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4388 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 884 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12513358 # DTB read accesses -system.cpu0.dtb.write_accesses 9857726 # DTB write accesses +system.cpu0.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12050463 # DTB read accesses +system.cpu0.dtb.write_accesses 9655819 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22364257 # DTB hits -system.cpu0.dtb.misses 6827 # DTB misses -system.cpu0.dtb.accesses 22371084 # DTB accesses +system.cpu0.dtb.hits 21699353 # DTB hits +system.cpu0.dtb.misses 6929 # DTB misses +system.cpu0.dtb.accesses 21706282 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,254 +460,256 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3521 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3521 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 830 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2691 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3521 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3521 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3521 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2670 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12834.082397 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11032.722243 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6917.920498 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 769 28.80% 28.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1283 48.05% 76.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 616 23.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2670 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1840 68.91% 68.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 830 31.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2670 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3426 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3426 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 828 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2598 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3426 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3426 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3426 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12817.630962 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11147.269267 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6399.295854 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::4096-6143 694 27.13% 27.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::10240-12287 823 32.17% 59.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::12288-14335 178 6.96% 66.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::14336-16383 343 13.41% 79.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-18431 1 0.04% 79.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::22528-24575 515 20.13% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-26623 4 0.16% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1730 67.63% 67.63% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 828 32.37% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2558 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3521 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3521 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3426 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3426 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2670 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2670 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6191 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 58595537 # ITB inst hits -system.cpu0.itb.inst_misses 3521 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2558 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2558 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5984 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56823446 # ITB inst hits +system.cpu0.itb.inst_misses 3426 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2940 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2691 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2582 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58599058 # ITB inst accesses -system.cpu0.itb.hits 58595537 # DTB hits -system.cpu0.itb.misses 3521 # DTB misses -system.cpu0.itb.accesses 58599058 # DTB accesses -system.cpu0.numCycles 2904052506 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56826872 # ITB inst accesses +system.cpu0.itb.hits 56823446 # DTB hits +system.cpu0.itb.misses 3426 # DTB misses +system.cpu0.itb.accesses 56826872 # DTB accesses +system.cpu0.numCycles 2910048510 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57017963 # Number of instructions committed -system.cpu0.committedOps 68702056 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60736686 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5415 # Number of float alu accesses -system.cpu0.num_func_calls 5101109 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7710665 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60736686 # number of integer instructions -system.cpu0.num_fp_insts 5415 # number of float instructions -system.cpu0.num_int_register_reads 110496547 # number of times the integer registers were read -system.cpu0.num_int_register_writes 42022968 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4193 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 248490103 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26091255 # number of times the CC registers were written -system.cpu0.num_mem_refs 23020484 # number of memory refs -system.cpu0.num_load_insts 12672781 # Number of load instructions -system.cpu0.num_store_insts 10347703 # Number of store instructions -system.cpu0.num_idle_cycles 2689228469.175671 # Number of idle cycles -system.cpu0.num_busy_cycles 214824036.824329 # Number of busy cycles -system.cpu0.not_idle_fraction 0.073974 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.926026 # Percentage of idle cycles -system.cpu0.Branches 13203328 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2205 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 47217639 67.16% 67.16% # Class of executed instruction -system.cpu0.op_class::IntMult 59885 0.09% 67.25% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4420 0.01% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::MemRead 12672781 18.03% 85.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 10347703 14.72% 100.00% # Class of executed instruction +system.cpu0.committedInsts 55288600 # Number of instructions committed +system.cpu0.committedOps 66713599 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58931600 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5354 # Number of float alu accesses +system.cpu0.num_func_calls 4809440 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7565706 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58931600 # number of integer instructions +system.cpu0.num_fp_insts 5354 # number of float instructions +system.cpu0.num_int_register_reads 107138015 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40582750 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4124 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1232 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 240777875 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25734446 # number of times the CC registers were written +system.cpu0.num_mem_refs 22316238 # number of memory refs +system.cpu0.num_load_insts 12197914 # Number of load instructions +system.cpu0.num_store_insts 10118324 # Number of store instructions +system.cpu0.num_idle_cycles 2666885275.671365 # Number of idle cycles +system.cpu0.num_busy_cycles 243163234.328635 # Number of busy cycles +system.cpu0.not_idle_fraction 0.083560 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.916440 # Percentage of idle cycles +system.cpu0.Branches 12750711 # Number of branches fetched +system.cpu0.op_class::No_OpClass 119 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 45844704 67.20% 67.20% # Class of executed instruction +system.cpu0.op_class::IntMult 57827 0.08% 67.28% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3997 0.01% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::MemRead 12197914 17.88% 85.17% # Class of executed instruction +system.cpu0.op_class::MemWrite 10118324 14.83% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 70304633 # Class of executed instruction +system.cpu0.op_class::total 68222885 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3029 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 820099 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.829843 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43241744 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 820611 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.694570 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 401.515698 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 110.314145 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.784210 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.215457 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 821400 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.702036 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43232181 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 821912 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.599525 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 174.965504 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 336.736532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.341730 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.657689 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177137427 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177137427 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11786116 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11329399 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23115515 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9461522 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9365348 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18826870 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201006 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191753 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392759 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 231308 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 212173 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443481 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 239891 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 220488 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460379 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 21247638 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20694747 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41942385 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 21448644 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 20886500 # number of overall hits -system.cpu0.dcache.overall_hits::total 42335144 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 202704 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 197921 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 400625 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 143580 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 155041 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298621 # 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number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9551716 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18823167 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190318 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202376 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392694 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 212739 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 230449 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443188 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 220738 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 239445 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460183 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20631199 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21302146 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10278276500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 19329792000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2904028500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3003756000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5907784500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2320925500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2251479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4572405000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5224954000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5255235500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10480189500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016883 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017138 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017008 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014948 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015614 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224761 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.230313 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227484 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018543 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.018121 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018341 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12964903000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 11904577000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24869480000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13768904000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12715148000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26484052000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2876770000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3059986500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5936756500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2305348000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2486099500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4791447500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5182118000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5546086000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10728204000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017073 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017035 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017054 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016065 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015217 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015635 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230689 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.224470 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227498 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017147 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019334 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018285 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016023 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016752 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016383 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018510 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019265 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018883 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13848.742423 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13901.949866 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13875.022814 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38166.370664 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43706.658239 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41042.831884 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13128.246088 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13091.368228 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13109.936430 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12710.590586 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12988.507168 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12842.105263 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016621 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016221 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019130 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018712 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15162.609022 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15163.629489 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15163.127298 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 65879.506811 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59734.344194 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62845.823620 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14006.742043 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13774.679242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13889.269308 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13606.183146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13461.169191 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13526.408451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23940.059481 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27007.575306 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25488.307810 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22375.664050 # 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average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11090149500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11460445000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22550594500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11090149500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11460445000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22550594500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11090149500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11460445000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22550594500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13291.239330 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1002,60 +1005,54 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6604 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6604 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1835 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4768 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6603 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6603 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6603 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5481 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12293.559569 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10651.112974 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6472.015315 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1651 30.12% 30.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2769 50.52% 80.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1058 19.30% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5481 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1004634564 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.995586 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000200000 -99.56% -99.56% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -2004834564 199.56% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1004634564 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3666 66.90% 66.90% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1814 33.10% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5480 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6604 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 6703 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6703 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2138 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4565 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6703 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6703 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6703 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5647 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13331.414911 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11611.737502 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7443.565061 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5646 99.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5647 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3534 62.58% 62.58% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 2113 37.42% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5647 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6703 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6604 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5480 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6703 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5647 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5480 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12084 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12350 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12016469 # DTB read hits -system.cpu1.dtb.read_misses 5667 # DTB read misses -system.cpu1.dtb.write_hits 9752712 # DTB write hits -system.cpu1.dtb.write_misses 937 # DTB write misses -system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12475099 # DTB read hits +system.cpu1.dtb.read_misses 5811 # DTB read misses +system.cpu1.dtb.write_hits 9951122 # DTB write hits +system.cpu1.dtb.write_misses 892 # DTB write misses +system.cpu1.dtb.flush_tlb 2942 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4084 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4467 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12022136 # DTB read accesses -system.cpu1.dtb.write_accesses 9753649 # DTB write accesses +system.cpu1.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12480910 # DTB read accesses +system.cpu1.dtb.write_accesses 9952014 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 21769181 # DTB hits -system.cpu1.dtb.misses 6604 # DTB misses -system.cpu1.dtb.accesses 21775785 # DTB accesses +system.cpu1.dtb.hits 22426221 # DTB hits +system.cpu1.dtb.misses 6703 # DTB misses +system.cpu1.dtb.accesses 22432924 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1085,122 +1082,119 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3234 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3234 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 677 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3234 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3234 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3234 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2430 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12793.004115 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11015.336185 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6613.791032 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 712 29.30% 29.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.04% 29.34% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.70% 57.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 477 19.63% 76.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 16 0.66% 77.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 551 22.67% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2430 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1753 72.14% 72.14% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 677 27.86% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2430 # Table walker page sizes translated +system.cpu1.itb.walker.walks 3400 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3400 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 811 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2589 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3400 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3400 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3400 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13798.698814 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12017.058980 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7032.742162 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1945 74.44% 74.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 667 25.53% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1802 68.96% 68.96% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 811 31.04% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2613 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3234 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3234 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3400 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2430 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2430 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5664 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 56973488 # ITB inst hits -system.cpu1.itb.inst_misses 3234 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2613 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2613 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6013 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58726785 # ITB inst hits +system.cpu1.itb.inst_misses 3400 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2933 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2942 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2428 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2616 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 56976722 # ITB inst accesses -system.cpu1.itb.hits 56973488 # DTB hits -system.cpu1.itb.misses 3234 # DTB misses -system.cpu1.itb.accesses 56976722 # DTB accesses -system.cpu1.numCycles 2902983091 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58730185 # ITB inst accesses +system.cpu1.itb.hits 58726785 # DTB hits +system.cpu1.itb.misses 3400 # DTB misses +system.cpu1.itb.accesses 58730185 # DTB accesses +system.cpu1.numCycles 2908727473 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55453570 # Number of instructions committed -system.cpu1.committedOps 66903769 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59172733 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5746 # Number of float alu accesses -system.cpu1.num_func_calls 4791563 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7521701 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59172733 # number of integer instructions -system.cpu1.num_fp_insts 5746 # number of float instructions -system.cpu1.num_int_register_reads 107592864 # number of times the integer registers were read -system.cpu1.num_int_register_writes 40634379 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4256 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 241317525 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25809860 # number of times the CC registers were written -system.cpu1.num_mem_refs 22393766 # number of memory refs -system.cpu1.num_load_insts 12173697 # Number of load instructions -system.cpu1.num_store_insts 10220069 # Number of store instructions -system.cpu1.num_idle_cycles 2697480671.520393 # Number of idle cycles -system.cpu1.num_busy_cycles 205502419.479607 # Number of busy cycles -system.cpu1.not_idle_fraction 0.070790 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.929210 # Percentage of idle cycles -system.cpu1.Branches 12715726 # Number of branches fetched -system.cpu1.op_class::No_OpClass 132 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45969122 67.18% 67.19% # Class of executed instruction -system.cpu1.op_class::IntMult 54656 0.08% 67.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4033 0.01% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::MemRead 12173697 17.79% 85.06% # Class of executed instruction -system.cpu1.op_class::MemWrite 10220069 14.94% 100.00% # Class of executed instruction +system.cpu1.committedInsts 57164215 # Number of instructions committed +system.cpu1.committedOps 68869811 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 60957593 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5807 # Number of float alu accesses +system.cpu1.num_func_calls 5082908 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7664467 # number of instructions that are conditional controls +system.cpu1.num_int_insts 60957593 # number of integer instructions +system.cpu1.num_fp_insts 5807 # number of float instructions +system.cpu1.num_int_register_reads 110918664 # number of times the integer registers were read +system.cpu1.num_int_register_writes 42060766 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4325 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1484 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 248948036 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26157973 # number of times the CC registers were written +system.cpu1.num_mem_refs 23089661 # number of memory refs +system.cpu1.num_load_insts 12644031 # Number of load instructions +system.cpu1.num_store_insts 10445630 # Number of store instructions +system.cpu1.num_idle_cycles 2688977301.144567 # Number of idle cycles +system.cpu1.num_busy_cycles 219750171.855433 # Number of busy cycles +system.cpu1.not_idle_fraction 0.075549 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.924451 # Percentage of idle cycles +system.cpu1.Branches 13165858 # Number of branches fetched +system.cpu1.op_class::No_OpClass 2218 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 47327866 67.15% 67.15% # Class of executed instruction +system.cpu1.op_class::IntMult 56561 0.08% 67.23% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4450 0.01% 67.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.24% # Class of executed instruction +system.cpu1.op_class::MemRead 12644031 17.94% 85.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 10445630 14.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68421709 # Class of executed instruction +system.cpu1.op_class::total 70480756 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::ReadReq 30177 # Transaction distribution +system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1225,9 +1219,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1250,9 +1244,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1293,52 +1287,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187451467 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186329023 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.079135 # Cycle average of tags in use +system.iocache.tags.replacements 36418 # number of replacements +system.iocache.tags.tagsinuse 1.084103 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309074032000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.079135 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067446 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067446 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313630728000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084103 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067756 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067756 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.tags.tag_accesses 328068 # Number of tag accesses +system.iocache.tags.data_accesses 328068 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses +system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses -system.iocache.demand_misses::total 234 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 234 # number of overall misses -system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4271859590 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4271859590 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses +system.iocache.demand_misses::total 228 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 228 # number of overall misses +system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28361877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28361877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4696967146 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4696967146 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28361877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28361877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28361877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28361877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1347,14 +1341,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117928.986031 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117928.986031 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124394.197368 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124394.197368 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129664.508227 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129664.508227 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124394.197368 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124394.197368 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1365,22 +1359,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460659590 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2460659590 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16961877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16961877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2885767146 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2885767146 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16961877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16961877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16961877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16961877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1389,262 +1383,262 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67928.986031 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67928.986031 # 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average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74394.197368 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74394.197368 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 89754 # number of replacements -system.l2c.tags.tagsinuse 64926.218037 # Cycle average of tags in use -system.l2c.tags.total_refs 4554949 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 154987 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.389233 # Average number of references to valid blocks. +system.l2c.tags.replacements 87592 # number of replacements +system.l2c.tags.tagsinuse 64865.832577 # Cycle average of tags in use +system.l2c.tags.total_refs 4555575 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 152761 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.821584 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063147 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.034183 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.084248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.042210 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989774 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6804 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40610992 # Number of tag accesses +system.l2c.tags.data_accesses 40610992 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6164 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3132 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6231 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3376 # number of ReadReq hits +system.l2c.ReadReq_hits::total 18903 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 685305 # number of Writeback hits +system.l2c.Writeback_hits::total 685305 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 80673 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 86743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167416 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 834184 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 844481 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1678665 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 252476 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 260979 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 513455 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6164 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3132 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4840380500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5181324000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11051822500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.992938 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989653 # 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mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023424 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.153298 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.195653 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063607 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.153298 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.195653 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063607 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 80150 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20784.773060 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.326909 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20788.029466 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 69500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.462058 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.406861 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.434806 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010582 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.023519 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.023191 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023352 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062674 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062674 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 124500 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70817.211949 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70784.540702 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70801.275046 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66669.360705 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65989.175430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 66281.796739 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70006.241331 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 72779.308658 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72360.123397 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 72569.272698 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67268.994431 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66474.778476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 67177.826952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67268.994431 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66474.778476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 67177.826952 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170523.098254 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184196.745465 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151463.085159 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133848.540832 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182242.319938 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154232.900794 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152127.642532 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 183352.167931 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 152591.019794 # average overall mshr uncacheable latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116781.514727 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117326.893666 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117033.472056 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120607.886822 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122228.169709 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121606.601033 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 121914.474220 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177699.603306 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178593.892462 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163786.068227 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162147.785478 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162195.207154 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162172.387546 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 170429.932045 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 170854.184528 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 163128.939173 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70721 # Transaction distribution +system.membus.trans_dist::ReadResp 70627 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 119469 # Transaction distribution -system.membus.trans_dist::CleanEvict 6488 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::Writeback 117457 # Transaction distribution +system.membus.trans_dist::CleanEvict 6338 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 129210 # Transaction distribution -system.membus.trans_dist::ReadExResp 129210 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30561 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution +system.membus.trans_dist::ReadExReq 127036 # Transaction distribution +system.membus.trans_dist::ReadExResp 127036 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30467 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 445477 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 553069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 661969 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 546371 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655265 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15578364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15741717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15304828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15468181 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18058837 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 394437 # Request fanout histogram +system.membus.pkt_size::total 17785301 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 492 # Total snoops (count) +system.membus.snoop_fanout::samples 389991 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394437 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 389991 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394437 # Request fanout histogram -system.membus.reqLayer0.occupancy 90486000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 389991 # Request fanout histogram +system.membus.reqLayer0.occupancy 90490000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1696500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 834684564 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 821977659 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 964305240 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952225245 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64480996 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64492032 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1910,63 +1910,69 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 74970 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2298377 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 5059453 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540884 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 582 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 582 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 75104 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2297700 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 803098 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1802826 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 802762 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1800707 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2769 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295883 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295883 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1698424 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 524998 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2771 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296210 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296210 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1696651 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 525960 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5081680 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2577380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18024 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34106 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7711190 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108733880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96470557 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24084 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 45196 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205273717 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180370 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5305015 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.037219 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.189299 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5076713 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581153 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18522 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35333 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7711721 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108619704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96660573 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205355921 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176740 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5302052 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018353 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.134225 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5107565 96.28% 96.28% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 197450 3.72% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5204742 98.16% 98.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 97310 1.84% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5305015 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3268607000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5302052 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3269894500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2556658000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2553998500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1277273499 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1279231000 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12003000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12013000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22807000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22931000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index fee5e3090..838105743 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1340669 # Simulator instruction rate (inst/s) -host_op_rate 2744641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34257071569 # Simulator tick rate (ticks/s) -host_mem_usage 654012 # Number of bytes of host memory used -host_seconds 149.23 # Real time elapsed on the host +host_inst_rate 1349307 # Simulator instruction rate (inst/s) +host_op_rate 2762327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34477807791 # Simulator tick rate (ticks/s) +host_mem_usage 659588 # Number of bytes of host memory used +host_seconds 148.27 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -337,9 +337,9 @@ system.cpu.itb_walker_cache.writebacks::total 545 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 106193 # number of replacements system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4345511 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4340112 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.539145 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.507414 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor @@ -359,8 +359,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39306136 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39306136 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 39255968 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39255968 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits @@ -456,42 +456,48 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks system.cpu.l2cache.writebacks::total 98168 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 886676 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880405 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 792735 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321418 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377686 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 35029733 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377675 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613331 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 49698 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18776912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002627 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051183 # Request fanout histogram +system.cpu.toL2Bus.snoops 203459 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18930673 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 18727593 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 49319 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18911114 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18776912 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18930673 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -600,7 +606,7 @@ system.membus.trans_dist::ReadResp 13903747 # Tr system.membus.trans_dist::WriteReq 13943 # Transaction distribution system.membus.trans_dist::WriteResp 13943 # Transaction distribution system.membus.trans_dist::Writeback 144835 # Transaction distribution -system.membus.trans_dist::CleanEvict 9844 # Transaction distribution +system.membus.trans_dist::CleanEvict 8392 # Transaction distribution system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution system.membus.trans_dist::ReadExReq 134360 # Transaction distribution @@ -614,11 +620,11 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 471480 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28214040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28360246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28213119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28358794 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) @@ -629,17 +635,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 14257691 # Request fanout histogram +system.membus.snoop_fanout::samples 14256770 # Request fanout histogram system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 14255995 99.99% 99.99% # Request fanout histogram +system.membus.snoop_fanout::1 14255074 99.99% 99.99% # Request fanout histogram system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 14257691 # Request fanout histogram +system.membus.snoop_fanout::total 14256770 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 2f3799b17..aa1e69b35 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.184733 # Number of seconds simulated -sim_ticks 5184732721500 # Number of ticks simulated -final_tick 5184732721500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.194921 # Number of seconds simulated +sim_ticks 5194921252500 # Number of ticks simulated +final_tick 5194921252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 808289 # Simulator instruction rate (inst/s) -host_op_rate 1558079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32570584041 # Simulator tick rate (ticks/s) -host_mem_usage 654268 # Number of bytes of host memory used -host_seconds 159.18 # Real time elapsed on the host -sim_insts 128667033 # Number of instructions simulated -sim_ops 248022101 # Number of ops (including micro ops) simulated +host_inst_rate 862150 # Simulator instruction rate (inst/s) +host_op_rate 1661827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34815163679 # Simulator tick rate (ticks/s) +host_mem_usage 660376 # Number of bytes of host memory used +host_seconds 149.21 # Real time elapsed on the host +sim_insts 128645146 # Number of instructions simulated +sim_ops 247968367 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9044928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 824576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8975232 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9898944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8133056 # Number of bytes written to this memory -system.physmem.bytes_written::total 8133056 # Number of bytes written to this memory +system.physmem.bytes_read::total 9828480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8074432 # Number of bytes written to this memory +system.physmem.bytes_written::total 8074432 # Number of bytes written to this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141327 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140238 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154671 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 127079 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127079 # Number of write requests responded to by this memory +system.physmem.num_reads::total 153570 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126163 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1744531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1909249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159187 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159187 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1568655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1568655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1568655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1727694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1891940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1554293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1554293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1554293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1744531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3477903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154671 # Number of read requests accepted -system.physmem.writeReqs 127079 # Number of write requests accepted -system.physmem.readBursts 154671 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 127079 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9888768 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu.inst 158727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1727694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3446234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 153570 # Number of read requests accepted +system.physmem.writeReqs 126163 # Number of write requests accepted +system.physmem.readBursts 153570 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 126163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9818304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 8131392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9898944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8133056 # Total written bytes from the system interface side +system.physmem.bytesWritten 8073216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9828480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8074432 # Total written bytes from the system interface side system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48348 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9772 # Per bank write bursts -system.physmem.perBankRdBursts::1 9412 # Per bank write bursts -system.physmem.perBankRdBursts::2 9829 # Per bank write bursts -system.physmem.perBankRdBursts::3 9622 # Per bank write bursts -system.physmem.perBankRdBursts::4 9563 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 9720 # Per bank write bursts -system.physmem.perBankRdBursts::7 9664 # Per bank write bursts -system.physmem.perBankRdBursts::8 9219 # Per bank write bursts -system.physmem.perBankRdBursts::9 9313 # Per bank write bursts -system.physmem.perBankRdBursts::10 9431 # Per bank write bursts -system.physmem.perBankRdBursts::11 9415 # Per bank write bursts -system.physmem.perBankRdBursts::12 9985 # Per bank write bursts -system.physmem.perBankRdBursts::13 10194 # Per bank write bursts -system.physmem.perBankRdBursts::14 10163 # Per bank write bursts -system.physmem.perBankRdBursts::15 9855 # Per bank write bursts -system.physmem.perBankWrBursts::0 8316 # Per bank write bursts -system.physmem.perBankWrBursts::1 7960 # Per bank write bursts -system.physmem.perBankWrBursts::2 8144 # Per bank write bursts -system.physmem.perBankWrBursts::3 8236 # Per bank write bursts -system.physmem.perBankWrBursts::4 8504 # Per bank write bursts -system.physmem.perBankWrBursts::5 7731 # Per bank write bursts -system.physmem.perBankWrBursts::6 7974 # Per bank write bursts -system.physmem.perBankWrBursts::7 7835 # Per bank write bursts -system.physmem.perBankWrBursts::8 7118 # Per bank write bursts -system.physmem.perBankWrBursts::9 7555 # Per bank write bursts -system.physmem.perBankWrBursts::10 7609 # Per bank write bursts -system.physmem.perBankWrBursts::11 7637 # Per bank write bursts -system.physmem.perBankWrBursts::12 8092 # Per bank write bursts -system.physmem.perBankWrBursts::13 8095 # Per bank write bursts -system.physmem.perBankWrBursts::14 8240 # Per bank write bursts -system.physmem.perBankWrBursts::15 8007 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48373 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9606 # Per bank write bursts +system.physmem.perBankRdBursts::1 9083 # Per bank write bursts +system.physmem.perBankRdBursts::2 10021 # Per bank write bursts +system.physmem.perBankRdBursts::3 9578 # Per bank write bursts +system.physmem.perBankRdBursts::4 9425 # Per bank write bursts +system.physmem.perBankRdBursts::5 9133 # Per bank write bursts +system.physmem.perBankRdBursts::6 9428 # Per bank write bursts +system.physmem.perBankRdBursts::7 9379 # Per bank write bursts +system.physmem.perBankRdBursts::8 9296 # Per bank write bursts +system.physmem.perBankRdBursts::9 9532 # Per bank write bursts +system.physmem.perBankRdBursts::10 9485 # Per bank write bursts +system.physmem.perBankRdBursts::11 9788 # Per bank write bursts +system.physmem.perBankRdBursts::12 9982 # Per bank write bursts +system.physmem.perBankRdBursts::13 10070 # Per bank write bursts +system.physmem.perBankRdBursts::14 9926 # Per bank write bursts +system.physmem.perBankRdBursts::15 9679 # Per bank write bursts +system.physmem.perBankWrBursts::0 8208 # Per bank write bursts +system.physmem.perBankWrBursts::1 7344 # Per bank write bursts +system.physmem.perBankWrBursts::2 8031 # Per bank write bursts +system.physmem.perBankWrBursts::3 7623 # Per bank write bursts +system.physmem.perBankWrBursts::4 7645 # Per bank write bursts +system.physmem.perBankWrBursts::5 7565 # Per bank write bursts +system.physmem.perBankWrBursts::6 7708 # Per bank write bursts +system.physmem.perBankWrBursts::7 7791 # Per bank write bursts +system.physmem.perBankWrBursts::8 7759 # Per bank write bursts +system.physmem.perBankWrBursts::9 7930 # Per bank write bursts +system.physmem.perBankWrBursts::10 7732 # Per bank write bursts +system.physmem.perBankWrBursts::11 7853 # Per bank write bursts +system.physmem.perBankWrBursts::12 8038 # Per bank write bursts +system.physmem.perBankWrBursts::13 8512 # Per bank write bursts +system.physmem.perBankWrBursts::14 8378 # Per bank write bursts +system.physmem.perBankWrBursts::15 8027 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 5184732588500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5194921069000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154671 # Read request sizes (log2) +system.physmem.readPktSize::6 153570 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 127079 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126163 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -152,189 +152,188 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6964 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 55882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.466912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.971568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.231986 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19566 35.01% 35.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13855 24.79% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5752 10.29% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3280 5.87% 75.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2436 4.36% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1597 2.86% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1106 1.98% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 958 1.71% 86.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7332 13.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 55882 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5902 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.177906 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 623.301246 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5901 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::51 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 55967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.678668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.248377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.031309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19371 34.61% 34.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13720 24.51% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6335 11.32% 70.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3428 6.13% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2404 4.30% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1641 2.93% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1130 2.02% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 964 1.72% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6974 12.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 55967 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5838 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.276465 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 626.709863 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5837 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5902 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5902 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.527109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.363013 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.814592 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4841 82.02% 82.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 49 0.83% 82.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 261 4.42% 87.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 70 1.19% 88.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 69 1.17% 89.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 251 4.25% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.37% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 13 0.22% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.25% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 235 3.98% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.14% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.46% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5902 # Writes before turning the bus around for reads -system.physmem.totQLat 1454171981 # Total ticks spent queuing -system.physmem.totMemAccLat 4351271981 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9411.39 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5838 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5838 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.607400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.425561 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.518520 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4794 82.12% 82.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.88% 84.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 38 0.65% 84.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 229 3.92% 88.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 28 0.48% 89.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 201 3.44% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 72 1.23% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 93.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.21% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 30 0.51% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.10% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 233 3.99% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 31 0.53% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.27% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5838 # Writes before turning the bus around for reads +system.physmem.totQLat 1519267484 # Total ticks spent queuing +system.physmem.totMemAccLat 4395723734 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 767055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9903.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28161.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28653.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 126926 # Number of row buffer hits during reads -system.physmem.writeRowHits 98756 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.71 # Row buffer hit rate for writes -system.physmem.avgGap 18401890.29 # Average gap between requests -system.physmem.pageHitRate 80.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 207522000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 113231250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 600100800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 419256000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 134001495225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2993293881750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3467276945505 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.747605 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4979520185732 # Time in different power states -system.physmem_0.memoryStateTime::REF 173129580000 # Time in different power states +system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing +system.physmem.readRowHits 125316 # Number of row buffer hits during reads +system.physmem.writeRowHits 98271 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.89 # Row buffer hit rate for writes +system.physmem.avgGap 18570998.31 # Average gap between requests +system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 205775640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 112278375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 590093400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 401209200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 136710410535 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2997028289250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3474354711360 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.798995 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4985717898976 # Time in different power states +system.physmem_0.memoryStateTime::REF 173469660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32082834268 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35728624774 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214945920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117282000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 605085000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 404047440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134530881300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2992829508000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3467343208140 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.760386 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4978746411720 # Time in different power states -system.physmem_1.memoryStateTime::REF 173129580000 # Time in different power states +system.physmem_1.actEnergy 217334880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118585500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 606504600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 416203920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 137303657415 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2996507897250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3474476838525 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.822504 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4984854152228 # Time in different power states +system.physmem_1.memoryStateTime::REF 173469660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32855777030 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36597268272 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10369465443 # number of cpu cycles simulated +system.cpu.numCycles 10389842505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128667033 # Number of instructions committed -system.cpu.committedOps 248022101 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232599125 # Number of integer alu accesses +system.cpu.committedInsts 128645146 # Number of instructions committed +system.cpu.committedOps 247968367 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232546073 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2317363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23194478 # number of instructions that are conditional controls -system.cpu.num_int_insts 232599125 # number of integer instructions +system.cpu.num_func_calls 2315361 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23194066 # number of instructions that are conditional controls +system.cpu.num_int_insts 232546073 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 435753384 # number of times the integer registers were read -system.cpu.num_int_register_writes 198362025 # number of times the integer registers were written +system.cpu.num_int_register_reads 435625867 # number of times the integer registers were read +system.cpu.num_int_register_writes 198317571 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133133176 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95670461 # number of times the CC registers were written -system.cpu.num_mem_refs 22356642 # number of memory refs -system.cpu.num_load_insts 13946240 # Number of load instructions -system.cpu.num_store_insts 8410402 # Number of store instructions -system.cpu.num_idle_cycles 9769457503.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600007939.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057863 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942137 # Percentage of idle cycles -system.cpu.Branches 26370667 # Number of branches fetched -system.cpu.op_class::No_OpClass 172538 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225235379 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140393 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123647 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 133116487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95666128 # number of times the CC registers were written +system.cpu.num_mem_refs 22339099 # number of memory refs +system.cpu.num_load_insts 13935933 # Number of load instructions +system.cpu.num_store_insts 8403166 # Number of store instructions +system.cpu.num_idle_cycles 9774871363.998119 # Number of idle cycles +system.cpu.num_busy_cycles 614971141.001882 # Number of busy cycles +system.cpu.not_idle_fraction 0.059190 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940810 # Percentage of idle cycles +system.cpu.Branches 26367781 # Number of branches fetched +system.cpu.op_class::No_OpClass 172241 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225200251 90.82% 90.89% # Class of executed instruction +system.cpu.op_class::IntMult 140056 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123237 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -361,215 +360,215 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13941273 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8410402 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13930961 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8403166 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248023648 # Class of executed instruction +system.cpu.op_class::total 247969928 # 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number of replacements +system.cpu.dcache.tags.tagsinuse 511.995361 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20131143 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623840 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.397245 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995361 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88751069 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88751069 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12012436 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12012436 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8077606 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8077606 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59170 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59170 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8402408 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8402408 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461708 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461708 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21320665 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21320665 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21782373 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21782373 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070119 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070119 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038656 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871845 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871845 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057720 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057720 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074976 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074976 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14144.598105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14144.598105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37337.758016 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37337.758016 # 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number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20070308 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20070308 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20128970 # number of overall hits +system.cpu.dcache.overall_hits::total 20128970 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906883 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906883 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325772 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403210 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403210 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232655 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1232655 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1635865 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8395187 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8395187 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21302963 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21302963 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21764835 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21764835 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070259 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070259 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038805 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038805 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872991 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872991 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075161 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075161 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.902098 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.902098 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56160.007542 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56160.007542 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25835.221515 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25835.221515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19467.324612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19467.324612 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15094 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 441 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.527778 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.226757 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11904745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11904745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11312729479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11312729479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5814985000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5814985000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23217474979 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23217474979 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29032459979 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29032459979 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684333500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684333500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622247500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622247500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97306581000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 97306581000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070097 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070097 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037574 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037574 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871772 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871772 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057280 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057280 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074544 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074544 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.672181 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.672181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35832.774736 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35832.774736 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14447.024129 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14447.024129 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19011.363005 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19011.363005 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17879.927020 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17879.927020 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.431581 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.431581 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188433.996838 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188433.996838 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165806.023480 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165806.023480 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586874 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 586874 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12641489000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12641489000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17000944477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17000944477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6508610000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6508610000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29642433477 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29642433477 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36151043477 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36151043477 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684331000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684331000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622740500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622740500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97307071500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 97307071500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070236 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872913 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872913 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074711 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074711 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.982457 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.982457 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53749.089405 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53749.089405 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16143.426907 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16143.426907 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24239.596986 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24239.596986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22232.197983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22232.197983 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.427218 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.427218 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188415.265805 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188415.265805 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165805.729168 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165805.729168 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7782 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.044171 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13071 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7797 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.676414 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5158049844500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.044171 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315261 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315261 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 7724 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13169 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7738 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.701861 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5166372049500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53116 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53116 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13073 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13073 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13073 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13073 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13073 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13073 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8990 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8990 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8990 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8990 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8990 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8990 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97324000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97324000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97324000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 97324000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97324000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 97324000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22063 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22063 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22063 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22063 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22063 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22063 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407470 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407470 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407470 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407470 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407470 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407470 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10825.806452 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10825.806452 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10825.806452 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13186 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13186 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13186 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13186 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13186 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13186 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8927 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8927 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8927 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8927 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8927 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8927 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97243000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97243000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97243000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 97243000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97243000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 97243000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22113 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22113 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22113 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22113 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22113 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22113 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403699 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403699 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403699 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403699 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403699 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403699 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10893.133191 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10893.133191 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10893.133191 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,86 +577,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8990 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8990 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8990 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8990 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8990 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8990 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88334000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88334000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88334000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88334000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88334000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88334000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407470 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407470 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407470 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9825.806452 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2877 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2877 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8927 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8927 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8927 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8927 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8927 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8927 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88316000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88316000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88316000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88316000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88316000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88316000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.403699 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.403699 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.403699 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9893.133191 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 792637 # number of replacements -system.cpu.icache.tags.tagsinuse 510.330403 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144952019 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 793149 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.755093 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161555480500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.330403 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996739 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996739 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 789867 # number of replacements +system.cpu.icache.tags.tagsinuse 510.214824 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144930127 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 790379 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 183.367887 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 164495636500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.214824 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996513 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146538331 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146538331 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144952019 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144952019 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144952019 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144952019 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144952019 # number of overall hits -system.cpu.icache.overall_hits::total 144952019 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 793156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 793156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 793156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 793156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 793156 # number of overall misses -system.cpu.icache.overall_misses::total 793156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11221653000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11221653000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11221653000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11221653000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11221653000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11221653000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145745175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145745175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145745175 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145745175 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145745175 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145745175 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005442 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005442 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005442 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005442 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005442 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005442 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14148.103274 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14148.103274 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14148.103274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14148.103274 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146510899 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146510899 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144930127 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144930127 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144930127 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144930127 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144930127 # number of overall hits +system.cpu.icache.overall_hits::total 144930127 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 790386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 790386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 790386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 790386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 790386 # number of overall misses +system.cpu.icache.overall_misses::total 790386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11833714500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11833714500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11833714500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11833714500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11833714500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11833714500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145720513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145720513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145720513 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145720513 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145720513 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145720513 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005424 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005424 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005424 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005424 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005424 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005424 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14972.069976 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14972.069976 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14972.069976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14972.069976 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -666,88 +665,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793156 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793156 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793156 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793156 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793156 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793156 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10428497000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10428497000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10428497000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10428497000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10428497000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10428497000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005442 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005442 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005442 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13148.103274 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13148.103274 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790386 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 790386 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 790386 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 790386 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 790386 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 790386 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11043328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11043328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11043328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11043328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11043328500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11043328500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005424 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005424 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005424 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13972.069976 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13972.069976 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3538 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.060279 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7930 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3549 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.234432 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161245744500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.060279 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191267 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191267 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3784 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.071212 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7587 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3797 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.998156 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5168596607500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071212 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191951 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191951 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29062 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29062 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7929 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7929 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29077 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29077 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7587 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7587 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7931 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7931 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7931 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7931 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4400 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4400 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4400 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4400 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4400 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4400 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45407000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45407000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45407000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 45407000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45407000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 45407000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12329 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12329 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7589 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7589 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7589 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7589 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4633 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4633 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4633 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4633 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4633 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4633 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48911500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48911500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48911500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 48911500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48911500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 48911500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12331 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12331 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12331 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12331 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356882 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356882 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356824 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.356824 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356824 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.356824 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10319.772727 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10319.772727 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10319.772727 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.379133 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.379133 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.379071 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.379071 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.379071 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.379071 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10557.198360 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10557.198360 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10557.198360 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,169 +755,169 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 796 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 796 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4400 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4400 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4400 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4400 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 41007000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 41007000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 41007000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 41007000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 41007000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 41007000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356882 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356882 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9319.772727 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 721 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 721 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4633 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4633 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4633 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4633 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4633 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4633 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 44278500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 44278500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 44278500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 44278500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 44278500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 44278500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.379133 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.379133 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.379071 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.379071 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9557.198360 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87263 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64757.225173 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4369524 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151965 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 28.753489 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 86240 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64592.333945 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4367637 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 150989 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 28.926856 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50419.617435 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.145028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3328.329800 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11009.132909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.769342 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50133.527739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3457.643805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11001.015544 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.764977 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050786 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.167986 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.988117 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64702 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5302 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56392 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987274 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39224493 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39224493 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1541775 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1541775 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 307 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 307 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199754 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199754 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 780246 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 780246 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6724 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3018 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1278797 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1288539 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6724 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3018 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 780246 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1478551 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2268539 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6724 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3018 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 780246 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1478551 # number of overall hits -system.cpu.l2cache.overall_hits::total 2268539 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1367 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1367 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113781 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113781 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12897 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 12897 # number of ReadCleanReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.167862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.985601 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64749 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56598 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987991 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 39213781 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39213781 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1544059 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1544059 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 298 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 298 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 201469 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 201469 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 777488 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 777488 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6514 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3101 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280565 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1290180 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6514 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3101 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 777488 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1482034 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2269137 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6514 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3101 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777488 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1482034 # number of overall hits +system.cpu.l2cache.overall_hits::total 2269137 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1394 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1394 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 112654 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 112654 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12885 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 12885 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28476 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 28481 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28510 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 28515 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12897 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142257 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3452410000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 587500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1562149500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16617922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18180659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1562149500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16617922500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18180659500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 87522404000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 87522404000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2462660500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2462660500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89985064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89985064500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816607 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816607 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362897 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362897 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016261 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021783 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021625 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.064017 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.064017 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21240.673007 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21240.673007 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66412.599643 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66412.599643 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70879.002869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70879.002869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 70300 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71770.350471 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71770.092342 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.424600 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.424600 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176933.996838 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176933.996838 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.728901 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.728901 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823877 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823877 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358630 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358630 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016302 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021624 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063575 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063575 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71385.581062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71385.581062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 116872.015197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 116872.015197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121074.096808 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121073.470103 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.423727 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.423727 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176915.265805 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176915.265805 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.444651 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.444651 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4854729 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2424193 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1088 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1088 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 572954 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2687857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1668857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 884964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 793156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322272 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2686987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1670227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 790386 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378925 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6040657 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20226 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8448782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50761152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203819691 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 629120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255454379 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 189246 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5626152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.032703 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.177859 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2370613 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6047740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8447236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50583872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204138427 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 601024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255568251 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 188441 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5624579 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.080591 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5442159 96.73% 96.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 183993 3.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5604820 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14130 0.25% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5629 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5626152 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4269812500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5624579 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4271820500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 588787 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1189734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1185579000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3013374987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3016848998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6600000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6949500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13485000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13390500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 226549 # Transaction distribution -system.iobus.trans_dist::ReadResp 226549 # Transaction distribution +system.iobus.trans_dist::ReadReq 226550 # Transaction distribution +system.iobus.trans_dist::ReadResp 226550 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 57726 # Transaction distribution -system.iobus.trans_dist::MessageReq 1652 # Transaction distribution -system.iobus.trans_dist::MessageResp 1652 # Transaction distribution +system.iobus.trans_dist::MessageReq 1654 # Transaction distribution +system.iobus.trans_dist::MessageResp 1654 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1095,11 +1100,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 473420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 571854 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 571860 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1119,12 +1124,12 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 242990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276902 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3939784 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276918 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1160,54 +1165,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 242362178 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 240989862 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 462414000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50042000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50044000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47510 # number of replacements -system.iocache.tags.tagsinuse 0.095938 # Cycle average of tags in use +system.iocache.tags.replacements 47511 # number of replacements +system.iocache.tags.tagsinuse 0.108299 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5046145075000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095938 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005996 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005996 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5048321264000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108299 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006769 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428085 # Number of tag accesses -system.iocache.tags.data_accesses 428085 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 845 # number of ReadReq misses -system.iocache.ReadReq_misses::total 845 # number of ReadReq misses +system.iocache.tags.tag_accesses 428094 # Number of tag accesses +system.iocache.tags.data_accesses 428094 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses +system.iocache.ReadReq_misses::total 846 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 845 # number of demand (read+write) misses -system.iocache.demand_misses::total 845 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 845 # number of overall misses -system.iocache.overall_misses::total 845 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 134017694 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 134017694 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5509470484 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5509470484 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 134017694 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 134017694 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 134017694 # number of overall miss cycles -system.iocache.overall_miss_latency::total 134017694 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 845 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 845 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses +system.iocache.demand_misses::total 846 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses +system.iocache.overall_misses::total 846 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144199688 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144199688 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6059543174 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6059543174 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144199688 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144199688 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144199688 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144199688 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 845 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 845 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 845 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 845 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1216,40 +1221,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158600.821302 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 117925.310017 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117925.310017 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 158600.821302 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 158600.821302 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 170448.803783 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129699.126156 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129699.126156 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 170448.803783 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 170448.803783 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 693 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 36 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.178571 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 19.250000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 845 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 845 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 845 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 845 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 845 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 91767694 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3173470484 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3173470484 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 91767694 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 91767694 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 101899688 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3723543174 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3723543174 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 101899688 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 101899688 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1258,73 +1263,73 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108600.821302 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67925.310017 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67925.310017 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 120448.803783 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79699.126156 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79699.126156 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 572954 # Transaction distribution -system.membus.trans_dist::ReadResp 615177 # Transaction distribution -system.membus.trans_dist::WriteReq 13916 # Transaction distribution -system.membus.trans_dist::WriteResp 13916 # Transaction distribution -system.membus.trans_dist::Writeback 127079 # Transaction distribution -system.membus.trans_dist::CleanEvict 7222 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2154 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1646 # Transaction distribution -system.membus.trans_dist::ReadExReq 113502 # Transaction distribution -system.membus.trans_dist::ReadExResp 113502 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42223 # Transaction distribution -system.membus.trans_dist::MessageReq 1652 # Transaction distribution -system.membus.trans_dist::MessageResp 1652 # Transaction distribution +system.membus.trans_dist::ReadResp 615200 # Transaction distribution +system.membus.trans_dist::WriteReq 13920 # Transaction distribution +system.membus.trans_dist::WriteResp 13920 # Transaction distribution +system.membus.trans_dist::Writeback 126163 # Transaction distribution +system.membus.trans_dist::CleanEvict 7113 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2165 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1671 # Transaction distribution +system.membus.trans_dist::ReadExReq 112377 # Transaction distribution +system.membus.trans_dist::ReadExResp 112377 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42246 # Transaction distribution +system.membus.trans_dist::MessageReq 1654 # Transaction distribution +system.membus.trans_dist::MessageResp 1654 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 473420 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 400152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1573892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1718963 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 396961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1570709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1715783 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242990 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15016960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16660587 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400653 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14887872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16531515 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19682235 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1580 # Total snoops (count) -system.membus.snoop_fanout::samples 927896 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001780 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.042157 # Request fanout histogram +system.membus.pkt_size::total 19553171 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1565 # Total snoops (count) +system.membus.snoop_fanout::samples 925791 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001787 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.042230 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 926244 99.82% 99.82% # Request fanout histogram -system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 924137 99.82% 99.82% # Request fanout histogram +system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 927896 # Request fanout histogram -system.membus.reqLayer0.occupancy 359896000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 925791 # Request fanout histogram +system.membus.reqLayer0.occupancy 359890000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 527973000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 527983500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 848970266 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 843164843 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2157850870 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2152042345 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85904679 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85908558 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |