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authorAndreas Hansson <andreas.hansson@arm.com>2013-01-31 07:49:16 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2013-01-31 07:49:16 -0500
commitfce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch)
tree26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/quick/fs
parentc4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff)
downloadgem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/quick/fs')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt6
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt70
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt2046
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt1134
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt2
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt2
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt2040
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt1014
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt2
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt40
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt1456
-rw-r--r--tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt580
12 files changed, 4243 insertions, 4149 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 6b719babe..a5d2b415b 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -197,7 +197,7 @@ system.physmem.avgRdBW 0.00 # Av
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
@@ -440,8 +440,8 @@ system.cpu0.num_fp_register_writes 150767 # nu
system.cpu0.num_mem_refs 15124548 # number of memory refs
system.cpu0.num_load_insts 9178366 # Number of load instructions
system.cpu0.num_store_insts 5946182 # Number of store instructions
-system.cpu0.num_idle_cycles 3683454681.836560 # Number of idle cycles
-system.cpu0.num_busy_cycles 57196201.163440 # Number of busy cycles
+system.cpu0.num_idle_cycles 3683454681.064560 # Number of idle cycles
+system.cpu0.num_busy_cycles 57196201.935440 # Number of busy cycles
system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 2435d9264..178493c15 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -187,7 +187,7 @@ system.physmem.avgRdBW 0.00 # Av
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
@@ -302,8 +302,8 @@ system.cpu.num_fp_register_writes 166520 # nu
system.cpu.num_mem_refs 16115688 # number of memory refs
system.cpu.num_load_insts 9747503 # Number of load instructions
system.cpu.num_store_insts 6368185 # Number of store instructions
-system.cpu.num_idle_cycles 3598606250.520791 # Number of idle cycles
-system.cpu.num_busy_cycles 60054827.479209 # Number of busy cycles
+system.cpu.num_idle_cycles 3598606249.772791 # Number of idle cycles
+system.cpu.num_busy_cycles 60054828.227209 # Number of busy cycles
system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983586 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
@@ -608,5 +608,69 @@ system.cpu.dcache.cache_copies 0 # nu
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
system.cpu.dcache.writebacks::total 833491 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2042707 # number of replacements
+system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
+system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
+system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
+system.cpu.dcache.writebacks::total 833491 # number of writebacks
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 0e2cc710f..e93e66fed 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,104 +1,104 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.950814 # Number of seconds simulated
-sim_ticks 1950813955500 # Number of ticks simulated
-final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.952724 # Number of seconds simulated
+sim_ticks 1952724269500 # Number of ticks simulated
+final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 720692 # Simulator instruction rate (inst/s)
-host_op_rate 720692 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23054537293 # Simulator tick rate (ticks/s)
-host_mem_usage 378432 # Number of bytes of host memory used
-host_seconds 84.62 # Real time elapsed on the host
-sim_insts 60983017 # Number of instructions simulated
-sim_ops 60983017 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory
+host_inst_rate 1678586 # Simulator instruction rate (inst/s)
+host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 53851852439 # Simulator tick rate (ticks/s)
+host_mem_usage 333452 # Number of bytes of host memory used
+host_seconds 36.26 # Real time elapsed on the host
+sim_insts 60867235 # Number of instructions simulated
+sim_ops 60867235 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 448191 # Total number of read requests seen
-system.physmem.writeReqs 120414 # Total number of write requests seen
-system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28684224 # Total number of bytes read from memory
-system.physmem.bytesWritten 7706496 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis
+system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 448125 # Total number of read requests seen
+system.physmem.writeReqs 120294 # Total number of write requests seen
+system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28680000 # Total number of bytes read from memory
+system.physmem.bytesWritten 7698816 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis
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+system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1950760240000 # Total gap between requests
+system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1952670553500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 448191 # Categorize read packet sizes
+system.physmem.readPktSize::6 448125 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 120944 # categorize write packet sizes
+system.physmem.writePktSize::6 121700 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -116,30 +116,30 @@ system.physmem.neitherpktsize::2 0 # ca
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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@@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
@@ -521,12 +521,12 @@ system.iocache.overall_misses::tsunami.ide 41728 #
system.iocache.overall_misses::total 41728 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10634917806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10634917806 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10656186804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10656186804 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10656186804 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10656186804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@@ -545,17 +545,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255942.380776 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 255942.380776 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 255372.574866 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 255372.574866 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 284837 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -569,14 +569,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41728
system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@@ -585,14 +585,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -610,22 +610,22 @@ system.cpu0.dtb.fetch_hits 0 # IT
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 7424685 # DTB read hits
+system.cpu0.dtb.read_hits 7490982 # DTB read hits
system.cpu0.dtb.read_misses 7443 # DTB read misses
system.cpu0.dtb.read_acv 210 # DTB read access violations
system.cpu0.dtb.read_accesses 490673 # DTB read accesses
-system.cpu0.dtb.write_hits 5011105 # DTB write hits
+system.cpu0.dtb.write_hits 5068153 # DTB write hits
system.cpu0.dtb.write_misses 813 # DTB write misses
system.cpu0.dtb.write_acv 134 # DTB write access violations
system.cpu0.dtb.write_accesses 187452 # DTB write accesses
-system.cpu0.dtb.data_hits 12435790 # DTB hits
+system.cpu0.dtb.data_hits 12559135 # DTB hits
system.cpu0.dtb.data_misses 8256 # DTB misses
system.cpu0.dtb.data_acv 344 # DTB access violations
system.cpu0.dtb.data_accesses 678125 # DTB accesses
-system.cpu0.itb.fetch_hits 3481701 # ITB hits
+system.cpu0.itb.fetch_hits 3503456 # ITB hits
system.cpu0.itb.fetch_misses 3871 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
-system.cpu0.itb.fetch_accesses 3485572 # ITB accesses
+system.cpu0.itb.fetch_accesses 3507327 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
@@ -638,55 +638,55 @@ system.cpu0.itb.data_hits 0 # DT
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3900399041 # number of cpu cycles simulated
+system.cpu0.numCycles 3904305293 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 47350784 # Number of instructions committed
-system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses
-system.cpu0.num_func_calls 1188579 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 43919786 # number of integer instructions
-system.cpu0.num_fp_insts 206365 # number of float instructions
-system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written
-system.cpu0.num_mem_refs 12475691 # number of memory refs
-system.cpu0.num_load_insts 7451626 # Number of load instructions
-system.cpu0.num_store_insts 5024065 # Number of store instructions
-system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles
-system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles
+system.cpu0.committedInsts 47706703 # Number of instructions committed
+system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses
+system.cpu0.num_func_calls 1201591 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 44241786 # number of integer instructions
+system.cpu0.num_fp_insts 211423 # number of float instructions
+system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written
+system.cpu0.num_mem_refs 12599388 # number of memory refs
+system.cpu0.num_load_insts 7518173 # Number of load instructions
+system.cpu0.num_store_insts 5081215 # Number of store instructions
+system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles
+system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
@@ -718,37 +718,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed
-system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed
-system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed
-system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed
+system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed
+system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed
+system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed
+system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 147588 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches
+system.cpu0.kern.callpal::total 149953 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1283
system.cpu0.kern.mode_good::user 1283
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3025 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3075 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
@@ -780,51 +780,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -833,112 +833,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.LoadLockedReq_hits::total 140562 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148239 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 148239 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 11069133 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 11069133 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 11069133 # number of overall hits
+system.cpu0.dcache.overall_hits::total 11069133 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 939643 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 939643 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 251886 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 251886 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13649 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 13649 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5418 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 5418 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 1191529 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1191529 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 1191529 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1191529 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 21121102500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 21121102500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7642676000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 7642676000 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149168500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 149168500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 41236000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 41236000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 28763778500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 28763778500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 28763778500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 28763778500 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 7349204 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 7349204 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 4911458 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 4911458 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154211 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 154211 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153657 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 153657 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 12260662 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 12260662 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 12260662 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 12260662 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127856 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.127856 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051285 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.051285 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088509 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088509 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035260 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035260 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097183 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.097183 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097183 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.097183 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22477.794758 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 22477.794758 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30341.805420 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 30341.805420 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10928.895890 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10928.895890 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7610.926541 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7610.926541 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 24140.225290 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 24140.225290 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -947,62 +947,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 672345 # number of writebacks
-system.cpu0.dcache.writebacks::total 672345 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933038 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 933038 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249274 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 249274 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13435 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13435 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182312 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 1182312 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182312 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks
+system.cpu0.dcache.writebacks::total 680601 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13649 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5418 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 5418 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191529 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1191529 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191529 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1191529 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19241816500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19241816500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7138904000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7138904000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@@ -1014,22 +1014,22 @@ system.cpu1.dtb.fetch_hits 0 # IT
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2500361 # DTB read hits
+system.cpu1.dtb.read_hits 2417694 # DTB read hits
system.cpu1.dtb.read_misses 2992 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 239363 # DTB read accesses
-system.cpu1.dtb.write_hits 1820984 # DTB write hits
+system.cpu1.dtb.write_hits 1754404 # DTB write hits
system.cpu1.dtb.write_misses 341 # DTB write misses
system.cpu1.dtb.write_acv 29 # DTB write access violations
system.cpu1.dtb.write_accesses 105247 # DTB write accesses
-system.cpu1.dtb.data_hits 4321345 # DTB hits
+system.cpu1.dtb.data_hits 4172098 # DTB hits
system.cpu1.dtb.data_misses 3333 # DTB misses
system.cpu1.dtb.data_acv 29 # DTB access violations
system.cpu1.dtb.data_accesses 344610 # DTB accesses
-system.cpu1.itb.fetch_hits 1990033 # ITB hits
+system.cpu1.itb.fetch_hits 1961503 # ITB hits
system.cpu1.itb.fetch_misses 1216 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 1991249 # ITB accesses
+system.cpu1.itb.fetch_accesses 1962719 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
@@ -1042,51 +1042,51 @@ system.cpu1.itb.data_hits 0 # DT
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3901627911 # number of cpu cycles simulated
+system.cpu1.numCycles 3905448539 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 13632233 # Number of instructions committed
-system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses
-system.cpu1.num_func_calls 426713 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 12571690 # number of integer instructions
-system.cpu1.num_fp_insts 180459 # number of float instructions
-system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written
-system.cpu1.num_mem_refs 4345653 # number of memory refs
-system.cpu1.num_load_insts 2515108 # Number of load instructions
-system.cpu1.num_store_insts 1830545 # Number of store instructions
-system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles
-system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles
+system.cpu1.committedInsts 13160532 # Number of instructions committed
+system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses
+system.cpu1.num_func_calls 411397 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 12141335 # number of integer instructions
+system.cpu1.num_fp_insts 171917 # number of float instructions
+system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written
+system.cpu1.num_mem_refs 4195541 # number of memory refs
+system.cpu1.num_load_insts 2431931 # Number of load instructions
+system.cpu1.num_store_insts 1763610 # Number of store instructions
+system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles
+system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl
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+system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
@@ -1102,81 +1102,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 104 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed
-system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed
-system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed
+system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed
+system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed
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+system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed
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system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 73828 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches
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system.cpu1.kern.mode_switch::user 465 # number of protection mode switches
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-system.cpu1.kern.mode_good::kernel 915
+system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches
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system.cpu1.kern.mode_good::user 465
-system.cpu1.kern.mode_good::idle 450
-system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::idle 424
+system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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-system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 2086 # number of times the context was actually changed
-system.cpu1.icache.replacements 328646 # number of replacements
-system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use
-system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit.
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-system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy
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-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024142 # miss rate for ReadReq accesses
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-system.cpu1.icache.overall_miss_rate::total 0.024142 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13203.569931 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13203.569931 # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::total 13203.569931 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency
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+system.cpu1.kern.swap_context 1984 # number of times the context was actually changed
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+system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit.
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+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles
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+system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses
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+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1185,112 +1185,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329194 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 329194 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 329194 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 329194 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 329194 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 329194 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688148000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688148000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688148000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 3688148000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688148000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 3688148000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024142 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.024142 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.024142 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11203.569931 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315439 # number of ReadReq MSHR misses
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+system.cpu1.icache.overall_mshr_misses::cpu1.inst 315439 # number of overall MSHR misses
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+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3538039000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 3538039000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses
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+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1299,62 +1299,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5817 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 5817 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 180006 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 180006 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 180006 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 180006 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1192562500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1192562500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 960154000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 960154000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63672000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63672000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30558000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30558000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2152716500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2152716500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2152716500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2152716500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 712390500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index e3ca77030..37fa2c1e1 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,94 +1,94 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.910582 # Number of seconds simulated
-sim_ticks 1910582068000 # Number of ticks simulated
-final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.910548 # Number of seconds simulated
+sim_ticks 1910547559000 # Number of ticks simulated
+final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 951839 # Simulator instruction rate (inst/s)
-host_op_rate 951839 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32401800424 # Simulator tick rate (ticks/s)
-host_mem_usage 374212 # Number of bytes of host memory used
-host_seconds 58.97 # Real time elapsed on the host
-sim_insts 56125446 # Number of instructions simulated
-sim_ops 56125446 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory
+host_inst_rate 1284259 # Simulator instruction rate (inst/s)
+host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 43720523895 # Simulator tick rate (ticks/s)
+host_mem_usage 330356 # Number of bytes of host memory used
+host_seconds 43.70 # Real time elapsed on the host
+sim_insts 56120911 # Number of instructions simulated
+sim_ops 56120911 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 442975 # Total number of read requests seen
-system.physmem.writeReqs 115503 # Total number of write requests seen
-system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28350400 # Total number of bytes read from memory
-system.physmem.bytesWritten 7392192 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q
+system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 443146 # Total number of read requests seen
+system.physmem.writeReqs 115693 # Total number of write requests seen
+system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28361344 # Total number of bytes read from memory
+system.physmem.bytesWritten 7404352 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 27723 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27886 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27600 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27483 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27641 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27656 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7552 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7244 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7137 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6901 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7584 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 6832 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7257 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7441 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7265 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7126 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7165 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7126 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 27562 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27598 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27733 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27646 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27564 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7032 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7167 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7067 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7154 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7184 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7113 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 404 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1910570168000 # Total gap between requests
+system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1910535659000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 442975 # Categorize read packet sizes
+system.physmem.readPktSize::6 443146 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 115907 # categorize write packet sizes
+system.physmem.writePktSize::6 117758 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -109,27 +109,27 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 130 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 404639 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 7455 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5269 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2334 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2835 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2403 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1793 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2009 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1658 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1931 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1592 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1535 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1623 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1782 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1204 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1459 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 903 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 267 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 101 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 402456 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4645 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 3680 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3123 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2721 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2721 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2666 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2589 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1544 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1454 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1412 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1360 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1368 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1379 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1491 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 926 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
@@ -142,69 +142,69 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4142 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4753 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2804911869 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 10779125869 # Sum of mem lat for all requests
-system.physmem.totBusLat 1771696000 # Total cycles spent in databus access
-system.physmem.totBankLat 6202518000 # Total cycles spent in bank access
-system.physmem.avgQLat 6332.72 # Average queueing delay per request
-system.physmem.avgBankLat 14003.57 # Average bank access latency per request
-system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24336.29 # Average memory access latency
+system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests
+system.physmem.totBusLat 2215505000 # Total cycles spent in databus access
+system.physmem.totBankLat 6296675000 # Total cycles spent in bank access
+system.physmem.avgQLat 10647.84 # Average queueing delay per request
+system.physmem.avgBankLat 14210.47 # Average bank access latency per request
+system.physmem.avgBusLat 5000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 29858.31 # Average memory access latency
system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s
+system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.12 # Data bus utilization in percentage
+system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 14.48 # Average write queue length over time
-system.physmem.readRowHits 423327 # Number of row buffer hits during reads
-system.physmem.writeRowHits 74914 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.58 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 64.86 # Row buffer hit rate for writes
-system.physmem.avgGap 3421030.31 # Average gap between requests
+system.physmem.avgWrQLen 11.47 # Average write queue length over time
+system.physmem.readRowHits 415807 # Number of row buffer hits during reads
+system.physmem.writeRowHits 89941 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes
+system.physmem.avgGap 3418758.64 # Average gap between requests
system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.342666 # Cycle average of tags in use
+system.iocache.tagsinuse 1.342284 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1745691885000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.342666 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.083917 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.083917 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.083893 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.083893 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
@@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 #
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 9475235806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 9475235806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 9496163804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 9496163804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 9496163804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 9496163804 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10644331806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10644331806 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10665259804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10665259804 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10665259804 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10665259804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228033.206729 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 228033.206729 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 227589.306267 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 227589.306267 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 189601 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 256168.940268 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 255608.383559 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 255608.383559 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 23064 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27152 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.220647 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.497496 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7312468500 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7312468500 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 7324399500 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7324399500 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 7324399500 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7324399500 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8482336109 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8482336109 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8494267359 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8494267359 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8494267359 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8494267359 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175983.550732 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 175983.550732 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9055970 # DTB read hits
+system.cpu.dtb.read_hits 9055197 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_accesses 728856 # DTB read accesses
-system.cpu.dtb.write_hits 6351685 # DTB write hits
+system.cpu.dtb.write_hits 6350929 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
-system.cpu.dtb.data_hits 15407655 # DTB hits
+system.cpu.dtb.data_hits 15406126 # DTB hits
system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020787 # DTB accesses
-system.cpu.itb.fetch_hits 4974178 # ITB hits
+system.cpu.itb.fetch_hits 4974131 # ITB hits
system.cpu.itb.fetch_misses 5006 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4979184 # ITB accesses
+system.cpu.itb.fetch_accesses 4979137 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -332,51 +332,51 @@ system.cpu.itb.data_hits 0 # DT
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3821164136 # number of cpu cycles simulated
+system.cpu.numCycles 3821095118 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 56125446 # Number of instructions committed
-system.cpu.committedOps 56125446 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 51999916 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses
-system.cpu.num_func_calls 1482010 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 6463546 # number of instructions that are conditional controls
-system.cpu.num_int_insts 51999916 # number of integer instructions
-system.cpu.num_fp_insts 324393 # number of float instructions
-system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read
-system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
-system.cpu.num_mem_refs 15460271 # number of memory refs
-system.cpu.num_load_insts 9092827 # Number of load instructions
-system.cpu.num_store_insts 6367444 # Number of store instructions
-system.cpu.num_idle_cycles 3587332264.998123 # Number of idle cycles
-system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles
-system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.938806 # Percentage of idle cycles
+system.cpu.committedInsts 56120911 # Number of instructions committed
+system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses
+system.cpu.num_func_calls 1481756 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls
+system.cpu.num_int_insts 51995405 # number of integer instructions
+system.cpu.num_fp_insts 324259 # number of float instructions
+system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read
+system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written
+system.cpu.num_mem_refs 15458726 # number of memory refs
+system.cpu.num_load_insts 9092044 # Number of load instructions
+system.cpu.num_store_insts 6366682 # Number of store instructions
+system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles
+system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles
+system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.938773 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211969 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149111 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 91164500 0.00% 97.14% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 736454000 0.04% 97.18% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 53835630000 2.82% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1910581334000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
@@ -412,10 +412,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
+system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175936 91.22% 93.42% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed
system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
@@ -424,21 +424,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu
system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192878 # number of callpals executed
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-system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
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-system.cpu.kern.mode_good::kernel 1911
-system.cpu.kern.mode_good::user 1741
-system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.323843 # fraction of useful protection mode switches
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system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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-system.cpu.kern.mode_switch_good::total 0.392483 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 45587423000 2.39% 2.39% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5075517000 0.27% 2.65% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4177 # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches
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+system.cpu.kern.mode_ticks::idle 1860019853500 97.36% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
@@ -470,51 +470,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 927460 # number of replacements
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-system.cpu.icache.total_refs 55209154 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 927971 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 59.494482 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 32120759000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 509.121498 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.994378 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.994378 # Average percentage of cache occupancy
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-system.cpu.icache.overall_hits::total 55209154 # number of overall hits
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-system.cpu.icache.ReadReq_miss_latency::cpu.inst 12666318500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 12666318500 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_avg_miss_latency::total 13647.123628 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13647.123628 # average overall miss latency
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+system.cpu.icache.warmup_cycle 32331359000 # Cycle when the warmup percentage was hit.
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -523,126 +523,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928131 # number of ReadReq MSHR misses
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 336061 # number of replacements
-system.cpu.l2cache.tagsinuse 65323.847661 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2445310 # Total number of references to valid blocks.
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -718,79 +718,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -799,54 +799,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195333000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28525483500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 28525483500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28525483500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 28525483500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 5fe42fc21..839e0acab 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -215,7 +215,7 @@ system.physmem.avgRdBW 0.00 # Av
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index bc1e2b029..9811be55f 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -198,7 +198,7 @@ system.physmem.avgRdBW 0.00 # Av
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index ebe1b98fa..13c85b6d1 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,122 +1,122 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.182882 # Number of seconds simulated
-sim_ticks 1182882156500 # Number of ticks simulated
-final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.183003 # Number of seconds simulated
+sim_ticks 1183003114000 # Number of ticks simulated
+final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 497131 # Simulator instruction rate (inst/s)
-host_op_rate 633435 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9569364300 # Simulator tick rate (ticks/s)
-host_mem_usage 452888 # Number of bytes of host memory used
-host_seconds 123.61 # Real time elapsed on the host
-sim_insts 61450993 # Number of instructions simulated
-sim_ops 78299715 # Number of ops (including micro ops) simulated
+host_inst_rate 673901 # Simulator instruction rate (inst/s)
+host_op_rate 858757 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 12970235901 # Simulator tick rate (ticks/s)
+host_mem_usage 408748 # Number of bytes of host memory used
+host_seconds 91.21 # Real time elapsed on the host
+sim_insts 61465824 # Number of instructions simulated
+sim_ops 78326377 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6654451 # Total number of read requests seen
-system.physmem.writeReqs 821128 # Total number of write requests seen
-system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 425884864 # Total number of bytes read from memory
-system.physmem.bytesWritten 52552192 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis
+system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6654023 # Total number of read requests seen
+system.physmem.writeReqs 820738 # Total number of write requests seen
+system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 425857472 # Total number of bytes read from memory
+system.physmem.bytesWritten 52527232 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1182877668000 # Total gap between requests
+system.physmem.totGap 1182998675500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6825 # Categorize read packet sizes
system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 159562 # Categorize read packet sizes
+system.physmem.readPktSize::6 159134 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -125,7 +125,7 @@ system.physmem.writePktSize::2 756836 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 64292 # categorize write packet sizes
+system.physmem.writePktSize::6 63902 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -134,26 +134,26 @@ system.physmem.neitherpktsize::2 0 # ca
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes
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@@ -170,60 +170,60 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
@@ -242,237 +242,237 @@ system.realview.nvmem.bw_inst_read::total 57 # I
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214915040 # number of WriteReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::total 176205976694 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044095 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019755 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.017528 # mshr miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.885452 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.827456 # mshr miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.855288 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770724 # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.546627 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.558553 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for overall accesses
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.735761 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.114496 # average UpgradeReq mshr miss latency
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+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.444685 # average SCUpgradeReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
@@ -656,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7070111 # DTB read hits
-system.cpu0.dtb.read_misses 3764 # DTB read misses
-system.cpu0.dtb.write_hits 5656042 # DTB write hits
-system.cpu0.dtb.write_misses 804 # DTB write misses
+system.cpu0.dtb.read_hits 5883553 # DTB read hits
+system.cpu0.dtb.read_misses 2148 # DTB read misses
+system.cpu0.dtb.write_hits 4842455 # DTB write hits
+system.cpu0.dtb.write_misses 405 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7073875 # DTB read accesses
-system.cpu0.dtb.write_accesses 5656846 # DTB write accesses
+system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions
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+system.cpu0.dtb.write_accesses 4842860 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 12726153 # DTB hits
-system.cpu0.dtb.misses 4568 # DTB misses
-system.cpu0.dtb.accesses 12730721 # DTB accesses
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-system.cpu0.itb.inst_misses 2205 # ITB inst misses
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
@@ -685,86 +685,86 @@ system.cpu0.itb.flush_tlb 4 # Nu
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses
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-system.cpu0.itb.misses 2205 # DTB misses
-system.cpu0.itb.accesses 29572515 # DTB accesses
-system.cpu0.numCycles 2365764313 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed
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-system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
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-system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
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+system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed
-system.cpu0.icache.replacements 425445 # number of replacements
-system.cpu0.icache.tagsinuse 509.616014 # Cycle average of tags in use
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-system.cpu0.icache.sampled_refs 425957 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 68.420838 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.995344 # Average percentage of cache occupancy
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+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2678719000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 2678719000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3810145000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 3810145000 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 78655500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 78655500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45606000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 45606000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 6488864000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 6488864000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 6488864000 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 6488864000 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 5669311 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 5669311 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 4698314 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 4698314 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138005 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 138005 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137928 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 137928 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 10367625 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 10367625 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 10367625 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 10367625 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033824 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.033824 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062643 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062643 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.055848 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.055848 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030699 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.030699 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030699 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.030699 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13969.414256 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13969.414256 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30114.486018 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 30114.486018 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -895,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 306206 # number of writebacks
-system.cpu0.dcache.writebacks::total 306206 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227863 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 227863 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141515 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 141515 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9301 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9301 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 369378 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 369378 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 369378 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 369378 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2674386000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2674386000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3820765500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3820765500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69382000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69382000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29532500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29532500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks
+system.cpu0.dcache.writebacks::total 257540 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6495151500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 6495151500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6495151500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 6495151500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@@ -964,27 +964,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 8310545 # DTB read hits
-system.cpu1.dtb.read_misses 3643 # DTB read misses
-system.cpu1.dtb.write_hits 5827351 # DTB write hits
-system.cpu1.dtb.write_misses 1434 # DTB write misses
+system.cpu1.dtb.read_hits 9504194 # DTB read hits
+system.cpu1.dtb.read_misses 5263 # DTB read misses
+system.cpu1.dtb.write_hits 6646220 # DTB write hits
+system.cpu1.dtb.write_misses 1833 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 8314188 # DTB read accesses
-system.cpu1.dtb.write_accesses 5828785 # DTB write accesses
+system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 9509457 # DTB read accesses
+system.cpu1.dtb.write_accesses 6648053 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 14137896 # DTB hits
-system.cpu1.dtb.misses 5077 # DTB misses
-system.cpu1.dtb.accesses 14142973 # DTB accesses
-system.cpu1.itb.inst_hits 33189113 # ITB inst hits
-system.cpu1.itb.inst_misses 2171 # ITB inst misses
+system.cpu1.dtb.hits 16150414 # DTB hits
+system.cpu1.dtb.misses 7096 # DTB misses
+system.cpu1.dtb.accesses 16157510 # DTB accesses
+system.cpu1.itb.inst_hits 37994467 # ITB inst hits
+system.cpu1.itb.inst_misses 3017 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
@@ -993,86 +993,86 @@ system.cpu1.itb.flush_tlb 4 # Nu
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses
-system.cpu1.itb.hits 33189113 # DTB hits
-system.cpu1.itb.misses 2171 # DTB misses
-system.cpu1.itb.accesses 33191284 # DTB accesses
-system.cpu1.numCycles 2364318212 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses
+system.cpu1.itb.hits 37994467 # DTB hits
+system.cpu1.itb.misses 3017 # DTB misses
+system.cpu1.itb.accesses 37997484 # DTB accesses
+system.cpu1.numCycles 2366006228 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 32578626 # Number of instructions committed
-system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
-system.cpu1.num_func_calls 962009 # number of times a function call or return occured
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@@ -1081,120 +1081,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119242 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108157 # miss rate for StoreCondReq accesses
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-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12604.357388 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12604.357388 # average ReadReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8334.432598 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8334.432598 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5152.327784 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5152.327784 # average StoreCondReq miss latency
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-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency
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+system.cpu1.dcache.sampled_refs 344469 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 83709904000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 473.088021 # Average occupied blocks per requestor
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+system.cpu1.dcache.occ_percent::total 0.924000 # Average percentage of cache occupancy
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+system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12738.492987 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12738.492987 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 29258.525014 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8746.395250 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8746.395250 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5135.753508 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5135.753508 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20068.570485 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20068.570485 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1203,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks
-system.cpu1.dcache.writebacks::total 265102 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10026 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10026 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 320439 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 320439 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 320439 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 320439 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1808202000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1808202000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4227233500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4227233500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70109500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70109500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31633000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31633000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks
+system.cpu1.dcache.writebacks::total 315665 # number of writebacks
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+system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses
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+system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses
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+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles
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+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
@@ -1284,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index b72126c20..73585121b 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,105 +1,105 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.603635 # Number of seconds simulated
-sim_ticks 2603634694000 # Number of ticks simulated
-final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.603665 # Number of seconds simulated
+sim_ticks 2603664815000 # Number of ticks simulated
+final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 413538 # Simulator instruction rate (inst/s)
-host_op_rate 526220 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17886148072 # Simulator tick rate (ticks/s)
-host_mem_usage 448796 # Number of bytes of host memory used
-host_seconds 145.57 # Real time elapsed on the host
-sim_insts 60197457 # Number of instructions simulated
-sim_ops 76600355 # Number of ops (including micro ops) simulated
+host_inst_rate 536000 # Simulator instruction rate (inst/s)
+host_op_rate 682052 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 23183028791 # Simulator tick rate (ticks/s)
+host_mem_usage 404656 # Number of bytes of host memory used
+host_seconds 112.31 # Real time elapsed on the host
+sim_insts 60197643 # Number of instructions simulated
+sim_ops 76600583 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15494095 # Total number of read requests seen
-system.physmem.writeReqs 811481 # Total number of write requests seen
-system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 991622080 # Total number of bytes read from memory
-system.physmem.bytesWritten 51934784 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15494089 # Total number of read requests seen
+system.physmem.writeReqs 811479 # Total number of write requests seen
+system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 991621696 # Total number of bytes read from memory
+system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2603630334000 # Total gap between requests
+system.physmem.totGap 2603660455000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6652 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 152019 # Categorize read packet sizes
+system.physmem.readPktSize::6 152013 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -108,7 +108,7 @@ system.physmem.writePktSize::2 754018 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 57463 # categorize write packet sizes
+system.physmem.writePktSize::6 57461 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -120,23 +120,23 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
@@ -153,14 +153,14 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see
@@ -169,44 +169,44 @@ system.physmem.wrQLenPdf::12 35282 # Wh
system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests
-system.physmem.totBusLat 61975036000 # Total cycles spent in databus access
-system.physmem.totBankLat 16863224000 # Total cycles spent in bank access
-system.physmem.avgQLat 18619.82 # Average queueing delay per request
-system.physmem.avgBankLat 1088.39 # Average bank access latency per request
-system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 23708.21 # Average memory access latency
+system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests
+system.physmem.totBusLat 77468765000 # Total cycles spent in databus access
+system.physmem.totBankLat 17445216250 # Total cycles spent in bank access
+system.physmem.avgQLat 22041.64 # Average queueing delay per request
+system.physmem.avgBankLat 1125.95 # Average bank access latency per request
+system.physmem.avgBusLat 5000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 28167.59 # Average memory access latency
system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.51 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.14 # Average read queue length over time
-system.physmem.avgWrQLen 12.40 # Average write queue length over time
-system.physmem.readRowHits 15451886 # Number of row buffer hits during reads
-system.physmem.writeRowHits 785061 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes
-system.physmem.avgGap 159677.30 # Average gap between requests
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 3.13 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.17 # Average read queue length over time
+system.physmem.avgWrQLen 12.39 # Average write queue length over time
+system.physmem.readRowHits 15418905 # Number of row buffer hits during reads
+system.physmem.writeRowHits 794060 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes
+system.physmem.avgGap 159679.22 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
@@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14995645 # DTB read hits
-system.cpu.dtb.read_misses 7331 # DTB read misses
-system.cpu.dtb.write_hits 11230857 # DTB write hits
+system.cpu.dtb.read_hits 14995667 # DTB read hits
+system.cpu.dtb.read_misses 7332 # DTB read misses
+system.cpu.dtb.write_hits 11230865 # DTB write hits
system.cpu.dtb.write_misses 2203 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
@@ -240,13 +240,13 @@ system.cpu.dtb.align_faults 0 # Nu
system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 15002976 # DTB read accesses
-system.cpu.dtb.write_accesses 11233060 # DTB write accesses
+system.cpu.dtb.read_accesses 15002999 # DTB read accesses
+system.cpu.dtb.write_accesses 11233068 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26226502 # DTB hits
-system.cpu.dtb.misses 9534 # DTB misses
-system.cpu.dtb.accesses 26236036 # DTB accesses
-system.cpu.itb.inst_hits 61491397 # ITB inst hits
+system.cpu.dtb.hits 26226532 # DTB hits
+system.cpu.dtb.misses 9535 # DTB misses
+system.cpu.dtb.accesses 26236067 # DTB accesses
+system.cpu.itb.inst_hits 61491584 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
@@ -263,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 61495868 # ITB inst accesses
-system.cpu.itb.hits 61491397 # DTB hits
+system.cpu.itb.inst_accesses 61496055 # ITB inst accesses
+system.cpu.itb.hits 61491584 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 61495868 # DTB accesses
-system.cpu.numCycles 5207269388 # number of cpu cycles simulated
+system.cpu.itb.accesses 61496055 # DTB accesses
+system.cpu.numCycles 5207329630 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60197457 # Number of instructions committed
-system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses
+system.cpu.committedInsts 60197643 # Number of instructions committed
+system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 2139722 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68868122 # number of integer instructions
+system.cpu.num_func_calls 2139730 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls
+system.cpu.num_int_insts 68868344 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read
-system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written
+system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read
+system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27393871 # number of memory refs
-system.cpu.num_load_insts 15659652 # Number of load instructions
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-system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles
-system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles
-system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.879373 # Percentage of idle cycles
+system.cpu.num_mem_refs 27393912 # number of memory refs
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+system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.879355 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed
-system.cpu.icache.replacements 855485 # number of replacements
-system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use
-system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy
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-system.cpu.icache.overall_hits::total 60635400 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 855997 # number of ReadReq misses
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-system.cpu.icache.overall_misses::total 855997 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles
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+system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13480.986499 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13480.986499 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13480.986499 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13480.986499 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13515.573635 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13515.573635 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13515.573635 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13515.573635 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -344,174 +344,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855997 # number of ReadReq MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9827690000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.l2cache.tagsinuse 50893.937876 # Cycle average of tags in use
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-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027188 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.027188 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.026034 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.026034 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.026034 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.026034 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.130145 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.130145 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32117.582132 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -696,54 +696,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 596029 # number of writebacks
-system.cpu.dcache.writebacks::total 596029 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368781 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 368781 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 619291 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 619291 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 619291 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 619291 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4464142000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4464142000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7544755500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7544755500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131983000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131983000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12008897500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12008897500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12008897500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12008897500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182078406500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182078406500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18714752000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18714752000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200793158500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 200793158500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks
+system.cpu.dcache.writebacks::total 596039 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.026034 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.026034 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.130145 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.130145 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30117.582132 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30117.582132 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11575.425364 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11575.425364 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index 21a80bd51..9d3d17a68 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -211,7 +211,7 @@ system.physmem.avgRdBW 0.00 # Av
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 175418c2b..4cde41f9a 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,13 +4,13 @@ sim_seconds 5.112041 # Nu
sim_ticks 5112040970500 # Number of ticks simulated
final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1071475 # Simulator instruction rate (inst/s)
-host_op_rate 2193921 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27413112180 # Simulator tick rate (ticks/s)
-host_mem_usage 626876 # Number of bytes of host memory used
-host_seconds 186.48 # Real time elapsed on the host
+host_inst_rate 1816388 # Simulator instruction rate (inst/s)
+host_op_rate 3719186 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 46471341970 # Simulator tick rate (ticks/s)
+host_mem_usage 582576 # Number of bytes of host memory used
+host_seconds 110.00 # Real time elapsed on the host
sim_insts 199810242 # Number of instructions simulated
-sim_ops 409125923 # Number of ops (including micro ops) simulated
+sim_ops 409125913 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
@@ -195,7 +195,7 @@ system.physmem.avgRdBW 0.00 # Av
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
@@ -264,22 +264,22 @@ system.cpu.numCycles 10224081964 # nu
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 199810242 # Number of instructions committed
-system.cpu.committedOps 409125923 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 374289914 # Number of integer alu accesses
+system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls
-system.cpu.num_int_insts 374289914 # number of integer instructions
+system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls
+system.cpu.num_int_insts 374289904 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 915450706 # number of times the integer registers were read
-system.cpu.num_int_register_writes 480322745 # number of times the integer registers were written
+system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read
+system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 35624590 # number of memory refs
system.cpu.num_load_insts 27216588 # Number of load instructions
system.cpu.num_store_insts 8408002 # Number of store instructions
-system.cpu.num_idle_cycles 9770609597.971960 # Number of idle cycles
-system.cpu.num_busy_cycles 453472366.028039 # Number of busy cycles
+system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles
+system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles
system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
@@ -331,7 +331,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cy
system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5102019610500 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy
@@ -379,7 +379,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cy
system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5101206386000 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy
@@ -471,7 +471,7 @@ system.cpu.dcache.writebacks::writebacks 1534848 # nu
system.cpu.dcache.writebacks::total 1534848 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 106558 # number of replacements
-system.cpu.l2cache.tagsinuse 64822.149219 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks.
@@ -479,8 +479,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 2434.994082 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 10405.564951 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 5387a3a4f..da7af1088 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,98 +1,102 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.191113 # Number of seconds simulated
-sim_ticks 5191112864000 # Number of ticks simulated
-final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.195162 # Number of seconds simulated
+sim_ticks 5195162021000 # Number of ticks simulated
+final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 663100 # Simulator instruction rate (inst/s)
-host_op_rate 1278245 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26841102406 # Simulator tick rate (ticks/s)
-host_mem_usage 658020 # Number of bytes of host memory used
-host_seconds 193.40 # Real time elapsed on the host
-sim_insts 128244620 # Number of instructions simulated
-sim_ops 247214608 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory
+host_inst_rate 973985 # Simulator instruction rate (inst/s)
+host_op_rate 1877578 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39447094407 # Simulator tick rate (ticks/s)
+host_mem_usage 612564 # Number of bytes of host memory used
+host_seconds 131.70 # Real time elapsed on the host
+sim_insts 128273348 # Number of instructions simulated
+sim_ops 247275973 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9026368 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12705024 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 825984 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 825984 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8129280 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8129280 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 44568 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9012160 # Number of bytes read from this memory
+system.physmem.bytes_read::total 12697600 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8123136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8123136 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 44708 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12906 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141037 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 198516 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 127020 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 127020 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 549468 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 140815 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 198400 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 126924 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 126924 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 550765 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 159115 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1738812 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2447457 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 159115 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 159115 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1565999 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1565999 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1565999 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 549468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 158560 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1734722 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2444120 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 158560 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 158560 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1563596 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1563596 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1563596 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 550765 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 159115 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1738812 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4013456 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 198516 # Total number of read requests seen
-system.physmem.writeReqs 127020 # Total number of write requests seen
-system.physmem.cpureqs 331314 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 12705024 # Total number of bytes read from memory
-system.physmem.bytesWritten 8129280 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 12705024 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 8129280 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 1599 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 12028 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 12411 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 11776 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 12503 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 12483 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 12755 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 12240 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 12788 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 12663 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 12687 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 12141 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 12548 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 12236 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 12474 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 11907 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 12788 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7431 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7966 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7373 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 8083 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7981 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 8219 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7719 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 8332 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 8225 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 8161 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7712 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 8125 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7893 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7991 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7528 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 8281 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 158560 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1734722 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 198400 # Total number of read requests seen
+system.physmem.writeReqs 126924 # Total number of write requests seen
+system.physmem.cpureqs 331611 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 12697600 # Total number of bytes read from memory
+system.physmem.bytesWritten 8123136 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 12233 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 12566 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 12719 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 12479 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 12349 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 12465 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 12500 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 12468 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 12050 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 12371 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 12574 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 8012 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7683 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7790 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 8089 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7865 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7679 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 8084 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 8243 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 8069 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7980 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7953 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7969 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7935 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7628 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5191112800500 # Total gap between requests
+system.physmem.numWrRetry 633 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5195161957500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 198516 # Categorize read packet sizes
+system.physmem.readPktSize::6 198400 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -101,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 127020 # categorize write packet sizes
+system.physmem.writePktSize::6 127557 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -110,30 +114,30 @@ system.physmem.neitherpktsize::2 0 # ca
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 1599 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 1624 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 158090 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 11440 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 7599 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2597 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3245 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2511 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1497 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1744 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1556 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1514 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1392 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1291 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1281 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1081 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 355 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 264 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 118 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 155111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 8768 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 6671 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3399 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2809 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2248 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2166 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2070 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2020 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1315 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1213 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1043 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 972 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1102 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1082 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
@@ -146,93 +150,93 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4625 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 5391 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 5480 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 5504 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 5511 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5517 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5523 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 5523 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 5523 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 5523 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 5523 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 5523 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 898 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4190 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5474 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5502 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5510 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5511 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2876225269 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 6438451269 # Sum of mem lat for all requests
-system.physmem.totBusLat 793712000 # Total cycles spent in databus access
-system.physmem.totBankLat 2768514000 # Total cycles spent in bank access
-system.physmem.avgQLat 14495.06 # Average queueing delay per request
-system.physmem.avgBankLat 13952.23 # Average bank access latency per request
-system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32447.29 # Average memory access latency
-system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.totQLat 4076582985 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7872522985 # Sum of mem lat for all requests
+system.physmem.totBusLat 991710000 # Total cycles spent in databus access
+system.physmem.totBankLat 2804230000 # Total cycles spent in bank access
+system.physmem.avgQLat 20553.30 # Average queueing delay per request
+system.physmem.avgBankLat 14138.36 # Average bank access latency per request
+system.physmem.avgBusLat 5000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 39691.66 # Average memory access latency
+system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 9.06 # Average write queue length over time
-system.physmem.readRowHits 179831 # Number of row buffer hits during reads
-system.physmem.writeRowHits 78085 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.63 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 61.47 # Row buffer hit rate for writes
-system.physmem.avgGap 15946355.55 # Average gap between requests
-system.iocache.replacements 47506 # number of replacements
-system.iocache.tagsinuse 0.117830 # Cycle average of tags in use
+system.physmem.avgWrQLen 12.66 # Average write queue length over time
+system.physmem.readRowHits 175587 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94819 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes
+system.physmem.avgGap 15969193.66 # Average gap between requests
+system.iocache.replacements 47509 # number of replacements
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system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47522 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47525 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 5044498925000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.117830 # Average occupied blocks per requestor
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-system.iocache.occ_percent::total 0.007364 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 841 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 841 # number of ReadReq misses
+system.iocache.warmup_cycle 5044527520000 # Cycle when the warmup percentage was hit.
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system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
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-system.iocache.demand_misses::total 47561 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47561 # number of overall misses
-system.iocache.overall_misses::total 47561 # number of overall misses
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-system.iocache.ReadReq_miss_latency::total 133668932 # number of ReadReq miss cycles
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-system.iocache.WriteReq_miss_latency::total 9598301160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 9731970092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 9731970092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 9731970092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 9731970092 # number of overall miss cycles
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-system.iocache.ReadReq_accesses::total 841 # number of ReadReq accesses(hits+misses)
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+system.iocache.demand_miss_latency::total 10841219092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10841219092 # number of overall miss cycles
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+system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47561 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47561 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47561 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47561 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses
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+system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
@@ -241,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158940.466112 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 158940.466112 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 205443.089897 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 205443.089897 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 204620.804693 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 204620.804693 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 78425 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229061.197774 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 229061.197774 # average WriteReq miss latency
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+system.iocache.demand_avg_miss_latency::total 227929.086957 # average overall miss latency
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+system.iocache.overall_avg_miss_latency::total 227929.086957 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 173428 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 10368 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 16211 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 7.564140 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.698168 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 841 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 841 # number of ReadReq MSHR misses
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system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
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-system.iocache.overall_mshr_misses::total 47561 # number of overall MSHR misses
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-system.iocache.ReadReq_mshr_miss_latency::total 89906992 # number of ReadReq MSHR miss cycles
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-system.iocache.WriteReq_mshr_miss_latency::total 7166703132 # number of WriteReq MSHR miss cycles
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-system.iocache.demand_mshr_miss_latency::total 7256610124 # number of demand (read+write) MSHR miss cycles
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-system.iocache.overall_mshr_miss_latency::total 7256610124 # number of overall MSHR miss cycles
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+system.iocache.ReadReq_mshr_miss_latency::total 95570991 # number of ReadReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::total 8366509215 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8366509215 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
@@ -283,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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-system.iocache.ReadReq_avg_mshr_miss_latency::total 106904.865636 # average ReadReq mshr miss latency
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-system.iocache.WriteReq_avg_mshr_miss_latency::total 153396.899229 # average WriteReq mshr miss latency
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-system.iocache.demand_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.771327 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.771327 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177032.068151 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 177032.068151 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@@ -304,75 +308,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 10382225728 # number of cpu cycles simulated
+system.cpu.numCycles 10390324042 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 128244620 # Number of instructions committed
-system.cpu.committedOps 247214608 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 231949869 # Number of integer alu accesses
+system.cpu.committedInsts 128273348 # Number of instructions committed
+system.cpu.committedOps 247275973 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 232011682 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls
-system.cpu.num_int_insts 231949869 # number of integer instructions
+system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls
+system.cpu.num_int_insts 232011682 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 566905534 # number of times the integer registers were read
-system.cpu.num_int_register_writes 293156476 # number of times the integer registers were written
+system.cpu.num_int_register_reads 567056120 # number of times the integer registers were read
+system.cpu.num_int_register_writes 293242224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 22227095 # number of memory refs
-system.cpu.num_load_insts 13866667 # Number of load instructions
-system.cpu.num_store_insts 8360428 # Number of store instructions
-system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles
-system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles
-system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.942147 # Percentage of idle cycles
+system.cpu.num_mem_refs 22232138 # number of memory refs
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+system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.942191 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.icache.replacements 790930 # number of replacements
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-system.cpu.icache.avg_refs 182.521707 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor
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+system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 144455345 # number of ReadReq hits
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system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -543,90 +547,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -635,46 +639,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@@ -682,127 +686,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.167198 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 141743 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 154621 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56252 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281260 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 630045573 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1296264296 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1926647381 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14542846 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14542846 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190240726 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190240726 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281260 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 630045573 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5486505022 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6116888107 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56252 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281260 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 630045573 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5486505022 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6116888107 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305021500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896197000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896197000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.063901 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56252 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48946.983608 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45667.229029 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46691.888156 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36964.667037 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36964.667037 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 015bc1924..c8eb78d93 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -1,45 +1,45 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.200409 # Number of seconds simulated
-sim_ticks 200409284500 # Number of ticks simulated
-final_tick 4321205328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 200409293000 # Number of ticks simulated
+final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 13697441 # Simulator instruction rate (inst/s)
-host_op_rate 13697433 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5245128514 # Simulator tick rate (ticks/s)
-host_mem_usage 514692 # Number of bytes of host memory used
-host_seconds 38.21 # Real time elapsed on the host
-sim_insts 523360203 # Number of instructions simulated
-sim_ops 523360203 # Number of ops (including micro ops) simulated
-testsys.physmem.bytes_read::cpu.inst 80888044 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 27771396 # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet 50103096 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 158762536 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 80888044 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 80888044 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 16575224 # Number of bytes written to this memory
+host_inst_rate 19440889 # Simulator instruction rate (inst/s)
+host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7408936081 # Simulator tick rate (ticks/s)
+host_mem_usage 472492 # Number of bytes of host memory used
+host_seconds 27.05 # Real time elapsed on the host
+sim_insts 525869186 # Number of instructions simulated
+sim_ops 525869186 # Number of ops (including micro ops) simulated
+testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 27826180 # Number of bytes read from this memory
+testsys.physmem.bytes_read::tsunami.ethernet 51169128 # Number of bytes read from this memory
+testsys.physmem.bytes_read::total 160043872 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 81048564 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 81048564 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 16606324 # Number of bytes written to this memory
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 16576126 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 20222011 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 3834989 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet 2087611 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 26144611 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 2254078 # Number of write requests responded to by this memory
+testsys.physmem.bytes_written::total 16607226 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 20262141 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 3842564 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::tsunami.ethernet 2132029 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::total 26236734 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 2258349 # Number of write requests responded to by this memory
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 2254109 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 403614255 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 138573400 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet 250003866 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 792191521 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 403614255 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 403614255 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 82706867 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.num_writes::total 2258380 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 404415198 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 138846755 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet 255323130 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 798585084 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 404415198 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 404415198 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 82862046 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 82711368 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 403614255 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 221280267 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet 250008367 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 874902889 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_write::total 82866547 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 404415198 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 221708801 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet 255327631 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 881451630 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.readReqs 0 # Total number of read requests seen
testsys.physmem.writeReqs 0 # Total number of write requests seen
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
@@ -189,7 +189,7 @@ testsys.physmem.avgRdBW 0.00 # Av
testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
@@ -214,22 +214,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 3909164 # DTB read hits
+testsys.cpu.dtb.read_hits 3916928 # DTB read hits
testsys.cpu.dtb.read_misses 3287 # DTB read misses
testsys.cpu.dtb.read_acv 80 # DTB read access violations
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
-testsys.cpu.dtb.write_hits 2312434 # DTB write hits
+testsys.cpu.dtb.write_hits 2316846 # DTB write hits
testsys.cpu.dtb.write_misses 528 # DTB write misses
testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
-testsys.cpu.dtb.data_hits 6221598 # DTB hits
+testsys.cpu.dtb.data_hits 6233774 # DTB hits
testsys.cpu.dtb.data_misses 3815 # DTB misses
testsys.cpu.dtb.data_acv 161 # DTB access violations
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
-testsys.cpu.itb.fetch_hits 4045775 # ITB hits
+testsys.cpu.itb.fetch_hits 4052272 # ITB hits
testsys.cpu.itb.fetch_misses 1497 # ITB misses
testsys.cpu.itb.fetch_acv 69 # ITB acv
-testsys.cpu.itb.fetch_accesses 4047272 # ITB accesses
+testsys.cpu.itb.fetch_accesses 4053769 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations
@@ -242,51 +242,51 @@ testsys.cpu.itb.data_hits 0 # DT
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 400807419 # number of cpu cycles simulated
+testsys.cpu.numCycles 400815936 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 20218035 # Number of instructions committed
-testsys.cpu.committedOps 20218035 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 18800192 # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
-testsys.cpu.num_func_calls 1218514 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 1439639 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 18800192 # number of integer instructions
-testsys.cpu.num_fp_insts 17380 # number of float instructions
-testsys.cpu.num_int_register_reads 24739164 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 14664877 # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 6250795 # number of memory refs
-testsys.cpu.num_load_insts 3936233 # Number of load instructions
-testsys.cpu.num_store_insts 2314562 # Number of store instructions
-testsys.cpu.num_idle_cycles 380584404.581032 # Number of idle cycles
-testsys.cpu.num_busy_cycles 20223014.418968 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.050456 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.949544 # Percentage of idle cycles
+testsys.cpu.committedInsts 20258165 # Number of instructions committed
+testsys.cpu.committedOps 20258165 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 18837392 # Number of integer alu accesses
+testsys.cpu.num_fp_alu_accesses 17313 # Number of float alu accesses
+testsys.cpu.num_func_calls 1221260 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 1442190 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 18837392 # number of integer instructions
+testsys.cpu.num_fp_insts 17313 # number of float instructions
+testsys.cpu.num_int_register_reads 24787608 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 14694255 # number of times the integer registers were written
+testsys.cpu.num_fp_register_reads 11133 # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes 10789 # number of times the floating registers were written
+testsys.cpu.num_mem_refs 6263009 # number of memory refs
+testsys.cpu.num_load_insts 3944038 # Number of load instructions
+testsys.cpu.num_store_insts 2318971 # Number of store instructions
+testsys.cpu.num_idle_cycles 380552362.972989 # Number of idle cycles
+testsys.cpu.num_busy_cycles 20263573.027011 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.050556 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.949444 # Percentage of idle cycles
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce 19525 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 153371 # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0 62656 42.67% 42.67% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21 19578 13.33% 56.01% # number of times we switched to this ipl
+testsys.cpu.kern.inst.quiesce 19598 # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei 153677 # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0 62790 42.68% 42.68% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21 19620 13.34% 56.01% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 64383 43.85% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 146822 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0 62650 43.18% 43.18% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21 19578 13.49% 56.67% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_count::31 64514 43.85% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 147129 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0 62784 43.18% 43.18% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21 19620 13.49% 56.67% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31 62661 43.19% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total 145094 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 194361437500 96.98% 96.98% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21 1585244500 0.79% 97.78% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_good::31 62791 43.19% 100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total 145400 # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0 194352160500 96.98% 96.98% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21 1588908500 0.79% 97.77% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 4448431000 2.22% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 200403928000 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 4458302500 2.22% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 200408186500 # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.973254 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.988231 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::31 0.973293 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.988248 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
@@ -309,30 +309,30 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
-testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed
+testsys.cpu.kern.callpal::swpctx 437 0.34% 0.34% # number of callpals executed
testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
-testsys.cpu.kern.callpal::swpipl 106626 83.26% 83.62% # number of callpals executed
+testsys.cpu.kern.callpal::swpipl 106841 83.26% 83.62% # number of callpals executed
testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
-testsys.cpu.kern.callpal::rdusp 3 0.00% 83.91% # number of callpals executed
-testsys.cpu.kern.callpal::rti 20424 15.95% 99.86% # number of callpals executed
+testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed
+testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed
testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 128057 # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel 1279 # number of protection mode switches
-testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle 19584 # number of protection mode switches
+testsys.cpu.kern.callpal::total 128317 # number of callpals executed
+testsys.cpu.kern.mode_switch::kernel 1281 # number of protection mode switches
+testsys.cpu.kern.mode_switch::user 703 # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle 19627 # number of protection mode switches
testsys.cpu.kern.mode_good::kernel 707
-testsys.cpu.kern.mode_good::user 702
-testsys.cpu.kern.mode_good::idle 5
-testsys.cpu.kern.mode_switch_good::kernel 0.552776 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_good::user 703
+testsys.cpu.kern.mode_good::idle 4
+testsys.cpu.kern.mode_switch_good::kernel 0.551913 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total 0.065569 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel 993857000 59.77% 59.77% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user 533068000 32.06% 91.82% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle 135946500 8.18% 100.00% # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
+testsys.cpu.kern.mode_switch_good::idle 0.000204 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks::kernel 1002766500 60.53% 60.53% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user 533073000 32.18% 92.70% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle 120928500 7.30% 100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.swap_context 437 # number of times the context was actually changed
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
@@ -343,9 +343,9 @@ testsys.tsunami.ethernet.txTcpChecksums 2 # Nu
testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-testsys.tsunami.ethernet.descDMAReads 2087576 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAReads 2131994 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 50101824 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 51167856 # number of descriptor bytes read w/ DMA
testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
testsys.tsunami.ethernet.totPackets 13 # Total Packets
@@ -370,9 +370,9 @@ testsys.tsunami.ethernet.totalRxDesc 5 # to
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle 19525 # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle 2087576 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.totalTxIdle 2131994 # total number of TxIdle written to ISR
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
@@ -380,37 +380,37 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts 2087594 # number of posts to CPU
+testsys.tsunami.ethernet.postedInterrupts 2132012 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.physmem.bytes_read::cpu.inst 76121948 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::cpu.data 26255588 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet 50103126 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total 152480662 # Number of bytes read from this memory
-drivesys.physmem.bytes_inst_read::cpu.inst 76121948 # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_inst_read::total 76121948 # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_written::cpu.data 14603776 # Number of bytes written to this memory
+drivesys.physmem.bytes_read::cpu.inst 76288612 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::cpu.data 26312880 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::tsunami.ethernet 51169134 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::total 153770626 # Number of bytes read from this memory
+drivesys.physmem.bytes_inst_read::cpu.inst 76288612 # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_inst_read::total 76288612 # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_written::cpu.data 14635456 # Number of bytes written to this memory
drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory
-drivesys.physmem.bytes_written::total 14604840 # Number of bytes written to this memory
-drivesys.physmem.num_reads::cpu.inst 19030487 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::cpu.data 3643074 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet 2087613 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total 24761174 # Number of read requests responded to by this memory
-drivesys.physmem.num_writes::cpu.data 2022588 # Number of write requests responded to by this memory
+drivesys.physmem.bytes_written::total 14636520 # Number of bytes written to this memory
+drivesys.physmem.num_reads::cpu.inst 19072153 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::cpu.data 3651006 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::tsunami.ethernet 2132030 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::total 24855189 # Number of read requests responded to by this memory
+drivesys.physmem.num_writes::cpu.data 2026958 # Number of write requests responded to by this memory
drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::total 2022625 # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst 379832442 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data 131009839 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet 250004016 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total 760846297 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst 379832442 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total 379832442 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data 72869758 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.num_writes::total 2026995 # Number of write requests responded to by this memory
+drivesys.physmem.bw_read::cpu.inst 380664044 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.data 131295708 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::tsunami.ethernet 255323160 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::total 767282912 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::cpu.inst 380664044 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::total 380664044 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::cpu.data 73027831 # Write bandwidth from this memory (bytes/s)
drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total 72875067 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst 379832442 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data 203879596 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet 250009325 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total 833721364 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_write::total 73033140 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.inst 380664044 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.data 204323539 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::tsunami.ethernet 255328469 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::total 840316053 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.readReqs 0 # Total number of read requests seen
drivesys.physmem.writeReqs 0 # Total number of write requests seen
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
@@ -560,7 +560,7 @@ drivesys.physmem.avgRdBW 0.00 # Av
drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
@@ -585,22 +585,22 @@ drivesys.cpu.dtb.fetch_hits 0 # IT
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
-drivesys.cpu.dtb.read_hits 3721202 # DTB read hits
+drivesys.cpu.dtb.read_hits 3729326 # DTB read hits
drivesys.cpu.dtb.read_misses 487 # DTB read misses
drivesys.cpu.dtb.read_acv 30 # DTB read access violations
drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses
-drivesys.cpu.dtb.write_hits 2081819 # DTB write hits
+drivesys.cpu.dtb.write_hits 2086333 # DTB write hits
drivesys.cpu.dtb.write_misses 82 # DTB write misses
drivesys.cpu.dtb.write_acv 10 # DTB write access violations
drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses
-drivesys.cpu.dtb.data_hits 5803021 # DTB hits
+drivesys.cpu.dtb.data_hits 5815659 # DTB hits
drivesys.cpu.dtb.data_misses 569 # DTB misses
drivesys.cpu.dtb.data_acv 40 # DTB access violations
drivesys.cpu.dtb.data_accesses 401230 # DTB accesses
-drivesys.cpu.itb.fetch_hits 4194101 # ITB hits
+drivesys.cpu.itb.fetch_hits 4201097 # ITB hits
drivesys.cpu.itb.fetch_misses 194 # ITB misses
drivesys.cpu.itb.fetch_acv 22 # ITB acv
-drivesys.cpu.itb.fetch_accesses 4194295 # ITB accesses
+drivesys.cpu.itb.fetch_accesses 4201291 # ITB accesses
drivesys.cpu.itb.read_hits 0 # DTB read hits
drivesys.cpu.itb.read_misses 0 # DTB read misses
drivesys.cpu.itb.read_acv 0 # DTB read access violations
@@ -613,51 +613,51 @@ drivesys.cpu.itb.data_hits 0 # DT
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
-drivesys.cpu.numCycles 801639056 # number of cpu cycles simulated
+drivesys.cpu.numCycles 801619128 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-drivesys.cpu.committedInsts 19029878 # Number of instructions committed
-drivesys.cpu.committedOps 19029878 # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses 17721251 # Number of integer alu accesses
+drivesys.cpu.committedInsts 19071544 # Number of instructions committed
+drivesys.cpu.committedOps 19071544 # Number of ops (including micro ops) committed
+drivesys.cpu.num_int_alu_accesses 17759891 # Number of integer alu accesses
drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses
-drivesys.cpu.num_func_calls 1263632 # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts 1263629 # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts 17721251 # number of integer instructions
+drivesys.cpu.num_func_calls 1266408 # number of times a function call or return occured
+drivesys.cpu.num_conditional_control_insts 1266328 # number of instructions that are conditional controls
+drivesys.cpu.num_int_insts 17759891 # number of integer instructions
drivesys.cpu.num_fp_insts 1412 # number of float instructions
-drivesys.cpu.num_int_register_reads 23047059 # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes 13965767 # number of times the integer registers were written
+drivesys.cpu.num_int_register_reads 23097438 # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes 13996340 # number of times the integer registers were written
drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read
drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written
-drivesys.cpu.num_mem_refs 5824433 # number of memory refs
-drivesys.cpu.num_load_insts 3742101 # Number of load instructions
-drivesys.cpu.num_store_insts 2082332 # Number of store instructions
-drivesys.cpu.num_idle_cycles 782608307.467164 # Number of idle cycles
-drivesys.cpu.num_busy_cycles 19030748.532836 # Number of busy cycles
-drivesys.cpu.not_idle_fraction 0.023740 # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction 0.976260 # Percentage of idle cycles
+drivesys.cpu.num_mem_refs 5837119 # number of memory refs
+drivesys.cpu.num_load_insts 3750273 # Number of load instructions
+drivesys.cpu.num_store_insts 2086846 # Number of store instructions
+drivesys.cpu.num_idle_cycles 782547188.298833 # Number of idle cycles
+drivesys.cpu.num_busy_cycles 19071939.701167 # Number of busy cycles
+drivesys.cpu.not_idle_fraction 0.023792 # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction 0.976208 # Percentage of idle cycles
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce 19854 # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei 143418 # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0 60285 42.42% 42.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21 19703 13.86% 56.28% # number of times we switched to this ipl
+drivesys.cpu.kern.inst.quiesce 19898 # number of quiesce instructions executed
+drivesys.cpu.kern.inst.hwrei 143758 # number of hwrei instructions executed
+drivesys.cpu.kern.ipl_count::0 60430 42.42% 42.42% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::21 19752 13.86% 56.28% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31 61936 43.58% 100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total 142129 # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0 60285 42.91% 42.91% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21 19703 14.03% 56.94% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_count::31 62082 43.58% 100.00% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::total 142469 # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_good::0 60430 42.91% 42.91% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::21 19752 14.03% 56.94% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31 60286 42.91% 100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total 140479 # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0 197404825250 98.50% 98.50% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21 797938750 0.40% 98.90% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_good::31 60432 42.91% 100.00% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::total 140819 # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_ticks::0 197392680000 98.50% 98.50% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::21 799890500 0.40% 98.90% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31 2202592500 1.10% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total 200409764000 # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::31 2207804000 1.10% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::total 200404782000 # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31 0.973360 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total 0.988391 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::31 0.973422 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::total 0.988419 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed
drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed
drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed
@@ -673,26 +673,26 @@ drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # nu
drivesys.cpu.kern.syscall::total 22 # number of syscalls executed
drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed
drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed
-drivesys.cpu.kern.callpal::swpipl 102208 83.31% 83.37% # number of callpals executed
+drivesys.cpu.kern.callpal::swpipl 102452 83.31% 83.37% # number of callpals executed
drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed
drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed
-drivesys.cpu.kern.callpal::rti 20014 16.31% 99.97% # number of callpals executed
+drivesys.cpu.kern.callpal::rti 20062 16.31% 99.97% # number of callpals executed
drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed
drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total 122686 # number of callpals executed
+drivesys.cpu.kern.callpal::total 122978 # number of callpals executed
drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches
drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle 19872 # number of protection mode switches
+drivesys.cpu.kern.mode_switch::idle 19920 # number of protection mode switches
drivesys.cpu.kern.mode_good::kernel 143
drivesys.cpu.kern.mode_good::user 139
drivesys.cpu.kern.mode_good::idle 4
drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total 0.014141 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::total 0.014107 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user 319665750 10.81% 13.45% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle 2560362000 86.55% 100.00% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::user 319665750 10.79% 13.43% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::idle 2564974000 86.57% 100.00% # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
@@ -704,9 +704,9 @@ drivesys.tsunami.ethernet.txTcpChecksums 2 # Nu
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-drivesys.tsunami.ethernet.descDMAReads 2087584 # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAReads 2132001 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes 50102016 # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes 51168024 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
@@ -731,9 +731,9 @@ drivesys.tsunami.ethernet.totalRxDesc 8 # to
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.postedTxIdle 19702 # number of TxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.postedTxIdle 19750 # number of TxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle 2087584 # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.totalTxIdle 2132001 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
@@ -741,49 +741,49 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts 2087605 # number of posts to CPU
+drivesys.tsunami.ethernet.postedInterrupts 2132022 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000407 # Number of seconds simulated
-sim_ticks 406952000 # Number of ticks simulated
-final_tick 4321612280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 407365500 # Number of ticks simulated
+final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 7058170696 # Simulator instruction rate (inst/s)
-host_op_rate 7056390513 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5484794115 # Simulator tick rate (ticks/s)
-host_mem_usage 514692 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-sim_insts 523432506 # Number of instructions simulated
-sim_ops 523432506 # Number of ops (including micro ops) simulated
-testsys.physmem.bytes_read::cpu.inst 144604 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 296292 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 144604 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 144604 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 27688 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 36151 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 47299 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 355334290 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 728076038 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 355334290 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 355334290 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 355334290 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 796113547 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 12024534237 # Simulator instruction rate (inst/s)
+host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9308365303 # Simulator tick rate (ticks/s)
+host_mem_usage 472492 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+sim_insts 525940622 # Number of instructions simulated
+sim_ops 525940622 # Number of ops (including micro ops) simulated
+testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 48760 # Number of bytes read from this memory
+testsys.physmem.bytes_read::tsunami.ethernet 103992 # Number of bytes read from this memory
+testsys.physmem.bytes_read::total 293888 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 141136 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 141136 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 27028 # Number of bytes written to this memory
+testsys.physmem.bytes_written::total 27028 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 35284 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 6744 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::tsunami.ethernet 4333 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::total 46361 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 3721 # Number of write requests responded to by this memory
+testsys.physmem.num_writes::total 3721 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 346460365 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 119695949 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet 255279350 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 721435664 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 346460365 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 346460365 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 66348279 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::total 66348279 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 346460365 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 186044228 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet 255279350 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 787783943 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.readReqs 0 # Total number of read requests seen
testsys.physmem.writeReqs 0 # Total number of write requests seen
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
@@ -933,7 +933,7 @@ testsys.physmem.avgRdBW 0.00 # Av
testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
@@ -958,22 +958,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 7069 # DTB read hits
+testsys.cpu.dtb.read_hits 6900 # DTB read hits
testsys.cpu.dtb.read_misses 0 # DTB read misses
testsys.cpu.dtb.read_acv 0 # DTB read access violations
testsys.cpu.dtb.read_accesses 0 # DTB read accesses
-testsys.cpu.dtb.write_hits 3933 # DTB write hits
+testsys.cpu.dtb.write_hits 3839 # DTB write hits
testsys.cpu.dtb.write_misses 0 # DTB write misses
testsys.cpu.dtb.write_acv 0 # DTB write access violations
testsys.cpu.dtb.write_accesses 0 # DTB write accesses
-testsys.cpu.dtb.data_hits 11002 # DTB hits
+testsys.cpu.dtb.data_hits 10739 # DTB hits
testsys.cpu.dtb.data_misses 0 # DTB misses
testsys.cpu.dtb.data_acv 0 # DTB access violations
testsys.cpu.dtb.data_accesses 0 # DTB accesses
-testsys.cpu.itb.fetch_hits 5992 # ITB hits
+testsys.cpu.itb.fetch_hits 5847 # ITB hits
testsys.cpu.itb.fetch_misses 0 # ITB misses
testsys.cpu.itb.fetch_acv 0 # ITB acv
-testsys.cpu.itb.fetch_accesses 5992 # ITB accesses
+testsys.cpu.itb.fetch_accesses 5847 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations
@@ -986,58 +986,58 @@ testsys.cpu.itb.data_hits 0 # DT
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 821760 # number of cpu cycles simulated
+testsys.cpu.numCycles 799188 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 36151 # Number of instructions committed
-testsys.cpu.committedOps 36151 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 33514 # Number of integer alu accesses
+testsys.cpu.committedInsts 35284 # Number of instructions committed
+testsys.cpu.committedOps 35284 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 32710 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-testsys.cpu.num_func_calls 2388 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 2348 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 33514 # number of integer instructions
+testsys.cpu.num_func_calls 2330 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 2292 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 32710 # number of integer instructions
testsys.cpu.num_fp_insts 0 # number of float instructions
-testsys.cpu.num_int_register_reads 43768 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 26496 # number of times the integer registers were written
+testsys.cpu.num_int_register_reads 42720 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 25860 # number of times the integer registers were written
testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 11043 # number of memory refs
-testsys.cpu.num_load_insts 7109 # Number of load instructions
-testsys.cpu.num_store_insts 3934 # Number of store instructions
-testsys.cpu.num_idle_cycles 785260.061817 # Number of idle cycles
-testsys.cpu.num_busy_cycles 36499.938183 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.044417 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.955583 # Percentage of idle cycles
+testsys.cpu.num_mem_refs 10779 # number of memory refs
+testsys.cpu.num_load_insts 6939 # Number of load instructions
+testsys.cpu.num_store_insts 3840 # Number of store instructions
+testsys.cpu.num_idle_cycles 764577.129267 # Number of idle cycles
+testsys.cpu.num_busy_cycles 34610.870733 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.043308 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.956692 # Percentage of idle cycles
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 398338500 96.95% 96.95% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.74% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.75% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 9258500 2.25% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 410880000 # number of cycles we spent at this ipl
+testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei 288 # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0 120 41.81% 41.81% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21 39 13.59% 55.40% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::22 1 0.35% 55.75% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31 127 44.25% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 287 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0 120 42.86% 42.86% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21 39 13.93% 56.79% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::22 1 0.36% 57.14% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::31 120 42.86% 100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total 280 # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0 387349500 96.94% 96.94% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21 3159000 0.79% 97.73% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 9042500 2.26% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 399594000 # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
-testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
-testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 254 # number of callpals executed
+testsys.cpu.kern.ipl_used::31 0.944882 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.975610 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.callpal::swpipl 207 83.47% 83.47% # number of callpals executed
+testsys.cpu.kern.callpal::rdps 1 0.40% 83.87% # number of callpals executed
+testsys.cpu.kern.callpal::rti 40 16.13% 100.00% # number of callpals executed
+testsys.cpu.kern.callpal::total 248 # number of callpals executed
testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle 40 # number of protection mode switches
testsys.cpu.kern.mode_good::kernel 0
testsys.cpu.kern.mode_good::user 0
testsys.cpu.kern.mode_good::idle 0
@@ -1049,9 +1049,9 @@ testsys.cpu.kern.mode_ticks::kernel 0 # nu
testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
-testsys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAReads 4333 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 103992 # number of descriptor bytes read w/ DMA
testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
@@ -1068,9 +1068,9 @@ testsys.tsunami.ethernet.totalRxDesc 0 # to
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxIdle 39 # number of TxIdle interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.totalTxIdle 4333 # total number of TxIdle written to ISR
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
@@ -1078,34 +1078,34 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU
+testsys.tsunami.ethernet.postedInterrupts 4333 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total 296296 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::tsunami.ethernet 104016 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::total 298576 # Number of bytes read from this memory
drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory
drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory
drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total 47300 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::tsunami.ethernet 4334 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::total 47395 # Number of read requests responded to by this memory
drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory
drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst 355344119 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total 728085868 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst 355344119 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total 355344119 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst 355344119 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total 796123376 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.inst 354983424 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.data 122622068 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::tsunami.ethernet 255338265 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::total 732943757 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::cpu.inst 354983424 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::total 354983424 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::cpu.data 67968446 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::total 67968446 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.inst 354983424 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.data 190590514 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::tsunami.ethernet 255338265 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::total 800912203 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.readReqs 0 # Total number of read requests seen
drivesys.physmem.writeReqs 0 # Total number of write requests seen
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
@@ -1255,7 +1255,7 @@ drivesys.physmem.avgRdBW 0.00 # Av
drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
@@ -1308,7 +1308,7 @@ drivesys.cpu.itb.data_hits 0 # DT
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
-drivesys.cpu.numCycles 1628160 # number of cpu cycles simulated
+drivesys.cpu.numCycles 1624320 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
drivesys.cpu.committedInsts 36152 # Number of instructions committed
@@ -1326,10 +1326,10 @@ drivesys.cpu.num_fp_register_writes 0 # nu
drivesys.cpu.num_mem_refs 11043 # number of memory refs
drivesys.cpu.num_load_insts 7109 # Number of load instructions
drivesys.cpu.num_store_insts 3934 # Number of store instructions
-drivesys.cpu.num_idle_cycles 1592000.182518 # Number of idle cycles
-drivesys.cpu.num_busy_cycles 36159.817482 # Number of busy cycles
-drivesys.cpu.not_idle_fraction 0.022209 # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction 0.977791 # Percentage of idle cycles
+drivesys.cpu.num_idle_cycles 1588282.082886 # Number of idle cycles
+drivesys.cpu.num_busy_cycles 36037.917114 # Number of busy cycles
+drivesys.cpu.not_idle_fraction 0.022186 # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction 0.977814 # Percentage of idle cycles
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
@@ -1343,11 +1343,11 @@ drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # nu
drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0 400769000 98.46% 98.46% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::0 399809000 98.46% 98.46% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.85% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total 407040000 # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::total 406080000 # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
@@ -1371,9 +1371,9 @@ drivesys.cpu.kern.mode_ticks::kernel 0 # nu
drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
-drivesys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAReads 4334 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes 104016 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
@@ -1392,7 +1392,7 @@ drivesys.tsunami.ethernet.coalescedTxOk 0 # av
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.totalTxIdle 4334 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
@@ -1400,7 +1400,7 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU
+drivesys.tsunami.ethernet.postedInterrupts 4334 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------