diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-23 04:49:48 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-23 04:49:48 -0400 |
| commit | a4329af937870e832caf3fc34e2ca448f2322ecc (patch) | |
| tree | 75f99dc15123d371a4d55f693b0d3044721bc7b3 /tests/quick/fs | |
| parent | 69e82539fd81299751e1000c0dac49f2eddbbdb6 (diff) | |
| download | gem5-a4329af937870e832caf3fc34e2ca448f2322ecc.tar.xz | |
stats: Update stats for DMA port send
This patch updates the stats after removing the zero-time send used in
the DMA port.
Diffstat (limited to 'tests/quick/fs')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 1602 | ||||
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 760 |
2 files changed, 1181 insertions, 1181 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0a013f420..db4dfffca 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,320 +1,320 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.203695 # Number of seconds simulated -sim_ticks 1203694548000 # Number of ticks simulated -final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.203606 # Number of seconds simulated +sim_ticks 1203606499000 # Number of ticks simulated +final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 610810 # Simulator instruction rate (inst/s) -host_op_rate 778429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11963163223 # Simulator tick rate (ticks/s) -host_mem_usage 383784 # Number of bytes of host memory used -host_seconds 100.62 # Real time elapsed on the host -sim_insts 61457649 # Number of instructions simulated -sim_ops 78322983 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 418240 # Simulator instruction rate (inst/s) +host_op_rate 532998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8191230777 # Simulator tick rate (ticks/s) +host_mem_usage 386340 # Number of bytes of host memory used +host_seconds 146.94 # Real time elapsed on the host +sim_insts 61455549 # Number of instructions simulated +sim_ops 78317886 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory -system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory +system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory +system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82960 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6655189 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65060 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821896 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43120999 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 294430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3538482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 302931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4409557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51666772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 294430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 302931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597361 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3459216 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14123 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2500920 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5974260 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3459216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43120999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 294430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3552606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 302931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6910477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57641032 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 70187 # number of replacements -system.l2c.tagsinuse 53228.642974 # Cycle average of tags in use -system.l2c.total_refs 1643789 # Total number of references to valid blocks. -system.l2c.sampled_refs 135350 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.144728 # Average number of references to valid blocks. +system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70188 # number of replacements +system.l2c.tagsinuse 53228.072476 # Cycle average of tags in use +system.l2c.total_refs 1643838 # Total number of references to valid blocks. +system.l2c.sampled_refs 135351 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.145001 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40454.040636 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40453.574010 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.003088 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3394.914064 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2735.381228 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.669984 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3118.851455 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3522.782116 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.617280 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.003089 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3394.604865 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2735.402876 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.669960 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3118.943835 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3522.873439 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.617273 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.051802 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.051798 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.047590 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.053753 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.812205 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.047591 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.053755 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.812196 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 278283 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 124654 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 278308 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 124645 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5210 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 576279 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 223386 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1213325 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571443 # number of Writeback hits -system.l2c.Writeback_hits::total 571443 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 576222 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223363 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1213263 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571562 # number of Writeback hits +system.l2c.Writeback_hits::total 571562 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 888 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1880 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 95 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 286 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 39230 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 70245 # number of ReadExReq hits +system.l2c.UpgradeReq_hits::cpu1.data 878 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1870 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 189 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 285 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 39231 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 70244 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 278283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 163884 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 278308 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 163876 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5210 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 576279 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 293631 # number of demand (read+write) hits -system.l2c.demand_hits::total 1322800 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 576222 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 293607 # number of demand (read+write) hits +system.l2c.demand_hits::total 1322738 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits -system.l2c.overall_hits::cpu0.inst 278283 # number of overall hits -system.l2c.overall_hits::cpu0.data 163884 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits +system.l2c.overall_hits::cpu0.inst 278308 # number of overall hits +system.l2c.overall_hits::cpu0.data 163876 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5210 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits -system.l2c.overall_hits::cpu1.inst 576279 # number of overall hits -system.l2c.overall_hits::cpu1.data 293631 # number of overall hits -system.l2c.overall_hits::total 1322800 # number of overall hits +system.l2c.overall_hits::cpu1.inst 576222 # number of overall hits +system.l2c.overall_hits::cpu1.data 293607 # number of overall hits +system.l2c.overall_hits::total 1322738 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5124 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6001 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5119 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6000 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5692 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5607 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5697 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5608 # number of ReadReq misses system.l2c.ReadReq_misses::total 22431 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4012 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4909 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8921 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4011 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4908 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8919 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 652 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 388 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1043 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 61449 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::total 1040 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 61450 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 78839 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140288 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140289 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5124 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5119 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 67450 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5692 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 84446 # number of demand (read+write) misses -system.l2c.demand_misses::total 162719 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5697 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 84447 # number of demand (read+write) misses +system.l2c.demand_misses::total 162720 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5124 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5119 # number of overall misses system.l2c.overall_misses::cpu0.data 67450 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5692 # number of overall misses -system.l2c.overall_misses::cpu1.data 84446 # number of overall misses -system.l2c.overall_misses::total 162719 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5697 # number of overall misses +system.l2c.overall_misses::cpu1.data 84447 # number of overall misses +system.l2c.overall_misses::total 162720 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 156500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 268094000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 313174000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 298650000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 293295000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1173581500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 15964999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 31408500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 47373499 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1462500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6173000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 7635500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3221682991 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4131389996 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7353072987 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 267825000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 313081000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 156000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 298083000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 292866500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1172220000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 15780999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 31202500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 46983499 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1357500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6172500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 7530000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3221673990 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4120152496 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7341826486 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 156500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 268094000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3534856991 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 298650000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4424684996 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8526654487 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 267825000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3534754990 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 156000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 298083000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4413018996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8514046486 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 156500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 268094000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3534856991 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 160000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 298650000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4424684996 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8526654487 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 267825000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3534754990 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 156000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 298083000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4413018996 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8514046486 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 2524 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 1493 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 283407 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 130655 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5211 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 283427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 130645 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5213 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 1502 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 581971 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 228993 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1235756 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 571443 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 571443 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5004 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5797 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10801 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 846 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 483 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1329 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 100679 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 149084 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249763 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 581919 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 228971 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1235694 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 571562 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 571562 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5003 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5786 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10789 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 841 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 484 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1325 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 100681 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 149083 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249764 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 2524 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 1493 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 283407 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 231334 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5211 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 283427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 231326 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5213 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 1502 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 581971 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 378077 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1485519 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 581919 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 378054 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1485458 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 2524 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 1493 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 283407 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 231334 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5211 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 283427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 231326 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5213 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 1502 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 581971 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 378077 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1485519 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 581919 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 378054 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1485458 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002009 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018080 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.045930 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009781 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024485 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018152 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801759 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.846817 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.825942 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.774232 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.803313 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.784801 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.610346 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.528823 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.561684 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018061 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.045926 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009790 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024492 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018153 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801719 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848254 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.826675 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.775268 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.801653 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.784906 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.610344 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.528826 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.561686 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.002009 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018080 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.291570 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009781 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.223357 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.109537 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018061 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.291580 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009790 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.223373 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109542 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.002009 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018080 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.291570 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009781 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.223357 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.109537 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018061 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.291580 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009790 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.223373 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109542 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52166.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52321.233411 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52186.968839 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52468.376669 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52308.721241 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52319.624627 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3979.311815 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6398.146262 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5310.335052 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2232.824427 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15909.793814 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 7320.709492 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52428.566632 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52402.871624 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52414.126561 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52319.789021 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52180.166667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52322.801474 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52222.985021 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52258.927377 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3934.430067 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6357.477588 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5267.798968 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2082.055215 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15908.505155 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 7240.384615 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52427.566965 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52260.334302 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52333.586283 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52321.233411 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52407.071772 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52468.376669 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52396.620278 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52401.099361 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52323.294530 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52321.233411 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52407.071772 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52468.376669 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52396.620278 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52401.099361 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52323.294530 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,8 +323,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65060 # number of writebacks -system.l2c.writebacks::total 65060 # number of writebacks +system.l2c.writebacks::writebacks 65061 # number of writebacks +system.l2c.writebacks::total 65061 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -333,149 +333,149 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5123 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6001 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5118 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6000 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5692 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 5607 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5697 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 5608 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 22430 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4012 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4909 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8921 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4011 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4908 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8919 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 652 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 388 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1043 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 61449 # number of ReadExReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1040 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 61450 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 78839 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140288 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140289 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5123 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5118 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 67450 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5692 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 84446 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162718 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5697 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 84447 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5123 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5118 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 67450 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5692 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 84446 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162718 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5697 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 84447 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162719 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 120000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 204994000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 240097000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 124000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 228616000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 224783500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 898774500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 160670998 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 196506499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 357177497 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26201999 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15527999 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 41729998 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2458624491 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3165174496 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5623798987 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 204790500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 240017000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 120000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 227965500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 224340500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 897393500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 160489997 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 196385999 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 356875996 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26081499 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15523499 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 41604998 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2458644990 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3153935496 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5612580486 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 120000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 204994000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2698721491 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 124000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 228616000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3389957996 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6522573487 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 204790500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2698661990 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 120000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 227965500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3378275996 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6509973986 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 120000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 204994000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2698721491 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 124000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 228616000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3389957996 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6522573487 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 204790500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2698661990 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 120000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 227965500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3378275996 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6509973986 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11136775500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11136863000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155704815500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167111072500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1070730500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30910255000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31980985500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155607031000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167013375500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1070738498 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30849143000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31919881498 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12207506000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12207601498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186615070500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 199092058000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186456174000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198933256998 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045930 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024485 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018151 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801759 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.846817 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.825942 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.774232 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.803313 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784801 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610346 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528823 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561684 # mshr miss rate for ReadExReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045926 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024492 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018152 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801719 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848254 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.826675 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.775268 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.801653 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784906 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610344 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528826 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.561686 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.109536 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.109541 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.109536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.109541 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40009.498417 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40089.798466 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40070.196166 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.606680 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40029.842942 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.831745 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40003.051908 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40020.615979 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40009.585810 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.813699 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.319169 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40087.526994 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40002.833333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40003.655492 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40008.626839 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40012.464971 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40013.447229 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40013.005494 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.299080 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40009.018041 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40004.805769 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.496176 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40004.762820 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.274170 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,9 +498,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 4800541 # DTB read hits +system.cpu0.dtb.read_hits 4800569 # DTB read hits system.cpu0.dtb.read_misses 2116 # DTB read misses -system.cpu0.dtb.write_hits 4101169 # DTB write hits +system.cpu0.dtb.write_hits 4101188 # DTB write hits system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 4802657 # DTB read accesses -system.cpu0.dtb.write_accesses 4101574 # DTB write accesses +system.cpu0.dtb.read_accesses 4802685 # DTB read accesses +system.cpu0.dtb.write_accesses 4101593 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 8901710 # DTB hits +system.cpu0.dtb.hits 8901757 # DTB hits system.cpu0.dtb.misses 2521 # DTB misses -system.cpu0.dtb.accesses 8904231 # DTB accesses -system.cpu0.itb.inst_hits 19425295 # ITB inst hits +system.cpu0.dtb.accesses 8904278 # DTB accesses +system.cpu0.itb.inst_hits 19425317 # ITB inst hits system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19426645 # ITB inst accesses -system.cpu0.itb.hits 19425295 # DTB hits +system.cpu0.itb.inst_accesses 19426667 # ITB inst accesses +system.cpu0.itb.hits 19425317 # DTB hits system.cpu0.itb.misses 1350 # DTB misses -system.cpu0.itb.accesses 19426645 # DTB accesses -system.cpu0.numCycles 2405961611 # number of cpu cycles simulated +system.cpu0.itb.accesses 19426667 # DTB accesses +system.cpu0.numCycles 2405785466 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 19048182 # Number of instructions committed -system.cpu0.committedOps 25051772 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 22684080 # Number of integer alu accesses +system.cpu0.committedInsts 19048205 # Number of instructions committed +system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 868675 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 2620305 # number of instructions that are conditional controls -system.cpu0.num_int_insts 22684080 # number of integer instructions +system.cpu0.num_func_calls 868672 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls +system.cpu0.num_int_insts 22684157 # number of integer instructions system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 128950966 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23731370 # number of times the integer registers were written +system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 9388163 # number of memory refs -system.cpu0.num_load_insts 5047859 # Number of load instructions -system.cpu0.num_store_insts 4340304 # Number of store instructions -system.cpu0.num_idle_cycles 2301502404.823749 # Number of idle cycles -system.cpu0.num_busy_cycles 104459206.176251 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043417 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956583 # Percentage of idle cycles +system.cpu0.num_mem_refs 9388218 # number of memory refs +system.cpu0.num_load_insts 5047895 # Number of load instructions +system.cpu0.num_store_insts 4340323 # Number of store instructions +system.cpu0.num_idle_cycles 2301327262.807119 # Number of idle cycles +system.cpu0.num_busy_cycles 104458203.192881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043420 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956580 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 34020 # number of quiesce instructions executed -system.cpu0.icache.replacements 283184 # number of replacements -system.cpu0.icache.tagsinuse 509.502628 # Cycle average of tags in use -system.cpu0.icache.total_refs 19141582 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 283696 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.472160 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed +system.cpu0.icache.replacements 283204 # number of replacements +system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use +system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.502628 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 19141582 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 19141582 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19141582 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 19141582 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19141582 # number of overall hits -system.cpu0.icache.overall_hits::total 19141582 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 283696 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 283696 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 283696 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 283696 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 283696 # number of overall misses -system.cpu0.icache.overall_misses::total 283696 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929923500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 3929923500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 3929923500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 3929923500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 3929923500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 3929923500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425278 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 19425278 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19425278 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 19425278 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19425278 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 19425278 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014604 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014604 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014604 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014604 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014604 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014604 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.586924 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13852.586924 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13852.586924 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13852.586924 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 19141584 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 19141584 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19141584 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 19141584 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19141584 # number of overall hits +system.cpu0.icache.overall_hits::total 19141584 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 283716 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 283716 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 283716 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 283716 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 283716 # number of overall misses +system.cpu0.icache.overall_misses::total 283716 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929859500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 3929859500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 3929859500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 3929859500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 3929859500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 3929859500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 19425300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 19425300 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 19425300 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 19425300 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 19425300 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014605 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014605 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014605 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014605 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014605 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014605 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13851.384836 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13851.384836 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13851.384836 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13851.384836 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,120 +615,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283696 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 283696 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 283696 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 283696 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 283696 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 283696 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362531500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362531500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362531500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 3362531500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362531500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 3362531500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283716 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 283716 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 283716 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 283716 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 283716 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 283716 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362427500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362427500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362427500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 3362427500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362427500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 3362427500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 353907000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 353907000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 353907000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 353907000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014604 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014604 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014604 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11852.586924 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014605 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014605 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11851.384836 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 220187 # number of replacements -system.cpu0.dcache.tagsinuse 456.524851 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8560144 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 220557 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.811482 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 220249 # number of replacements +system.cpu0.dcache.tagsinuse 456.517669 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8560161 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 220619 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.800652 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 656029000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 456.524851 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.891650 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.891650 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4452407 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4452407 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3852535 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3852535 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117731 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 117731 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117849 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 117849 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8304942 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8304942 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8304942 # number of overall hits -system.cpu0.dcache.overall_hits::total 8304942 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 146461 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 146461 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 116958 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 116958 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7880 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 7880 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7697 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7697 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 263419 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 263419 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 263419 # number of overall misses -system.cpu0.dcache.overall_misses::total 263419 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991314500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 1991314500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199641500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4199641500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70263500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 70263500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 66334500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 66334500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 6190956000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 6190956000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 6190956000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 6190956000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4598868 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 4598868 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3969493 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 3969493 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 456.517669 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.891636 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.891636 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 4452439 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4452439 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3852551 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3852551 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117730 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 117730 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117854 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 117854 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8304990 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8304990 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8304990 # number of overall hits +system.cpu0.dcache.overall_hits::total 8304990 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 146457 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 146457 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 116961 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 116961 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7881 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 7881 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7692 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7692 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 263418 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 263418 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 263418 # number of overall misses +system.cpu0.dcache.overall_misses::total 263418 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991139500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 1991139500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199443500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4199443500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70259000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 70259000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 66131000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 66131000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 6190583000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 6190583000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6190583000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 6190583000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4598896 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 4598896 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3969512 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 3969512 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125611 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 125611 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125546 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 125546 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8568361 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 8568361 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8568361 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 8568361 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031847 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031847 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029464 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.029464 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062733 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062733 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061308 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 8568408 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 8568408 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8568408 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 8568408 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031846 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031846 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029465 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.029465 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062741 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062741 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061268 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061268 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13596.209913 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13596.209913 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35907.261581 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35907.261581 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8916.687817 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8916.687817 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8618.227881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8618.227881 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13595.386359 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13595.386359 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35904.647703 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35904.647703 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8914.985408 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8914.985408 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8597.373895 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8597.373895 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23500.987024 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23500.987024 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,66 +737,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 204960 # number of writebacks -system.cpu0.dcache.writebacks::total 204960 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146461 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 146461 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116958 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 116958 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7880 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7880 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7695 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7695 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 263419 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 263419 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 263419 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 263419 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698392500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698392500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965725500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965725500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54503500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54503500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 205058 # number of writebacks +system.cpu0.dcache.writebacks::total 205058 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146457 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 146457 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116961 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 116961 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7881 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7881 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7690 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7690 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 263418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -806,26 +806,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10590618 # DTB read hits -system.cpu1.dtb.read_misses 5230 # DTB read misses -system.cpu1.dtb.write_hits 7384755 # DTB write hits -system.cpu1.dtb.write_misses 1835 # DTB write misses +system.cpu1.dtb.read_hits 10589201 # DTB read hits +system.cpu1.dtb.read_misses 5231 # DTB read misses +system.cpu1.dtb.write_hits 7383574 # DTB write hits +system.cpu1.dtb.write_misses 1834 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10595848 # DTB read accesses -system.cpu1.dtb.write_accesses 7386590 # DTB write accesses +system.cpu1.dtb.read_accesses 10594432 # DTB read accesses +system.cpu1.dtb.write_accesses 7385408 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17975373 # DTB hits +system.cpu1.dtb.hits 17972775 # DTB hits system.cpu1.dtb.misses 7065 # DTB misses -system.cpu1.dtb.accesses 17982438 # DTB accesses -system.cpu1.itb.inst_hits 43340388 # ITB inst hits +system.cpu1.dtb.accesses 17979840 # DTB accesses +system.cpu1.itb.inst_hits 43338256 # ITB inst hits system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -842,79 +842,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses -system.cpu1.itb.hits 43340388 # DTB hits +system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses +system.cpu1.itb.hits 43338256 # DTB hits system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 43343405 # DTB accesses -system.cpu1.numCycles 2407389096 # number of cpu cycles simulated +system.cpu1.itb.accesses 43341273 # DTB accesses +system.cpu1.numCycles 2407212998 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42409467 # Number of instructions committed -system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses +system.cpu1.committedInsts 42407344 # Number of instructions committed +system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1335008 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47739499 # number of integer instructions +system.cpu1.num_func_calls 1334953 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47734651 # number of integer instructions system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read -system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written +system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read +system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 18684058 # number of memory refs -system.cpu1.num_load_insts 11000639 # Number of load instructions -system.cpu1.num_store_insts 7683419 # Number of store instructions -system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles -system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles -system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles +system.cpu1.num_mem_refs 18681443 # number of memory refs +system.cpu1.num_load_insts 10999206 # Number of load instructions +system.cpu1.num_store_insts 7682237 # Number of store instructions +system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles +system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles +system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 56706 # number of quiesce instructions executed -system.cpu1.icache.replacements 582628 # number of replacements -system.cpu1.icache.tagsinuse 479.068937 # Cycle average of tags in use -system.cpu1.icache.total_refs 42757244 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 583140 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 73.322434 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed +system.cpu1.icache.replacements 582576 # number of replacements +system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use +system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.068937 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935682 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935682 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 42757244 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 42757244 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 42757244 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 42757244 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 42757244 # number of overall hits -system.cpu1.icache.overall_hits::total 42757244 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 583140 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 583140 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 583140 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 583140 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 583140 # number of overall misses -system.cpu1.icache.overall_misses::total 583140 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7853505000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7853505000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7853505000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7853505000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7853505000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7853505000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43340384 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43340384 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43340384 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43340384 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43340384 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43340384 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013455 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013455 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013455 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013455 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013455 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013455 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.614981 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.614981 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13467.614981 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13467.614981 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits +system.cpu1.icache.overall_hits::total 42755164 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 583088 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 583088 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 583088 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 583088 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 583088 # number of overall misses +system.cpu1.icache.overall_misses::total 583088 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7852005500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7852005500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7852005500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7852005500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7852005500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7852005500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43338252 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43338252 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43338252 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43338252 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43338252 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43338252 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013454 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013454 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013454 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013454 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013454 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013454 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13466.244375 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13466.244375 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13466.244375 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13466.244375 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -923,120 +923,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583140 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 583140 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 583140 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 583140 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 583140 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 583140 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6687225000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6687225000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6687225000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6687225000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6687225000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6687225000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583088 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 583088 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 583088 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 583088 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 583088 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 583088 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6685829500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6685829500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6685829500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6685829500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6685829500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6685829500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5251000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5251000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5251000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5251000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013455 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013455 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013455 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11467.614981 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11467.614981 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11467.614981 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013454 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013454 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11466.244375 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 401361 # number of replacements -system.cpu1.dcache.tagsinuse 473.304740 # Cycle average of tags in use -system.cpu1.dcache.total_refs 15681919 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 401873 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.022077 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 401285 # number of replacements +system.cpu1.dcache.tagsinuse 473.299929 # Cycle average of tags in use +system.cpu1.dcache.total_refs 15679399 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 401797 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.023186 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 473.304740 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.924423 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.924423 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 9101949 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9101949 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6323711 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6323711 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111853 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 111853 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114473 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 114473 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15425660 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15425660 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15425660 # number of overall hits -system.cpu1.dcache.overall_hits::total 15425660 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 253200 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 253200 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 178129 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 178129 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13100 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13100 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10404 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10404 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 431329 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 431329 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 431329 # number of overall misses -system.cpu1.dcache.overall_misses::total 431329 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3278248500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3278248500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5660664500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5660664500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115759000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 115759000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63020500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 63020500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8938913000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8938913000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8938913000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8938913000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9355149 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9355149 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6501840 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6501840 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124953 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 124953 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124877 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 124877 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 15856989 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 15856989 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 15856989 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 15856989 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027065 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027065 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027397 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027397 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104839 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104839 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083314 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083314 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027201 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027201 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027201 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027201 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.268957 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.268957 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31778.455501 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 31778.455501 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8836.564885 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8836.564885 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6057.333718 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6057.333718 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20724.117785 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20724.117785 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 473.299929 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.924414 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.924414 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9100620 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9100620 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6322619 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6322619 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111839 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 111839 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114463 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 114463 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15423239 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15423239 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15423239 # number of overall hits +system.cpu1.dcache.overall_hits::total 15423239 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 253127 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 253127 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 178055 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 178055 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13099 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13099 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10399 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10399 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 431182 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 431182 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 431182 # number of overall misses +system.cpu1.dcache.overall_misses::total 431182 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3277248500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3277248500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5648876500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5648876500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115793500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 115793500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63008000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 63008000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8926125000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8926125000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8926125000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8926125000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9353747 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9353747 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6500674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6500674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124938 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 124938 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 124862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15854421 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15854421 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15854421 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15854421 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027062 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027062 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027390 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027390 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104844 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104844 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027196 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027196 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027196 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027196 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.052270 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.052270 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31725.458426 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31725.458426 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8839.873273 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8839.873273 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6059.044139 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6059.044139 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20701.525110 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20701.525110 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,66 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks -system.cpu1.dcache.writebacks::total 366483 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks +system.cpu1.dcache.writebacks::total 366504 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1126,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index e07e69ea6..d1abeb8c8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.624688 # Number of seconds simulated -sim_ticks 2624688000000 # Number of ticks simulated -final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.624627 # Number of seconds simulated +sim_ticks 2624627401000 # Number of ticks simulated +final_tick 2624627401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 509092 # Simulator instruction rate (inst/s) -host_op_rate 647812 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22195691402 # Simulator tick rate (ticks/s) -host_mem_usage 379628 # Number of bytes of host memory used -host_seconds 118.25 # Real time elapsed on the host -sim_insts 60201138 # Number of instructions simulated -sim_ops 76605123 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory +host_inst_rate 463403 # Simulator instruction rate (inst/s) +host_op_rate 589674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20203281292 # Simulator tick rate (ticks/s) +host_mem_usage 381220 # Number of bytes of host memory used +host_seconds 129.91 # Real time elapsed on the host +sim_insts 60201162 # Number of instructions simulated +sim_ops 76605148 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 123834568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory -system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9049808 # Number of bytes read from this memory +system.physmem.bytes_read::total 133590712 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3677120 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6693192 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15479321 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 141437 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15637997 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57455 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811473 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47181771 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 268924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3448035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50898925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 268924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1401006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1149143 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550149 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1401006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47181771 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 268924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4597178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53449074 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -69,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996726 # DTB read hits -system.cpu.dtb.read_misses 7357 # DTB read misses -system.cpu.dtb.write_hits 11231612 # DTB write hits +system.cpu.dtb.read_hits 14996727 # DTB read hits +system.cpu.dtb.read_misses 7361 # DTB read misses +system.cpu.dtb.write_hits 11231610 # DTB write hits system.cpu.dtb.write_misses 2211 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15004083 # DTB read accesses -system.cpu.dtb.write_accesses 11233823 # DTB write accesses +system.cpu.dtb.read_accesses 15004088 # DTB read accesses +system.cpu.dtb.write_accesses 11233821 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26228338 # DTB hits -system.cpu.dtb.misses 9568 # DTB misses -system.cpu.dtb.accesses 26237906 # DTB accesses -system.cpu.itb.inst_hits 61495107 # ITB inst hits +system.cpu.dtb.hits 26228337 # DTB hits +system.cpu.dtb.misses 9572 # DTB misses +system.cpu.dtb.accesses 26237909 # DTB accesses +system.cpu.itb.inst_hits 61495131 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -105,79 +105,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61499578 # ITB inst accesses -system.cpu.itb.hits 61495107 # DTB hits +system.cpu.itb.inst_accesses 61499602 # ITB inst accesses +system.cpu.itb.hits 61495131 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61499578 # DTB accesses -system.cpu.numCycles 5249376000 # number of cpu cycles simulated +system.cpu.itb.accesses 61499602 # DTB accesses +system.cpu.numCycles 5249254802 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60201138 # Number of instructions committed -system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses +system.cpu.committedInsts 60201162 # Number of instructions committed +system.cpu.committedOps 76605148 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872531 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139913 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872510 # number of integer instructions +system.cpu.num_func_calls 2139915 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948068 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872531 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written +system.cpu.num_int_register_reads 394780405 # number of times the integer registers were read +system.cpu.num_int_register_writes 74180740 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27395681 # number of memory refs -system.cpu.num_load_insts 15660705 # Number of load instructions -system.cpu.num_store_insts 11734976 # Number of store instructions -system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles -system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles -system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.871278 # Percentage of idle cycles +system.cpu.num_mem_refs 27395680 # number of memory refs +system.cpu.num_load_insts 15660706 # Number of load instructions +system.cpu.num_store_insts 11734974 # Number of store instructions +system.cpu.num_idle_cycles 4573851223.612257 # Number of idle cycles +system.cpu.num_busy_cycles 675403578.387743 # Number of busy cycles +system.cpu.not_idle_fraction 0.128667 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.871333 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.replacements 855878 # number of replacements -system.cpu.icache.tagsinuse 510.920723 # Cycle average of tags in use -system.cpu.icache.total_refs 60638717 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856390 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.807362 # Average number of references to valid blocks. +system.cpu.icache.replacements 855895 # number of replacements +system.cpu.icache.tagsinuse 510.920698 # Cycle average of tags in use +system.cpu.icache.total_refs 60638724 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856407 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.805965 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.920723 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.920698 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60638717 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60638717 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60638717 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60638717 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60638717 # number of overall hits -system.cpu.icache.overall_hits::total 60638717 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses -system.cpu.icache.overall_misses::total 856390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565531500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11565531500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11565531500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11565531500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11565531500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11565531500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61495107 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61495107 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61495107 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60638724 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60638724 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60638724 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60638724 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60638724 # number of overall hits +system.cpu.icache.overall_hits::total 60638724 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856407 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856407 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856407 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856407 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856407 # number of overall misses +system.cpu.icache.overall_misses::total 856407 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11564476500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11564476500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11564476500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11564476500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11564476500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11564476500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61495131 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61495131 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61495131 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61495131 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61495131 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61495131 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.981959 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13504.981959 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13504.981959 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13504.981959 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.481989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13503.481989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13503.481989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13503.481989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,18 +186,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856390 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856390 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856390 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9852751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9852751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852751500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9852751500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856407 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856407 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856407 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856407 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856407 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856407 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9851662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9851662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851662500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9851662500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles @@ -208,90 +208,90 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.981959 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.981959 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.481989 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.481989 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627203 # number of replacements -system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use -system.cpu.dcache.total_refs 23656923 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627715 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.687363 # Average number of references to valid blocks. +system.cpu.dcache.replacements 627232 # number of replacements +system.cpu.dcache.tagsinuse 511.878513 # Cycle average of tags in use +system.cpu.dcache.total_refs 23656893 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627744 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.685574 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.878513 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13196260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13196266 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196266 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973744 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973744 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236294 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236294 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23170043 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23170043 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23170043 # number of overall hits -system.cpu.dcache.overall_hits::total 23170043 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368704 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368704 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619214 # number of overall misses -system.cpu.dcache.overall_misses::total 619214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201105500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5201105500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8977284500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8977284500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14178390000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14178390000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14178390000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14178390000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10224293 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 23170010 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23170010 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23170010 # number of overall hits +system.cpu.dcache.overall_hits::total 23170010 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368699 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368699 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250547 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250547 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11397 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11397 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619246 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619246 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619246 # number of overall misses +system.cpu.dcache.overall_misses::total 619246 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5200667500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5200667500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8968842000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8968842000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154755000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 154755000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14169509500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14169509500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14169509500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14169509500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564965 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564965 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10224291 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10224291 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23789257 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23789257 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23789257 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23789257 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027181 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027181 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024501 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024501 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.452602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.452602 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35836.032494 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35836.032494 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22897.398961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22897.398961 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 23789256 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23789256 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23789256 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23789256 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027180 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027180 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024505 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046013 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046013 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026030 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026030 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026030 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026030 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.455941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.455941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35797.044068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35797.044068 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.573309 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.573309 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22881.874893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22881.874893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,54 +300,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks -system.cpu.dcache.writebacks::total 595968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368704 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368704 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619214 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619214 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619214 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463697500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463697500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8476264500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8476264500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939962000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12939962000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939962000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12939962000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162296000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162296000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387676000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387676000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223549972000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223549972000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024501 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046025 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046025 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.452602 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.452602 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33836.032494 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33836.032494 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595999 # number of writebacks +system.cpu.dcache.writebacks::total 595999 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368699 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368699 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250547 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250547 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11397 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11397 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619246 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619246 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619246 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619246 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463269500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463269500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8467748000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8467748000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131961000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131961000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931017500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12931017500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931017500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12931017500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182084322500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182084322500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41323476000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41323476000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223407798500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 223407798500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027180 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027180 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046013 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046013 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026030 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026030 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.455941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.455941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33797.044068 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33797.044068 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.573309 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.573309 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -355,141 +355,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 61913 # number of replacements -system.cpu.l2cache.tagsinuse 50867.983864 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683055 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.221690 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2574063892000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37864.330390 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 61916 # number of replacements +system.cpu.l2cache.tagsinuse 50867.720143 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1683066 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127296 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 13.221672 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2574019400000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37864.952088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885583 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6985.667850 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6014.098622 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.577764 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 6985.681192 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6013.199864 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.577773 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.106593 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.091768 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.776184 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8765 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844136 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370246 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226698 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595968 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595968 # number of Writeback hits +system.cpu.l2cache.occ_percent::cpu.data 0.091754 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.776180 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8772 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 844153 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370237 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226711 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595999 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595999 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 114435 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 114435 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844136 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484681 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1341133 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8765 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844136 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484681 # number of overall hits -system.cpu.l2cache.overall_hits::total 1341133 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 114469 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 114469 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 8772 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 844153 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 484706 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1341180 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 8772 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 844153 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 484706 # number of overall hits +system.cpu.l2cache.overall_hits::total 1341180 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20481 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20482 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2873 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2873 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133179 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133179 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 10615 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143034 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153657 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143038 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153661 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 10615 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143034 # number of overall misses -system.cpu.l2cache.overall_misses::total 153657 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143038 # number of overall misses +system.cpu.l2cache.overall_misses::total 153661 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553362500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513127500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1066907500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6934471000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6934471000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 552086500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512764500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1065268500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1041000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1041000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6925666500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6925666500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 553362500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7447598500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8001378500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 552086500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7438431000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7990935000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 553362500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7447598500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8001378500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8770 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3554 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854751 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380104 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 595968 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 595968 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 552086500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7438431000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7990935000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8777 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3552 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 854768 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 380096 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1247193 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 595999 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 595999 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2899 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247611 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247611 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8770 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3554 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854751 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627715 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494790 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8770 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3554 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854751 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627715 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494790 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247648 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247648 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8777 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3552 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 854768 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627744 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494841 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8777 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3552 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 854768 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627744 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494841 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000844 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025935 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025938 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.016422 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991031 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991031 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537844 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.537844 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537775 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.537775 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000570 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000844 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012419 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.227865 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.102795 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.227860 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.102794 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000570 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000844 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012419 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.227865 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.102795 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.227860 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.102794 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52130.240226 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52051.886792 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52092.549192 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 361.990950 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52069.975071 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52069.975071 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52010.032972 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.788011 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52009.984377 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 362.339018 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 362.339018 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52002.691866 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52002.691866 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52072.983984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52003.663910 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52072.983984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52003.663910 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,92 +498,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57452 # number of writebacks -system.cpu.l2cache.writebacks::total 57452 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57455 # number of writebacks +system.cpu.l2cache.writebacks::total 57455 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10615 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20481 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20482 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2873 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2873 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133179 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133179 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 10615 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143034 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 153657 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143038 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 153661 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 10615 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143034 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 153657 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143038 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 153661 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425912000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394750500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820982500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115023000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115023000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5336288000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5336288000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 424634000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394375000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 819329000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114934000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114934000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5327448000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5327448000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425912000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5731038500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6157270500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 424634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5721823000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6146777000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425912000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5731038500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6157270500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 424634000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5721823000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6146777000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763232500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028072500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856015000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856015000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166685236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166950076000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31792706500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31792706500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198619247500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198884087500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198477942500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198742782500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025935 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025938 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537844 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537775 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537775 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.102795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.102794 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102794 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40123.598681 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40043.670116 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40085.078854 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40035.851027 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40035.851027 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.441941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40069.441941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.203015 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.521452 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.392344 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40004.872955 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40004.872955 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40002.162503 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40002.162503 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1359273920420 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1359273920420 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1246144703911 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1246144703911 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |