diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/quick/fs | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/quick/fs')
14 files changed, 5856 insertions, 5831 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 3ede85d66..7dde96a20 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -25,7 +25,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:134217727 +mem_ranges=0:134217727:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false @@ -60,7 +60,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=8796093022208:18446744073709551615 +ranges=8796093022208:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -115,7 +115,7 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -166,7 +166,7 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -268,7 +268,7 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -319,7 +319,7 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -467,7 +467,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=Cache children=tags -addr_ranges=0:134217727 +addr_ranges=0:134217727:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -513,7 +513,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -611,27 +611,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -651,6 +651,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -660,7 +661,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -682,9 +683,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 5e8bf0780..d5fb9a1a9 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -3,14 +3,14 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:25 -gem5 executing on e108600-lin, pid 39587 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28056 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 722572000 -Exiting @ tick 1963612574000 because m5_exit instruction encountered +info: Launching CPU 1 @ 752919000 +Exiting @ tick 1966741627000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a66428f0b..de3485335 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962627 # Number of seconds simulated -sim_ticks 1962626573500 # Number of ticks simulated -final_tick 1962626573500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.966742 # Number of seconds simulated +sim_ticks 1966741627000 # Number of ticks simulated +final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 944250 # Simulator instruction rate (inst/s) -host_op_rate 944250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30421290331 # Simulator tick rate (ticks/s) -host_mem_usage 338248 # Number of bytes of host memory used -host_seconds 64.52 # Real time elapsed on the host -sim_insts 60918166 # Number of instructions simulated -sim_ops 60918166 # Number of ops (including micro ops) simulated +host_inst_rate 801704 # Simulator instruction rate (inst/s) +host_op_rate 801704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25865455419 # Simulator tick rate (ticks/s) +host_mem_usage 334360 # Number of bytes of host memory used +host_seconds 76.04 # Real time elapsed on the host +sim_insts 60959478 # Number of instructions simulated +sim_ops 60959478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 831680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24730496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 27968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 420288 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 796480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24829632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 62464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 430848 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26011392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 27968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7700672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7700672 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 437 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6567 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26120384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 796480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 62464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 858944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7775296 # Number of bytes written to this memory +system.physmem.bytes_written::total 7775296 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 976 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6732 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406428 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120323 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12600714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 214146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13253358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423759 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 438009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3923656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3923656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3923656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12600714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 214146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17177014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406428 # Number of read requests accepted -system.physmem.writeReqs 120323 # Number of write requests accepted -system.physmem.readBursts 406428 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120323 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26003904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 7699456 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26011392 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7700672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 408131 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121489 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121489 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 404974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12624755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 31760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 219067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13281045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 404974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 31760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 436735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3953390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3953390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3953390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 404974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12624755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 31760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 219067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17234435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408131 # Number of read requests accepted +system.physmem.writeReqs 121489 # Number of write requests accepted +system.physmem.readBursts 408131 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121489 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26113216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue +system.physmem.bytesWritten 7773568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26120384 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7775296 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25480 # Per bank write bursts -system.physmem.perBankRdBursts::1 25719 # Per bank write bursts -system.physmem.perBankRdBursts::2 25425 # Per bank write bursts -system.physmem.perBankRdBursts::3 24952 # Per bank write bursts -system.physmem.perBankRdBursts::4 24963 # Per bank write bursts -system.physmem.perBankRdBursts::5 25448 # Per bank write bursts -system.physmem.perBankRdBursts::6 25036 # Per bank write bursts -system.physmem.perBankRdBursts::7 25388 # Per bank write bursts -system.physmem.perBankRdBursts::8 25382 # Per bank write bursts -system.physmem.perBankRdBursts::9 25021 # Per bank write bursts -system.physmem.perBankRdBursts::10 25321 # Per bank write bursts -system.physmem.perBankRdBursts::11 25245 # Per bank write bursts -system.physmem.perBankRdBursts::12 25883 # Per bank write bursts -system.physmem.perBankRdBursts::13 25960 # Per bank write bursts -system.physmem.perBankRdBursts::14 25500 # Per bank write bursts -system.physmem.perBankRdBursts::15 25588 # Per bank write bursts -system.physmem.perBankWrBursts::0 8093 # Per bank write bursts -system.physmem.perBankWrBursts::1 7861 # Per bank write bursts -system.physmem.perBankWrBursts::2 7317 # Per bank write bursts -system.physmem.perBankWrBursts::3 6760 # Per bank write bursts -system.physmem.perBankWrBursts::4 6801 # Per bank write bursts -system.physmem.perBankWrBursts::5 7296 # Per bank write bursts -system.physmem.perBankWrBursts::6 7054 # Per bank write bursts -system.physmem.perBankWrBursts::7 7130 # Per bank write bursts -system.physmem.perBankWrBursts::8 7229 # Per bank write bursts -system.physmem.perBankWrBursts::9 7212 # Per bank write bursts -system.physmem.perBankWrBursts::10 7633 # Per bank write bursts -system.physmem.perBankWrBursts::11 7389 # Per bank write bursts -system.physmem.perBankWrBursts::12 8081 # Per bank write bursts -system.physmem.perBankWrBursts::13 8482 # Per bank write bursts -system.physmem.perBankWrBursts::14 7977 # Per bank write bursts -system.physmem.perBankWrBursts::15 7989 # Per bank write bursts +system.physmem.perBankRdBursts::0 25299 # Per bank write bursts +system.physmem.perBankRdBursts::1 25599 # Per bank write bursts +system.physmem.perBankRdBursts::2 25910 # Per bank write bursts +system.physmem.perBankRdBursts::3 25657 # Per bank write bursts +system.physmem.perBankRdBursts::4 25586 # Per bank write bursts +system.physmem.perBankRdBursts::5 25177 # Per bank write bursts +system.physmem.perBankRdBursts::6 26012 # Per bank write bursts +system.physmem.perBankRdBursts::7 25110 # Per bank write bursts +system.physmem.perBankRdBursts::8 25002 # Per bank write bursts +system.physmem.perBankRdBursts::9 25326 # Per bank write bursts +system.physmem.perBankRdBursts::10 25348 # Per bank write bursts +system.physmem.perBankRdBursts::11 25350 # Per bank write bursts +system.physmem.perBankRdBursts::12 25736 # Per bank write bursts +system.physmem.perBankRdBursts::13 25396 # Per bank write bursts +system.physmem.perBankRdBursts::14 25673 # Per bank write bursts +system.physmem.perBankRdBursts::15 25838 # Per bank write bursts +system.physmem.perBankWrBursts::0 7888 # Per bank write bursts +system.physmem.perBankWrBursts::1 7973 # Per bank write bursts +system.physmem.perBankWrBursts::2 7891 # Per bank write bursts +system.physmem.perBankWrBursts::3 7697 # Per bank write bursts +system.physmem.perBankWrBursts::4 7528 # Per bank write bursts +system.physmem.perBankWrBursts::5 7375 # Per bank write bursts +system.physmem.perBankWrBursts::6 8079 # Per bank write bursts +system.physmem.perBankWrBursts::7 7030 # Per bank write bursts +system.physmem.perBankWrBursts::8 7056 # Per bank write bursts +system.physmem.perBankWrBursts::9 7058 # Per bank write bursts +system.physmem.perBankWrBursts::10 7243 # Per bank write bursts +system.physmem.perBankWrBursts::11 7671 # Per bank write bursts +system.physmem.perBankWrBursts::12 7657 # Per bank write bursts +system.physmem.perBankWrBursts::13 7555 # Per bank write bursts +system.physmem.perBankWrBursts::14 7813 # Per bank write bursts +system.physmem.perBankWrBursts::15 7948 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1962619726500 # Total gap between requests +system.physmem.numWrRetry 71 # Number of times write queue was full causing retry +system.physmem.totGap 1966734334500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406428 # Read request sizes (log2) +system.physmem.readPktSize::6 408131 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120323 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121489 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -159,195 +159,195 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65759 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 512.528475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.841182 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.690018 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15231 23.16% 23.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12147 18.47% 41.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5552 8.44% 50.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3316 5.04% 55.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2308 3.51% 58.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1955 2.97% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1491 2.27% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1296 1.97% 65.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22463 34.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65759 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5364 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.747390 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2879.661653 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5361 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 513.560621 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 309.956643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.656575 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15493 23.48% 23.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12381 18.76% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4640 7.03% 49.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3311 5.02% 54.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3269 4.95% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1542 2.34% 61.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1639 2.48% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1098 1.66% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22611 34.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65984 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5405 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.487327 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2871.274927 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5402 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5364 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5364 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.428039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.999012 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.364771 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4746 88.48% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 15 0.28% 88.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.30% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 23 0.43% 89.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 212 3.95% 93.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 26 0.48% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.24% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.04% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.15% 94.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.15% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 13 0.24% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.04% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.04% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 18 0.34% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.07% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 23 0.43% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 170 3.17% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.06% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 8 0.15% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.06% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.07% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 12 0.22% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5364 # Writes before turning the bus around for reads -system.physmem.totQLat 2137214000 # Total ticks spent queuing -system.physmem.totMemAccLat 9755545250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2031555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5260.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5405 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5405 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.472155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.786030 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.242091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4888 90.43% 90.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 28 0.52% 90.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 175 3.24% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 6 0.11% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 18 0.33% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 9 0.17% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 25 0.46% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 152 2.81% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 23 0.43% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 6 0.11% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 7 0.13% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 9 0.17% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 4 0.07% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.11% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.06% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5405 # Writes before turning the bus around for reads +system.physmem.totQLat 6252046750 # Total ticks spent queuing +system.physmem.totMemAccLat 13902403000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2040095000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15322.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24010.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34072.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing -system.physmem.readRowHits 364061 # Number of row buffer hits during reads -system.physmem.writeRowHits 96795 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.45 # Row buffer hit rate for writes -system.physmem.avgGap 3725896.54 # Average gap between requests -system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244346760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133324125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578805800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 377861760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128189159280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 66163184910 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119537594750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316224277385 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.644542 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862206979750 # Time in different power states -system.physmem_0.memoryStateTime::REF 65536380000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34882447750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 252791280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 137931750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1590420000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401708160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128189159280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66247264755 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119463832250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316283107475 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.674522 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1862086480750 # Time in different power states -system.physmem_1.memoryStateTime::REF 65536380000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35002933000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing +system.physmem.readRowHits 365911 # Number of row buffer hits during reads +system.physmem.writeRowHits 97586 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes +system.physmem.avgGap 3713482.00 # Average gap between requests +system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 236241180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125565165 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5643624480.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5139412980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 370844640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13440056220 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6440902560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 458973488295 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 492152011950 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.237247 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1954499558250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 615960500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2400520000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1908253811750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16773151500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9224451750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 29473731500 # Time in different power states +system.physmem_1.actEnergy 234884580 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124844115 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1454196660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313205220 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5773313520.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5158429890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 364374240 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13818451860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6703686720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 458612092095 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 492560034510 # Total energy per rank (pJ) +system.physmem_1.averagePower 250.444709 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1954406570250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 598675750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2455572000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1906713566750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17457468500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9212976500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 30303367500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7493005 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 7479115 # DTB read hits +system.cpu0.dtb.read_misses 7764 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5064687 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses -system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12557692 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses -system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3501057 # ITB hits -system.cpu0.itb.fetch_misses 3871 # ITB misses +system.cpu0.dtb.read_accesses 524068 # DTB read accesses +system.cpu0.dtb.write_hits 5079820 # DTB write hits +system.cpu0.dtb.write_misses 909 # DTB write misses +system.cpu0.dtb.write_acv 133 # DTB write access violations +system.cpu0.dtb.write_accesses 202594 # DTB write accesses +system.cpu0.dtb.data_hits 12558935 # DTB hits +system.cpu0.dtb.data_misses 8673 # DTB misses +system.cpu0.dtb.data_acv 343 # DTB access violations +system.cpu0.dtb.data_accesses 726662 # DTB accesses +system.cpu0.itb.fetch_hits 3638634 # ITB hits +system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3504928 # ITB accesses +system.cpu0.itb.fetch_accesses 3642618 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -360,427 +360,430 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13585 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 272297667.010158 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 432721655.998866 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 104000 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 272289101.854578 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 432882462.064242 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 249000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 112908521500 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849718052000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3923838819 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 116809469000 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 3933483254 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164897 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56819 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.40% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 423 0.30% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82035 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141381 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56285 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 423 0.37% 51.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55862 48.71% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114674 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900334186500 96.86% 96.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93688500 0.00% 96.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 789357000 0.04% 96.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314729500 0.02% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60387418000 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919379500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 163850 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56218 40.17% 40.17% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139952 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55706 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55273 48.69% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113518 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1903167810000 96.77% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93266000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 790441500 0.04% 96.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 321171500 0.02% 96.83% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 62368212000 3.17% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1966740901000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990893 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680953 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811099 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680744 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811121 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134520 89.85% 92.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149713 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3064 2.07% 2.43% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed +system.cpu0.kern.callpal::swpipl 133000 89.79% 92.25% # number of callpals executed +system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed +system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 148125 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::kernel 1368 +system.cpu0.kern.mode_good::user 1369 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186320 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195764 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314114 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958165685500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3548030000 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327510 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1962821824500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3919074500 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3064 # number of times the context was actually changed -system.cpu0.committedInsts 47738229 # Number of instructions committed -system.cpu0.committedOps 47738229 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44272305 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses -system.cpu0.num_func_calls 1201649 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5610320 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44272305 # number of integer instructions -system.cpu0.num_fp_insts 210363 # number of float instructions -system.cpu0.num_int_register_reads 60851829 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32993694 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written -system.cpu0.num_mem_refs 12597866 # number of memory refs -system.cpu0.num_load_insts 7520141 # Number of load instructions -system.cpu0.num_store_insts 5077725 # Number of store instructions -system.cpu0.num_idle_cycles 3698103141.291685 # Number of idle cycles -system.cpu0.num_busy_cycles 225735677.708315 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057529 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942471 # Percentage of idle cycles -system.cpu0.Branches 7202811 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2726604 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31424940 65.82% 71.53% # Class of executed instruction -system.cpu0.op_class::IntMult 52727 0.11% 71.64% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25705 0.05% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::MemRead 7695505 16.12% 87.81% # Class of executed instruction -system.cpu0.op_class::MemWrite 5083820 10.65% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 735872 1.54% 100.00% # Class of executed instruction +system.cpu0.kern.swap_context 3065 # number of times the context was actually changed +system.cpu0.committedInsts 47690735 # Number of instructions committed +system.cpu0.committedOps 47690735 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44243506 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210072 # Number of float alu accesses +system.cpu0.num_func_calls 1190980 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5607273 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44243506 # number of integer instructions +system.cpu0.num_fp_insts 210072 # number of float instructions +system.cpu0.num_int_register_reads 60857324 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32955789 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102653 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104432 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599733 # number of memory refs +system.cpu0.num_load_insts 7506744 # Number of load instructions +system.cpu0.num_store_insts 5092989 # Number of store instructions +system.cpu0.num_idle_cycles 3699864315.998118 # Number of idle cycles +system.cpu0.num_busy_cycles 233618938.001881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059392 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940608 # Percentage of idle cycles +system.cpu0.Branches 7182999 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2715471 5.69% 5.69% # Class of executed instruction +system.cpu0.op_class::IntAlu 31387897 65.80% 71.50% # Class of executed instruction +system.cpu0.op_class::IntMult 52053 0.11% 71.61% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::MemRead 7680863 16.10% 87.77% # Class of executed instruction +system.cpu0.op_class::MemWrite 5099104 10.69% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47746829 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1179926 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.222517 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11367443 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1180345 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.630611 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.222517 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986763 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986763 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 394 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 25 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51462845 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51462845 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6409921 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6409921 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4656712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4656712 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143926 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 143926 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147979 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 147979 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11066633 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11066633 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11066633 # number of overall hits -system.cpu0.dcache.overall_hits::total 11066633 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 937871 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 937871 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251485 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251485 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13660 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13660 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1189356 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1189356 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1189356 # number of overall misses -system.cpu0.dcache.overall_misses::total 1189356 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29160615500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 29160615500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10889573000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10889573000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150754500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150754500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 30482000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 30482000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 40050188500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 40050188500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 40050188500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 40050188500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7347792 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7347792 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4908197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4908197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157586 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157586 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153409 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153409 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12255989 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12255989 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12255989 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12255989 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127640 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127640 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051238 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051238 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086683 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086683 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035396 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035396 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097043 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097043 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097043 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097043 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.352253 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.352253 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43301.083564 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43301.083564 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11036.200586 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11036.200586 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5613.627993 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5613.627993 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33673.844080 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33673.844080 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33673.844080 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33673.844080 # average overall miss latency +system.cpu0.op_class::total 47699751 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1183172 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.236482 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11369674 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1183684 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.605329 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.236482 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986790 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986790 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51472726 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51472726 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6400739 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6400739 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4669408 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4669408 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146309 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146309 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11070147 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11070147 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11070147 # number of overall hits +system.cpu0.dcache.overall_hits::total 11070147 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938380 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938380 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 255338 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 255338 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13584 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13584 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1193718 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1193718 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1193718 # number of overall misses +system.cpu0.dcache.overall_misses::total 1193718 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31213946000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 31213946000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12660198000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12660198000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149666500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 149666500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31954500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 31954500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 43874144000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 43874144000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 43874144000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 43874144000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339119 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7339119 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4924746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152578 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 152578 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152037 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 152037 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12263865 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12263865 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12263865 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12263865 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127860 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127860 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051848 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051848 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097336 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097336 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097336 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097336 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.648743 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.648743 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 679177 # number of writebacks -system.cpu0.dcache.writebacks::total 679177 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937871 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 937871 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251485 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251485 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13660 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13660 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189356 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1189356 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189356 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1189356 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28222744500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28222744500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10638088000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10638088000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137094500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137094500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25052000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25052000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38860832500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38860832500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38860832500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38860832500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578478000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578478000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578478000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578478000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051238 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051238 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086683 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086683 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035396 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035396 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097043 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097043 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097043 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097043 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.352253 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.352253 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42301.083564 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42301.083564 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10036.200586 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10036.200586 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4613.627993 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4613.627993 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222008.157525 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222008.157525 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87952.192567 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87952.192567 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 698827 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.151884 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47047389 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 699339 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.274082 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42438027500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.151884 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992484 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992484 # Average percentage of cache occupancy +system.cpu0.dcache.writebacks::writebacks 681271 # number of writebacks +system.cpu0.dcache.writebacks::total 681271 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938380 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938380 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255338 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 255338 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1193718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193718 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1193718 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30275566000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30275566000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12404860000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12404860000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136082500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136082500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26226500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26226500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42680426000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 42680426000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42680426000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 42680426000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572135500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572135500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572135500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572135500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051848 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051848 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097336 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097336 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.648743 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.648743 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 692001 # number of replacements +system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47007113 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 692513 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.879033 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 44813245500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 349 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48446269 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48446269 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 47047389 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47047389 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47047389 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47047389 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47047389 # number of overall hits -system.cpu0.icache.overall_hits::total 47047389 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 699440 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 699440 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 699440 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 699440 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 699440 # number of overall misses -system.cpu0.icache.overall_misses::total 699440 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10201863500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10201863500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10201863500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10201863500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10201863500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10201863500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47746829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47746829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47746829 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47746829 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47746829 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47746829 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014649 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014649 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014649 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014649 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014649 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014649 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14585.759322 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14585.759322 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14585.759322 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14585.759322 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14585.759322 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14585.759322 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48392391 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48392391 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 47007113 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47007113 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47007113 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47007113 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47007113 # number of overall hits +system.cpu0.icache.overall_hits::total 47007113 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 692639 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 692639 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 692639 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 692639 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 692639 # number of overall misses +system.cpu0.icache.overall_misses::total 692639 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10340404000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10340404000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10340404000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10340404000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10340404000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10340404000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47699752 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47699752 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47699752 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47699752 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47699752 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47699752 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14928.994758 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14928.994758 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 698827 # number of writebacks -system.cpu0.icache.writebacks::total 698827 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699440 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 699440 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 699440 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 699440 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 699440 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 699440 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9502423500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9502423500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9502423500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9502423500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9502423500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9502423500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014649 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014649 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014649 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13585.759322 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13585.759322 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13585.759322 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 692001 # number of writebacks +system.cpu0.icache.writebacks::total 692001 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692639 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 692639 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 692639 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 692639 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 692639 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 692639 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9647765000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9647765000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9647765000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9647765000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9647765000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9647765000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2422670 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_hits 2442522 # DTB read hits +system.cpu1.dtb.read_misses 2621 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1760134 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses -system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4182804 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses -system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1965215 # ITB hits -system.cpu1.itb.fetch_misses 1216 # ITB misses +system.cpu1.dtb.read_accesses 205338 # DTB read accesses +system.cpu1.dtb.write_hits 1749235 # DTB write hits +system.cpu1.dtb.write_misses 236 # DTB write misses +system.cpu1.dtb.write_acv 24 # DTB write access violations +system.cpu1.dtb.write_accesses 89740 # DTB write accesses +system.cpu1.dtb.data_hits 4191757 # DTB hits +system.cpu1.dtb.data_misses 2857 # DTB misses +system.cpu1.dtb.data_acv 24 # DTB access violations +system.cpu1.dtb.data_accesses 295078 # DTB accesses +system.cpu1.itb.fetch_hits 1826928 # ITB hits +system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1966431 # ITB accesses +system.cpu1.itb.fetch_accesses 1827992 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -793,389 +796,387 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5486 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 706502118.118848 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 410575500.110236 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2743 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 98500 # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 692202308.556150 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 417084374.205506 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 82000 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 24691263500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1937935310000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3925253147 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 25114151500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 3931646339 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2743 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78622 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26563 38.35% 38.35% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40238 58.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69272 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25720 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25216 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53407 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909399868000 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 730527500 0.04% 97.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 354535500 0.02% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 52140917500 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962625848500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968264 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 79700 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27196 38.42% 38.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41097 58.06% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 70787 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26331 48.20% 48.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25806 47.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 54631 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909855366000 97.15% 97.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 731068500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 371926000 0.02% 97.21% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 54864779000 2.79% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1965823139500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968194 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626671 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.770975 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.627929 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771766 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 423 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63023 88.06% 91.46% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3777 5.28% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed +system.cpu1.kern.callpal::swpipl 64567 88.14% 91.50% # number of callpals executed +system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed +system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71571 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2066 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2880 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 892 -system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 428 -system.cpu1.kern.mode_switch_good::kernel 0.431752 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73259 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 816 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 449 +system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148611 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329760 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17773252500 0.91% 0.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1704242000 0.09% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943148352000 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2002 # number of times the context was actually changed -system.cpu1.committedInsts 13179937 # Number of instructions committed -system.cpu1.committedOps 13179937 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12156604 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses -system.cpu1.num_func_calls 411985 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1307841 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12156604 # number of integer instructions -system.cpu1.num_fp_insts 173446 # number of float instructions -system.cpu1.num_int_register_reads 16739384 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8921370 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written -system.cpu1.num_mem_refs 4206400 # number of memory refs -system.cpu1.num_load_insts 2436997 # Number of load instructions -system.cpu1.num_store_insts 1769403 # Number of store instructions -system.cpu1.num_idle_cycles 3875870619.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49382527.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012581 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987419 # Percentage of idle cycles -system.cpu1.Branches 1874664 # Number of branches fetched -system.cpu1.op_class::No_OpClass 705658 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7796168 59.14% 64.49% # Class of executed instruction -system.cpu1.op_class::IntMult 21633 0.16% 64.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14181 0.11% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.78% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::MemRead 2508903 19.03% 83.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 1770394 13.43% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 364376 2.76% 100.00% # Class of executed instruction +system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 18376717500 0.94% 0.94% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1492465500 0.08% 1.01% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1945081083000 98.99% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2017 # number of times the context was actually changed +system.cpu1.committedInsts 13268743 # Number of instructions committed +system.cpu1.committedOps 13268743 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12224543 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses +system.cpu1.num_func_calls 423393 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1315452 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12224543 # number of integer instructions +system.cpu1.num_fp_insts 175144 # number of float instructions +system.cpu1.num_int_register_reads 16795911 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8988763 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written +system.cpu1.num_mem_refs 4214824 # number of memory refs +system.cpu1.num_load_insts 2456352 # Number of load instructions +system.cpu1.num_store_insts 1758472 # Number of store instructions +system.cpu1.num_idle_cycles 3881441492.340690 # Number of idle cycles +system.cpu1.num_busy_cycles 50204846.659310 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012769 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987231 # Percentage of idle cycles +system.cpu1.Branches 1899015 # Number of branches fetched +system.cpu1.op_class::No_OpClass 719201 5.42% 5.42% # Class of executed instruction +system.cpu1.op_class::IntAlu 7861154 59.23% 64.65% # Class of executed instruction +system.cpu1.op_class::IntMult 22602 0.17% 64.82% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::MemRead 2529811 19.06% 84.00% # Class of executed instruction +system.cpu1.op_class::MemWrite 1759476 13.26% 97.25% # Class of executed instruction +system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13183299 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 166569 # number of replacements -system.cpu1.dcache.tags.tagsinuse 484.920851 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4014072 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 167081 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.024707 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 79208580000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.920851 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947111 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.947111 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16965673 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16965673 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2258295 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2258295 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1642687 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1642687 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48217 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48217 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50804 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50804 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3900982 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3900982 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3900982 # number of overall hits -system.cpu1.dcache.overall_hits::total 3900982 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118473 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118473 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62672 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62672 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8931 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8931 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5870 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5870 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 181145 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 181145 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 181145 # number of overall misses -system.cpu1.dcache.overall_misses::total 181145 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1450679500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1450679500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1216299000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1216299000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81854000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 81854000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 32847500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 32847500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2666978500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2666978500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2666978500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2666978500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2376768 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2376768 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1705359 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1705359 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57148 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57148 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56674 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56674 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4082127 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4082127 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4082127 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4082127 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049846 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049846 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036750 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036750 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156278 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156278 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103575 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103575 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044375 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044375 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044375 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044375 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12244.811054 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12244.811054 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19407.374904 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19407.374904 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9165.155078 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9165.155078 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5595.826235 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5595.826235 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14722.893262 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14722.893262 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14722.893262 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14722.893262 # average overall miss latency +system.cpu1.op_class::total 13271624 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 162095 # number of replacements +system.cpu1.dcache.tags.tagsinuse 484.320037 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4015175 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 162424 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.720331 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 72635663500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320037 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16996897 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16996897 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 2273870 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2273870 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1634166 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1634166 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51918 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 51918 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52084 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 52084 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3908036 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3908036 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3908036 # number of overall hits +system.cpu1.dcache.overall_hits::total 3908036 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118670 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118670 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 58749 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 58749 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9148 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9148 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6116 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6116 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 177419 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 177419 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 177419 # number of overall misses +system.cpu1.dcache.overall_misses::total 177419 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1466187000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1466187000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1296760000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1296760000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84020000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84020000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34172000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 34172000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2762947000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2762947000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2762947000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2762947000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392540 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2392540 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692915 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1692915 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61066 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 61066 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58200 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 58200 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4085455 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4085455 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4085455 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4085455 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049600 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049600 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034703 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034703 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149805 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149805 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105086 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105086 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043427 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043427 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043427 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043427 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9184.521207 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9184.521207 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5587.311969 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5587.311969 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 114559 # number of writebacks -system.cpu1.dcache.writebacks::total 114559 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118473 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118473 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62672 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62672 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8931 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8931 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 181145 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 181145 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 181145 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 181145 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1332206500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1332206500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1153627000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1153627000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72923000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72923000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26977500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26977500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2485833500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2485833500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2485833500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2485833500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049846 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049846 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036750 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036750 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156278 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156278 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103575 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103575 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044375 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044375 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044375 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044375 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11244.811054 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11244.811054 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18407.374904 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18407.374904 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8165.155078 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8165.155078 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4595.826235 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4595.826235 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 316020 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.922081 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12866727 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 316532 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.649056 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960698705500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.922081 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870942 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870942 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13499873 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13499873 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 12866727 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12866727 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12866727 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12866727 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12866727 # number of overall hits -system.cpu1.icache.overall_hits::total 12866727 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316573 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316573 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316573 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316573 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316573 # number of overall misses -system.cpu1.icache.overall_misses::total 316573 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4250508000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4250508000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4250508000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4250508000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4250508000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4250508000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13183300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13183300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13183300 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13183300 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13183300 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13183300 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024013 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024013 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024013 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024013 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024013 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024013 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13426.628297 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13426.628297 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13426.628297 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13426.628297 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13426.628297 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13426.628297 # average overall miss latency +system.cpu1.dcache.writebacks::writebacks 111600 # number of writebacks +system.cpu1.dcache.writebacks::total 111600 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118670 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118670 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58749 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 58749 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9148 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9148 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 177419 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 177419 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 177419 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 177419 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1347517000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1347517000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238011000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1238011000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74872000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74872000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28056000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28056000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2585528000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2585528000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2585528000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2585528000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049600 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049600 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034703 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034703 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149805 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149805 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105086 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105086 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043427 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043427 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8184.521207 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8184.521207 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4587.311969 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4587.311969 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 326538 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.783445 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12944535 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 327049 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.579803 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960887554500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783445 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 13598713 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13598713 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 12944535 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12944535 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12944535 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12944535 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12944535 # number of overall hits +system.cpu1.icache.overall_hits::total 12944535 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 327089 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 327089 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 327089 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 327089 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 327089 # number of overall misses +system.cpu1.icache.overall_misses::total 327089 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4450039000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4450039000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4450039000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4450039000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4450039000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4450039000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271624 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13271624 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13271624 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13271624 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13271624 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13271624 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024646 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024646 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024646 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024646 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024646 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024646 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13604.979073 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13604.979073 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 316020 # number of writebacks -system.cpu1.icache.writebacks::total 316020 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316573 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316573 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316573 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316573 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316573 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316573 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3933935000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933935000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933935000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3933935000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933935000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3933935000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024013 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024013 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024013 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12426.628297 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12426.628297 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12426.628297 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 326538 # number of writebacks +system.cpu1.icache.writebacks::total 326538 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327089 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 327089 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 327089 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 327089 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 327089 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 327089 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4122950000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4122950000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4122950000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4122950000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4122950000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4122950000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024646 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024646 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024646 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1188,13 +1189,13 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7375 # Transaction distribution -system.iobus.trans_dist::ReadResp 7375 # Transaction distribution -system.iobus.trans_dist::WriteReq 55610 # Transaction distribution -system.iobus.trans_dist::WriteResp 55610 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 55675 # Transaction distribution +system.iobus.trans_dist::WriteResp 55675 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1202,12 +1203,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1215,74 +1216,74 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743514 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 14952500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 763000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15838000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6057500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216134056 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216235265 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.568010 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.568421 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756490226000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.568010 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035501 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035501 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1760410342000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.568421 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035526 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035526 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.tags.tag_accesses 375570 # Number of tag accesses +system.iocache.tags.data_accesses 375570 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22088883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22088883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858687173 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4858687173 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4880776056 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4880776056 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4880776056 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4880776056 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4956087382 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4956087382 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4978500265 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4978500265 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4978500265 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4978500265 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1291,38 +1292,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125505.017045 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125505.017045 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116930.284294 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116930.284294 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116966.450729 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116966.450729 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116966.450729 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116966.450729 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 16 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119302.666307 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119302.666307 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13288883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13288883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778678942 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2778678942 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2791967825 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2791967825 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2791967825 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2791967825 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2876027417 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2876027417 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2889540300 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2889540300 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2889540300 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2889540300 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1331,196 +1332,196 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75505.017045 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75505.017045 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.327253 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.327253 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66908.738137 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66908.738137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66908.738137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66908.738137 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 341251 # number of replacements -system.l2c.tags.tagsinuse 65397.203087 # Cycle average of tags in use -system.l2c.tags.total_refs 3991452 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406774 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.812456 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7305719000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 281.092347 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4857.550126 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 59344.826381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 110.880269 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 802.853964 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004289 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074120 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.905530 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012251 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997882 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65523 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6255 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 57986 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999802 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35595123 # Number of tag accesses -system.l2c.tags.data_accesses 35595123 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 793736 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 793736 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 747944 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 747944 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3115 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2258 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5373 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 912 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 927 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1839 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126843 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47590 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 174433 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 686424 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 316124 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1002548 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 663180 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 109254 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 772434 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 686424 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 790023 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 316124 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 156844 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949415 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 686424 # number of overall hits -system.l2c.overall_hits::cpu0.data 790023 # number of overall hits -system.l2c.overall_hits::cpu1.inst 316124 # number of overall hits -system.l2c.overall_hits::cpu1.data 156844 # number of overall hits -system.l2c.overall_hits::total 1949415 # number of overall hits +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 342937 # number of replacements +system.l2c.tags.tagsinuse 65389.954388 # Cycle average of tags in use +system.l2c.tags.total_refs 3989146 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 408458 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.766355 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7750506000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 285.827023 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4791.190703 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 59306.187710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 166.825599 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 839.923352 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073108 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.904941 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002546 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012816 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35591920 # Number of tag accesses +system.l2c.tags.data_accesses 35591920 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 792871 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792871 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173230 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44916.666667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67128.746754 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72597.285782 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67414.036388 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71711.025908 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63242.401431 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 69739.316239 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63247.992806 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64399.203973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72495.510577 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64771.410451 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64399.203973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72495.510577 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64771.410451 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209503.516174 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209561.189054 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82998.272692 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70971.021311 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 851905 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 404237 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 411 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 856503 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 407142 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 292704 # Transaction distribution -system.membus.trans_dist::WriteReq 14058 # Transaction distribution -system.membus.trans_dist::WriteResp 14058 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120323 # Transaction distribution -system.membus.trans_dist::CleanEvict 261806 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11056 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9461 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 7198 # Transaction distribution +system.membus.trans_dist::ReadResp 292654 # Transaction distribution +system.membus.trans_dist::WriteReq 14123 # Transaction distribution +system.membus.trans_dist::WriteResp 14123 # Transaction distribution +system.membus.trans_dist::WritebackDirty 121489 # Transaction distribution +system.membus.trans_dist::CleanEvict 262335 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11693 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9938 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 122183 # Transaction distribution -system.membus.trans_dist::ReadExResp 121347 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285505 # Transaction distribution +system.membus.trans_dist::ReadExReq 123969 # Transaction distribution +system.membus.trans_dist::ReadExResp 123101 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285456 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1174875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1217389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1300828 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31053824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31135706 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1223762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1307205 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31237440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31319834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33793946 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21651 # Total snoops (count) -system.membus.snoopTraffic 27136 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 491014 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001340 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036583 # Request fanout histogram +system.membus.pkt_size::total 33978074 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22774 # Total snoops (count) +system.membus.snoopTraffic 27264 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 493929 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001371 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036997 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 490356 99.87% 99.87% # Request fanout histogram -system.membus.snoop_fanout::1 658 0.13% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 493252 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 491014 # Request fanout histogram -system.membus.reqLayer0.occupancy 40347000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 493929 # Request fanout histogram +system.membus.reqLayer0.occupancy 40493000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314918038 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1323047597 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2173304250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2182313750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 904117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 915117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4781747 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2390985 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 355114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 992 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 932 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102308 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 872539 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1014847 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 815207 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16306 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11300 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27606 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297851 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297851 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1016013 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079098 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 229 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2097686 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605272 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949165 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535742 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7187865 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89487744 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118850496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40485888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17815770 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266639898 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 398766 # Total snoops (count) -system.toL2Bus.snoopTraffic 7394432 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2783305 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.138476 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.345638 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 4789247 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2394847 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 989 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2106871 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 872840 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1018539 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 815364 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17050 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11844 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28894 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297037 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297037 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019728 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1079947 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077258 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523549 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7197758 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88615616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119196292 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41832064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17309590 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266953562 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 403246 # Total snoops (count) +system.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2790110 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.141029 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.348296 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2398113 86.16% 86.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 384964 13.83% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 227 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2396861 85.91% 85.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 393013 14.09% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 235 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2783305 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4217117493 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2790110 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4223757496 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 299383 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 302383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1049361097 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1039141633 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1811830165 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1817975093 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 476124465 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 491872018 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 281628843 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 276251327 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1788,28 +1789,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal index b603b455c..fff26b301 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 38 cycles, load miss latency 162 cycles +
4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index b5a7841a1..7a4d88e30 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -25,7 +25,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:134217727 +mem_ranges=0:134217727:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false @@ -60,7 +60,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=8796093022208:18446744073709551615 +ranges=8796093022208:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -115,7 +115,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -166,7 +166,7 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -226,7 +226,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -389,7 +389,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=Cache children=tags -addr_ranges=0:134217727 +addr_ranges=0:134217727:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -434,7 +434,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -446,7 +446,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -478,29 +478,36 @@ update_data=false warn_access= pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -520,6 +527,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -529,7 +537,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -551,9 +559,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index ef6ffb4a6..1d59c0edc 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:24 -gem5 executing on e108600-lin, pid 39578 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28068 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1941275996000 because m5_exit instruction encountered +Exiting @ tick 1926421414000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 23c45cb03..e8b92466f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922415 # Number of seconds simulated -sim_ticks 1922415409000 # Number of ticks simulated -final_tick 1922415409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.926421 # Number of seconds simulated +sim_ticks 1926421414000 # Number of ticks simulated +final_tick 1926421414000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 933149 # Simulator instruction rate (inst/s) -host_op_rate 933149 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31931169584 # Simulator tick rate (ticks/s) -host_mem_usage 334404 # Number of bytes of host memory used -host_seconds 60.21 # Real time elapsed on the host -sim_insts 56180200 # Number of instructions simulated -sim_ops 56180200 # Number of ops (including micro ops) simulated +host_inst_rate 779030 # Simulator instruction rate (inst/s) +host_op_rate 779030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26705916367 # Simulator tick rate (ticks/s) +host_mem_usage 331544 # Number of bytes of host memory used +host_seconds 72.13 # Real time elapsed on the host +sim_insts 56195014 # Number of instructions simulated +sim_ops 56195014 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 844608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24856576 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25702144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 844608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 844608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7408512 # Number of bytes written to this memory -system.physmem.bytes_written::total 7408512 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13197 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388384 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25702528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 844672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 844672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7408960 # Number of bytes written to this memory +system.physmem.bytes_written::total 7408960 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13198 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388389 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401596 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115758 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115758 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 439347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12929867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13369714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 439347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3853752 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3853752 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3853752 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 439347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12929867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17223466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401596 # Number of read requests accepted -system.physmem.writeReqs 115758 # Number of write requests accepted -system.physmem.readBursts 401596 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115758 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25695616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue -system.physmem.bytesWritten 7407424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25702144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7408512 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 401602 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12903146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13342111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3845971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3845971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3845971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12903146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17188081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401602 # Number of read requests accepted +system.physmem.writeReqs 115765 # Number of write requests accepted +system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115765 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25695552 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7408000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25702528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7408960 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25227 # Per bank write bursts -system.physmem.perBankRdBursts::1 25633 # Per bank write bursts -system.physmem.perBankRdBursts::2 25570 # Per bank write bursts -system.physmem.perBankRdBursts::3 25510 # Per bank write bursts -system.physmem.perBankRdBursts::4 24963 # Per bank write bursts -system.physmem.perBankRdBursts::5 24975 # Per bank write bursts -system.physmem.perBankRdBursts::6 24200 # Per bank write bursts +system.physmem.perBankRdBursts::0 25229 # Per bank write bursts +system.physmem.perBankRdBursts::1 25631 # Per bank write bursts +system.physmem.perBankRdBursts::2 25563 # Per bank write bursts +system.physmem.perBankRdBursts::3 25503 # Per bank write bursts +system.physmem.perBankRdBursts::4 24978 # Per bank write bursts +system.physmem.perBankRdBursts::5 24964 # Per bank write bursts +system.physmem.perBankRdBursts::6 24209 # Per bank write bursts system.physmem.perBankRdBursts::7 24494 # Per bank write bursts -system.physmem.perBankRdBursts::8 25179 # Per bank write bursts -system.physmem.perBankRdBursts::9 24767 # Per bank write bursts -system.physmem.perBankRdBursts::10 25265 # Per bank write bursts -system.physmem.perBankRdBursts::11 24877 # Per bank write bursts -system.physmem.perBankRdBursts::12 24504 # Per bank write bursts -system.physmem.perBankRdBursts::13 25368 # Per bank write bursts +system.physmem.perBankRdBursts::8 25180 # Per bank write bursts +system.physmem.perBankRdBursts::9 24757 # Per bank write bursts +system.physmem.perBankRdBursts::10 25269 # Per bank write bursts +system.physmem.perBankRdBursts::11 24873 # Per bank write bursts +system.physmem.perBankRdBursts::12 24512 # Per bank write bursts +system.physmem.perBankRdBursts::13 25367 # Per bank write bursts system.physmem.perBankRdBursts::14 25615 # Per bank write bursts -system.physmem.perBankRdBursts::15 25347 # Per bank write bursts -system.physmem.perBankWrBursts::0 7623 # Per bank write bursts -system.physmem.perBankWrBursts::1 7643 # Per bank write bursts -system.physmem.perBankWrBursts::2 7871 # Per bank write bursts -system.physmem.perBankWrBursts::3 7543 # Per bank write bursts -system.physmem.perBankWrBursts::4 7113 # Per bank write bursts -system.physmem.perBankWrBursts::5 6990 # Per bank write bursts -system.physmem.perBankWrBursts::6 6317 # Per bank write bursts -system.physmem.perBankWrBursts::7 6320 # Per bank write bursts -system.physmem.perBankWrBursts::8 7316 # Per bank write bursts -system.physmem.perBankWrBursts::9 6519 # Per bank write bursts -system.physmem.perBankWrBursts::10 7114 # Per bank write bursts -system.physmem.perBankWrBursts::11 6905 # Per bank write bursts -system.physmem.perBankWrBursts::12 7090 # Per bank write bursts +system.physmem.perBankRdBursts::15 25349 # Per bank write bursts +system.physmem.perBankWrBursts::0 7626 # Per bank write bursts +system.physmem.perBankWrBursts::1 7640 # Per bank write bursts +system.physmem.perBankWrBursts::2 7866 # Per bank write bursts +system.physmem.perBankWrBursts::3 7539 # Per bank write bursts +system.physmem.perBankWrBursts::4 7128 # Per bank write bursts +system.physmem.perBankWrBursts::5 6982 # Per bank write bursts +system.physmem.perBankWrBursts::6 6324 # Per bank write bursts +system.physmem.perBankWrBursts::7 6321 # Per bank write bursts +system.physmem.perBankWrBursts::8 7317 # Per bank write bursts +system.physmem.perBankWrBursts::9 6511 # Per bank write bursts +system.physmem.perBankWrBursts::10 7117 # Per bank write bursts +system.physmem.perBankWrBursts::11 6900 # Per bank write bursts +system.physmem.perBankWrBursts::12 7101 # Per bank write bursts system.physmem.perBankWrBursts::13 7827 # Per bank write bursts system.physmem.perBankWrBursts::14 7864 # Per bank write bursts -system.physmem.perBankWrBursts::15 7686 # Per bank write bursts +system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1922403535500 # Total gap between requests +system.physmem.numWrRetry 65 # Number of times write queue was full causing retry +system.physmem.totGap 1926409540500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401596 # Read request sizes (log2) +system.physmem.readPktSize::6 401602 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115758 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401480 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115765 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401479 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -149,197 +149,192 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63567 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 520.758255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 315.623593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.134860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14658 23.06% 23.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11541 18.16% 41.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4861 7.65% 48.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3298 5.19% 54.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2285 3.59% 57.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1919 3.02% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1565 2.46% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1066 1.68% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22374 35.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63567 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5112 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.539124 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2951.473216 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5109 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 521.529319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 315.079750 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.298836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14953 23.56% 23.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11433 18.01% 41.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4319 6.80% 48.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3083 4.86% 53.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3219 5.07% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1509 2.38% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1583 2.49% 63.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 998 1.57% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22377 35.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63474 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5046 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5112 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5112 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.641041 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.167929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.759533 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4475 87.54% 87.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 34 0.67% 88.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 11 0.22% 88.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 14 0.27% 88.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 223 4.36% 93.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 16 0.31% 93.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.27% 93.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.23% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 3 0.06% 93.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.14% 94.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.10% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 12 0.23% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.06% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 33 0.65% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.06% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 18 0.35% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 174 3.40% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.08% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.08% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.04% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 2 0.04% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.08% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 9 0.18% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.04% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 5 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5112 # Writes before turning the bus around for reads -system.physmem.totQLat 2082530750 # Total ticks spent queuing -system.physmem.totMemAccLat 9610543250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5186.95 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.952060 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.989890 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4540 89.92% 89.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.65% 90.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 164 3.25% 93.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 7 0.14% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 4 0.08% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 36 0.71% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 139 2.75% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 18 0.36% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 13 0.26% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 12 0.24% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads +system.physmem.totQLat 6110965000 # Total ticks spent queuing +system.physmem.totMemAccLat 13638958750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15220.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23936.95 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33970.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing -system.physmem.readRowHits 359878 # Number of row buffer hits during reads -system.physmem.writeRowHits 93790 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes -system.physmem.avgGap 3715837.77 # Average gap between requests -system.physmem.pageHitRate 87.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 235297440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128386500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564461600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372081600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64706229855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1096686028500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289254932375 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.645215 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1824198256500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34018076000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245269080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133827375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567191600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377920080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65408106195 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1096070355750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289365116960 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.702526 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1823171088500 # Time in different power states -system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35045257750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing +system.physmem.readRowHits 360227 # Number of row buffer hits during reads +system.physmem.writeRowHits 93542 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes +system.physmem.avgGap 3723487.47 # Average gap between requests +system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5038358250 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 366301440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13030830420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6357713760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 449603447400 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 481990669050 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.200016 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1914256960750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 613825000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1869275563500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16556600250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9050884750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28576648500 # Time in different power states +system.physmem_1.actEnergy 232364160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123504480 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5157840510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 361297920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13647845730 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6595007040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 449082638955 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 482651277075 # Total energy per rank (pJ) +system.physmem_1.averagePower 250.542936 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1914153639500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 598128250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1867054823500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17174624250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9236704750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 29929623250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064160 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9066536 # DTB read hits +system.cpu.dtb.read_misses 10331 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6356116 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728865 # DTB read accesses +system.cpu.dtb.write_hits 6357492 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15420276 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15424028 # DTB hits +system.cpu.dtb.data_misses 11474 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973965 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020797 # DTB accesses +system.cpu.itb.fetch_hits 4975201 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978962 # ITB accesses +system.cpu.itb.fetch_accesses 4980211 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -352,43 +347,43 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12754 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6377 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281224726.046887 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439034613.415905 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12758 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281128919.188117 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439406492.836173 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6376 99.98% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6377 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 129045330999 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1793370078001 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3844830818 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 133100038499 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321375501 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3852842828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211971 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212049 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74911 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106221 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1934 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106246 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183222 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73544 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857710123500 96.63% 96.63% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 93945500 0.00% 96.64% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 769790000 0.04% 96.68% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 63840816000 3.32% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1922414675000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1859428695000 96.52% 96.52% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 772442000 0.04% 96.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 66125040000 3.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1926420680000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692255 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814088 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692205 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814056 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,58 +419,58 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175962 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175997 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5159 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192906 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.callpal::total 192947 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46528757000 2.42% 2.42% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5244548000 0.27% 2.69% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1870641368000 97.31% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.committedInsts 56180200 # Number of instructions committed -system.cpu.committedOps 56180200 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52052716 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483318 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468478 # number of instructions that are conditional controls -system.cpu.num_int_insts 52052716 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71320481 # number of times the integer registers were read -system.cpu.num_int_register_writes 38519316 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15472847 # number of memory refs -system.cpu.num_load_insts 9100978 # Number of load instructions -system.cpu.num_store_insts 6371869 # Number of store instructions -system.cpu.num_idle_cycles 3586740156.000134 # Number of idle cycles -system.cpu.num_busy_cycles 258090661.999866 # Number of busy cycles -system.cpu.not_idle_fraction 0.067127 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.932873 # Percentage of idle cycles -system.cpu.Branches 8422318 # Number of branches fetched -system.cpu.op_class::No_OpClass 3200272 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36230015 64.48% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 60990 0.11% 70.28% # Class of executed instruction +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 47043056000 2.44% 2.44% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5370301500 0.28% 2.72% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1874007320500 97.28% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.committedInsts 56195014 # Number of instructions committed +system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52066552 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1483758 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469897 # number of instructions that are conditional controls +system.cpu.num_int_insts 52066552 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71340789 # number of times the integer registers were read +system.cpu.num_int_register_writes 38530081 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15476659 # number of memory refs +system.cpu.num_load_insts 9103400 # Number of load instructions +system.cpu.num_store_insts 6373259 # Number of store instructions +system.cpu.num_idle_cycles 3586642751.000138 # Number of idle cycles +system.cpu.num_busy_cycles 266200076.999862 # Number of busy cycles +system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.930908 # Percentage of idle cycles +system.cpu.Branches 8424278 # Number of branches fetched +system.cpu.op_class::No_OpClass 3201027 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36239709 64.48% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61024 0.11% 70.28% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction @@ -501,482 +496,482 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9328048 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6377943 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953034 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9330523 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6379338 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56192019 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1390892 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.977567 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14047886 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391404 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.096195 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.977567 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy +system.cpu.op_class::total 56206855 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1390811 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14051752 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391323 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099561 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999954 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63148569 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63148569 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7813455 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7813455 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852226 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852226 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182968 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182968 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199220 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199220 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13665681 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13665681 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13665681 # number of overall hits -system.cpu.dcache.overall_hits::total 13665681 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069828 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069828 # number of ReadReq misses +system.cpu.dcache.tags.tag_accesses 63163628 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63163628 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7815905 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815905 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853570 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853570 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183002 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183002 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15039828 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15039828 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120432 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120432 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049430 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049430 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086270 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086270 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091367 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091367 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091367 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091367 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.793843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.793843 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38655.800328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38655.800328 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13332.850941 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13332.850941 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31106.295760 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31106.295760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31106.295760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31106.295760 # average overall miss latency +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17279 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17279 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374062 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374062 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374062 # number of overall misses +system.cpu.dcache.overall_misses::total 1374062 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050586500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33050586500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442150000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13442150000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232520000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232520000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46492736500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46492736500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46492736500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46492736500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200281 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200281 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199258 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199258 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15043537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049419 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049419 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086274 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086274 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.819370 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.819370 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.247934 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.247934 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.797268 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.797268 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33835.981564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33835.981564 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 835265 # number of writebacks -system.cpu.dcache.writebacks::total 835265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069828 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069828 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 835205 # number of writebacks +system.cpu.dcache.writebacks::total 835205 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069743 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069743 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304319 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 304319 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17275 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17275 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374147 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41370476000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41370476000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533911000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533911000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533911000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533911000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120432 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120432 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049430 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049430 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086270 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086270 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091367 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091367 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091367 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091367 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27958.793843 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27958.793843 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37655.800328 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37655.800328 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12332.850941 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12332.850941 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.578644 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.578644 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92515.741858 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92515.741858 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 928034 # number of replacements -system.cpu.icache.tags.tagsinuse 508.064469 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55263315 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928545 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.516033 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42160205500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.064469 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992313 # 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number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13023819500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13023819500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13023819500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56192020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56192020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56192020 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56192020 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56192020 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56192020 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016527 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016527 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016527 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016527 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016527 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016527 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14023.634523 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14023.634523 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14023.634523 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14023.634523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14023.634523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14023.634523 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57136210 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14321.430800 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14321.430800 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 928034 # number of writebacks -system.cpu.icache.writebacks::total 928034 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928705 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928705 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928705 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928705 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928705 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928705 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095114500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12095114500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095114500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12095114500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095114500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12095114500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016527 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016527 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016527 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13023.634523 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13023.634523 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13023.634523 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13023.634523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13023.634523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13023.634523 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 336391 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65395.484463 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4235202 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401913 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.537609 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 7260348000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 235.775942 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4738.507265 # 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number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 74246 # number of writebacks -system.cpu.l2cache.writebacks::total 74246 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74253 # number of writebacks +system.cpu.l2cache.writebacks::total 74253 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116811 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116811 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13197 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13197 # 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number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13198 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271974 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271974 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13198 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401989 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13198 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401989 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7862462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7862462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 944176500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 944176500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17200833000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17200833000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 944176500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25063295500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26007472000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 944176500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25063295500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26007472000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447255500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447255500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447255500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447255500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540870500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540870500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221558000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221558000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273752000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273752000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814622500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30036180500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221558000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814622500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30036180500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383865 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383865 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014210 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173262 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173262 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250201 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250201 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67309.264538 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67309.264538 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71544.782905 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71544.782905 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63244.169501 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63244.169501 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208839.177489 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208839.177489 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87289.234017 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87289.234017 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4639053 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319092 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81673.647671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81673.647671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92556.296409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92556.296409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70866.156324 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70866.156324 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4640189 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319660 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1516 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 909511 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 817772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023463 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 909458 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928683 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 817750 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 928705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087182 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2785424 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4207053 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6992477 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118830016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142561492 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261391508 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 336947 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4763072 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2673477 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000954 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.030869 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787371 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206814 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6994185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142552484 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261465572 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 336953 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2674053 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030932 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2670927 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2550 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2671492 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2561 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2673477 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4095940500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2674053 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4097099500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1393057500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394031000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098871000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098750500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -990,12 +985,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 51202 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51204 # Transaction distribution +system.iobus.trans_dist::WriteResp 51204 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5160 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1004,11 +999,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20640 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1017,13 +1012,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44580 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5337500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5344500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1031,36 +1026,36 @@ system.iobus.reqLayer6.occupancy 10000 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15814000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15813000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 82000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216133054 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216215769 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342865 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.340614 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756469369000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342865 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083929 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083929 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.340614 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083788 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083788 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1069,14 +1064,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21758883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21758883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4857806171 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4857806171 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4879565054 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4879565054 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4879565054 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4879565054 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937126886 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4937126886 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4958975769 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4958975769 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4958975769 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4958975769 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1093,19 +1088,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125773.890173 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125773.890173 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116909.081897 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116909.081897 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116945.837124 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116945.837124 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118818.032489 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118818.032489 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118849.029814 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118849.029814 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 175 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1117,14 +1112,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13108883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13108883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2777800981 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2777800981 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2790909864 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2790909864 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2790909864 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2790909864 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857073994 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2857073994 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2870272877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2870272877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2870272877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2870272877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1133,71 +1128,71 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75773.890173 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75773.890173 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66851.198041 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66851.198041 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 821076 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 378187 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68759.000626 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68759.000626 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 378246 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 292275 # Transaction distribution -system.membus.trans_dist::WriteReq 9650 # Transaction distribution -system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115758 # Transaction distribution -system.membus.trans_dist::CleanEvict 261593 # Transaction distribution +system.membus.trans_dist::WriteReq 9652 # Transaction distribution +system.membus.trans_dist::WriteResp 9652 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115765 # Transaction distribution +system.membus.trans_dist::CleanEvict 261592 # Transaction distribution system.membus.trans_dist::UpgradeReq 136 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116680 # Transaction distribution -system.membus.trans_dist::ReadExResp 116680 # Transaction distribution +system.membus.trans_dist::ReadExReq 116686 # Transaction distribution +system.membus.trans_dist::ReadExResp 116686 # Transaction distribution system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139235 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1255820 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30452928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30497492 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1255842 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30453760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33155220 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 460293 # Request fanout histogram +system.membus.snoop_fanout::samples 460301 # Request fanout histogram system.membus.snoop_fanout::mean 0.001416 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037610 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037609 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 459641 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::0 459649 99.86% 99.86% # Request fanout histogram system.membus.snoop_fanout::1 652 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460293 # Request fanout histogram -system.membus.reqLayer0.occupancy 30118500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 460301 # Request fanout histogram +system.membus.reqLayer0.occupancy 30124000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1286935040 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287045337 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2142767250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2142987750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1229,28 +1224,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal index 9603a7507..d82c05314 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 38 cycles, load miss latency 263 cycles +
4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 942d8ed5e..d7e6fcfdf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -153,7 +153,7 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -250,7 +250,7 @@ port=system.cpu0.toL2Bus.slave[3] [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -382,7 +382,7 @@ port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -531,7 +531,7 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -628,7 +628,7 @@ port=system.cpu1.toL2Bus.slave[3] [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,7 +760,7 @@ port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -907,7 +907,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -953,7 +953,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1051,27 +1051,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1091,6 +1091,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1100,7 +1101,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1122,9 +1123,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1477,7 +1478,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1794,6 +1795,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1801,7 +1803,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2032,6 +2034,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2039,7 +2042,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 8023e7aa6..c41a1ac7e 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12233 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:54:49 +gem5 executing on e108600-lin, pid 17501 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2869796829000 because m5_exit instruction encountered +Exiting @ tick 2870822663000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index dc9310742..bd324667f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,163 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.870001 # Number of seconds simulated -sim_ticks 2870000710000 # Number of ticks simulated -final_tick 2870000710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.870823 # Number of seconds simulated +sim_ticks 2870822663000 # Number of ticks simulated +final_tick 2870822663000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 371570 # Simulator instruction rate (inst/s) -host_op_rate 449436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8101953096 # Simulator tick rate (ticks/s) -host_mem_usage 621024 # Number of bytes of host memory used -host_seconds 354.24 # Real time elapsed on the host -sim_insts 131623434 # Number of instructions simulated -sim_ops 159206188 # Number of ops (including micro ops) simulated +host_inst_rate 442891 # Simulator instruction rate (inst/s) +host_op_rate 535691 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9664154143 # Simulator tick rate (ticks/s) +host_mem_usage 616988 # Number of bytes of host memory used +host_seconds 297.06 # Real time elapsed on the host +sim_insts 131564747 # Number of instructions simulated +sim_ops 159131669 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1182180 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1312420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8596224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150484 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 578772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 396096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1180196 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1289828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8538816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 149012 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 568660 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 388160 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12217776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1182180 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150484 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1332664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8789056 # Number of bytes written to this memory +system.physmem.bytes_read::total 12116336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1180196 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 149012 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1329208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8714368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8806620 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8731932 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26925 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134316 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2506 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6189 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2483 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8906 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6065 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200051 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 137329 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198466 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 136162 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141720 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 140553 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 201 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 411909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 457289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2995199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 201663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 138013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 411100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 449289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2974345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 135209 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4257064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 411909 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52433 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464343 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3062388 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4220510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 411100 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 463006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3035495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3068508 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3062388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3041613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3035495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 201 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 411909 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 463395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2995199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 201677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 138013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 411100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 455393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2974345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 198097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 135209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7325572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200051 # Number of read requests accepted -system.physmem.writeReqs 141720 # Number of write requests accepted -system.physmem.readBursts 200051 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141720 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12793920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 8819520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12217776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8806620 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 7262123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198466 # Number of read requests accepted +system.physmem.writeReqs 140553 # Number of write requests accepted +system.physmem.readBursts 198466 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 140553 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12692032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue +system.physmem.bytesWritten 8744000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12116336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8731932 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11709 # Per bank write bursts -system.physmem.perBankRdBursts::1 12160 # Per bank write bursts -system.physmem.perBankRdBursts::2 12038 # Per bank write bursts -system.physmem.perBankRdBursts::3 12178 # Per bank write bursts -system.physmem.perBankRdBursts::4 20671 # Per bank write bursts -system.physmem.perBankRdBursts::5 12806 # Per bank write bursts -system.physmem.perBankRdBursts::6 12086 # Per bank write bursts -system.physmem.perBankRdBursts::7 12477 # Per bank write bursts -system.physmem.perBankRdBursts::8 12638 # Per bank write bursts -system.physmem.perBankRdBursts::9 12504 # Per bank write bursts -system.physmem.perBankRdBursts::10 11795 # Per bank write bursts -system.physmem.perBankRdBursts::11 11324 # Per bank write bursts -system.physmem.perBankRdBursts::12 11594 # Per bank write bursts -system.physmem.perBankRdBursts::13 11843 # Per bank write bursts -system.physmem.perBankRdBursts::14 11003 # Per bank write bursts -system.physmem.perBankRdBursts::15 11079 # Per bank write bursts -system.physmem.perBankWrBursts::0 8559 # Per bank write bursts -system.physmem.perBankWrBursts::1 9022 # Per bank write bursts -system.physmem.perBankWrBursts::2 9017 # Per bank write bursts -system.physmem.perBankWrBursts::3 8844 # Per bank write bursts -system.physmem.perBankWrBursts::4 8437 # Per bank write bursts -system.physmem.perBankWrBursts::5 9230 # Per bank write bursts -system.physmem.perBankWrBursts::6 8825 # Per bank write bursts -system.physmem.perBankWrBursts::7 8866 # Per bank write bursts -system.physmem.perBankWrBursts::8 9056 # Per bank write bursts -system.physmem.perBankWrBursts::9 8974 # Per bank write bursts -system.physmem.perBankWrBursts::10 8482 # Per bank write bursts -system.physmem.perBankWrBursts::11 8329 # Per bank write bursts -system.physmem.perBankWrBursts::12 8472 # Per bank write bursts -system.physmem.perBankWrBursts::13 8225 # Per bank write bursts -system.physmem.perBankWrBursts::14 7833 # Per bank write bursts -system.physmem.perBankWrBursts::15 7634 # Per bank write bursts +system.physmem.perBankRdBursts::0 11821 # Per bank write bursts +system.physmem.perBankRdBursts::1 11810 # Per bank write bursts +system.physmem.perBankRdBursts::2 12062 # Per bank write bursts +system.physmem.perBankRdBursts::3 12027 # Per bank write bursts +system.physmem.perBankRdBursts::4 20473 # Per bank write bursts +system.physmem.perBankRdBursts::5 12098 # Per bank write bursts +system.physmem.perBankRdBursts::6 12277 # Per bank write bursts +system.physmem.perBankRdBursts::7 12432 # Per bank write bursts +system.physmem.perBankRdBursts::8 12179 # Per bank write bursts +system.physmem.perBankRdBursts::9 12459 # Per bank write bursts +system.physmem.perBankRdBursts::10 11810 # Per bank write bursts +system.physmem.perBankRdBursts::11 11367 # Per bank write bursts +system.physmem.perBankRdBursts::12 11535 # Per bank write bursts +system.physmem.perBankRdBursts::13 11583 # Per bank write bursts +system.physmem.perBankRdBursts::14 11073 # Per bank write bursts +system.physmem.perBankRdBursts::15 11307 # Per bank write bursts +system.physmem.perBankWrBursts::0 8516 # Per bank write bursts +system.physmem.perBankWrBursts::1 8730 # Per bank write bursts +system.physmem.perBankWrBursts::2 8955 # Per bank write bursts +system.physmem.perBankWrBursts::3 8735 # Per bank write bursts +system.physmem.perBankWrBursts::4 8248 # Per bank write bursts +system.physmem.perBankWrBursts::5 8655 # Per bank write bursts +system.physmem.perBankWrBursts::6 8964 # Per bank write bursts +system.physmem.perBankWrBursts::7 8852 # Per bank write bursts +system.physmem.perBankWrBursts::8 8742 # Per bank write bursts +system.physmem.perBankWrBursts::9 8980 # Per bank write bursts +system.physmem.perBankWrBursts::10 8644 # Per bank write bursts +system.physmem.perBankWrBursts::11 8478 # Per bank write bursts +system.physmem.perBankWrBursts::12 8438 # Per bank write bursts +system.physmem.perBankWrBursts::13 8004 # Per bank write bursts +system.physmem.perBankWrBursts::14 7925 # Per bank write bursts +system.physmem.perBankWrBursts::15 7759 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 37 # Number of times write queue was full causing retry -system.physmem.totGap 2870000192000 # Total gap between requests +system.physmem.numWrRetry 91 # Number of times write queue was full causing retry +system.physmem.totGap 2870821632000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190291 # Read request sizes (log2) +system.physmem.readPktSize::6 188706 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 137329 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 139673 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136162 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 135157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -185,164 +181,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 85925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.537690 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.363316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 306.826134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42893 49.92% 49.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18336 21.34% 71.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6281 7.31% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3896 4.53% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2533 2.95% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1590 1.85% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1050 1.22% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 985 1.15% 90.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8361 9.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 85925 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.251244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.918265 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6833 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 236 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 84864 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 252.592006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.738576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.804055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42330 49.88% 49.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18020 21.23% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6191 7.30% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3740 4.41% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2680 3.16% 85.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1634 1.93% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 923 1.09% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 980 1.15% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8366 9.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84864 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6753 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.364283 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 566.459907 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6751 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6834 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.164618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.651361 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.320527 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5790 84.72% 84.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 323 4.73% 89.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 59 0.86% 90.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.67% 90.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 267 3.91% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 35 0.51% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 21 0.31% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 28 0.41% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 23 0.34% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.10% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 12 0.18% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 155 2.27% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.07% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.09% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.18% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6834 # Writes before turning the bus around for reads -system.physmem.totQLat 4674239132 # Total ticks spent queuing -system.physmem.totMemAccLat 8422457882 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 999525000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23382.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6753 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6753 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.231749 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.531627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.015829 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5781 85.61% 85.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 288 4.26% 89.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 56 0.83% 90.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 54 0.80% 91.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 265 3.92% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 16 0.24% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.25% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 13 0.19% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.15% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.16% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 146 2.16% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.18% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.06% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.09% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6753 # Writes before turning the bus around for reads +system.physmem.totQLat 9353740299 # Total ticks spent queuing +system.physmem.totMemAccLat 13072109049 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 991565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47166.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42132.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.07 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 65916.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing -system.physmem.readRowHits 166683 # Number of row buffer hits during reads -system.physmem.writeRowHits 85101 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.75 # Row buffer hit rate for writes -system.physmem.avgGap 8397436.27 # Average gap between requests -system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 335240640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 182919000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 827767200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 458784000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84698340030 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647701064750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1921658314500 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.568191 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740964082488 # Time in different power states -system.physmem_0.memoryStateTime::REF 95835480000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33201034512 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 314352360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 171521625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 731484000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 434192400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83981561895 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648329817500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1921417128660 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.484154 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742009812705 # Time in different power states -system.physmem_1.memoryStateTime::REF 95835480000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32151144795 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing +system.physmem.readRowHits 165583 # Number of row buffer hits during reads +system.physmem.writeRowHits 84490 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.83 # Row buffer hit rate for writes +system.physmem.avgGap 8468025.78 # Average gap between requests +system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 311268300 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 165439230 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 749700000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 363599100 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6175288080.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5556148530 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 353114880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11660360040 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 9231007680 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 675128481165 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 709697287665 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.210424 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2857712170474 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 646078467 # Time in different power states +system.physmem_0.memoryStateTime::REF 2625372000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2808102138000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 24039125004 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9838978559 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25570970970 # Time in different power states +system.physmem_1.actEnergy 294667800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 156619650 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 666254820 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 349583400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6182663760.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5620280370 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 353139840 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11082999060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 9548118720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 675230388855 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 709488226485 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.137601 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2857213980946 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 650996744 # Time in different power states +system.physmem_1.memoryStateTime::REF 2628804000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2808400306500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 24864927177 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9973048810 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24304579769 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -361,9 +371,9 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -371,7 +381,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,61 +411,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 7878 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7878 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1506 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6372 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7878 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7878 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7878 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6484 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12295.265268 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11397.219739 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5676.180841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 5980 92.23% 92.23% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 464 7.16% 99.38% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6484 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5017 77.38% 77.38% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1467 22.62% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6484 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7878 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 7793 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7793 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1456 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6337 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7793 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7793 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7793 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6399 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12413.189561 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11268.612574 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10437.446912 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 6392 99.89% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 4 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6399 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1181299500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1181299500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1181299500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4982 77.86% 77.86% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1417 22.14% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6399 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7793 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7878 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6484 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7793 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6399 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6484 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14362 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14192 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25174501 # DTB read hits -system.cpu0.dtb.read_misses 6776 # DTB read misses -system.cpu0.dtb.write_hits 18763964 # DTB write hits -system.cpu0.dtb.write_misses 1102 # DTB write misses +system.cpu0.dtb.read_hits 25156364 # DTB read hits +system.cpu0.dtb.read_misses 6669 # DTB read misses +system.cpu0.dtb.write_hits 18748845 # DTB write hits +system.cpu0.dtb.write_misses 1124 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3391 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3378 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1765 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1745 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25181277 # DTB read accesses -system.cpu0.dtb.write_accesses 18765066 # DTB write accesses +system.cpu0.dtb.read_accesses 25163033 # DTB read accesses +system.cpu0.dtb.write_accesses 18749969 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43938465 # DTB hits -system.cpu0.dtb.misses 7878 # DTB misses -system.cpu0.dtb.accesses 43946343 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 43905209 # DTB hits +system.cpu0.dtb.misses 7793 # DTB misses +system.cpu0.dtb.accesses 43913002 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,7 +493,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 3349 # Table walker walks requested system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate @@ -494,22 +502,23 @@ system.cpu0.itb.walker.walkWaitTime::samples 3349 system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12613.587655 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11778.875659 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5637.639193 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 386 16.55% 16.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1666 71.41% 87.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 225 9.64% 97.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 98.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.11% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12610.587227 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11657.853110 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5955.666994 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 437 18.73% 18.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1604 68.75% 87.48% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 228 9.77% 97.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 98.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 1.03% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.83% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated @@ -520,7 +529,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 119077538 # ITB inst hits +system.cpu0.itb.inst_hits 119019454 # ITB inst hits system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -537,660 +546,663 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 119080887 # ITB inst accesses -system.cpu0.itb.hits 119077538 # DTB hits +system.cpu0.itb.inst_accesses 119022803 # ITB inst accesses +system.cpu0.itb.hits 119019454 # DTB hits system.cpu0.itb.misses 3349 # DTB misses -system.cpu0.itb.accesses 119080887 # DTB accesses -system.cpu0.numPwrStateTransitions 3762 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1881 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1452265205.015417 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23608911235.366570 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1082 57.52% 57.52% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 794 42.21% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.accesses 119022803 # DTB accesses +system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1460468935.028877 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23678191319.145061 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1076 57.54% 57.54% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 789 42.19% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963656512 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1881 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 138289859366 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731710850634 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5740001420 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499962822056 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 139745754496 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731076908504 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5741645326 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1881 # number of quiesce instructions executed -system.cpu0.committedInsts 115412619 # Number of instructions committed -system.cpu0.committedOps 139453859 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123427491 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 12678366 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15706258 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123427491 # number of integer instructions -system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 227200136 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85767213 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read +system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed +system.cpu0.committedInsts 115354991 # Number of instructions committed +system.cpu0.committedOps 139381682 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123361088 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9690 # Number of float alu accesses +system.cpu0.num_func_calls 12675511 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15701045 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123361088 # number of integer instructions +system.cpu0.num_fp_insts 9690 # number of float instructions +system.cpu0.num_int_register_reads 227079516 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85717450 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7430 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 505219370 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52317118 # number of times the CC registers were written -system.cpu0.num_mem_refs 45075192 # number of memory refs -system.cpu0.num_load_insts 25426401 # Number of load instructions -system.cpu0.num_store_insts 19648791 # Number of store instructions -system.cpu0.num_idle_cycles 5463421701.266096 # Number of idle cycles -system.cpu0.num_busy_cycles 276579718.733904 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048185 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951815 # Percentage of idle cycles -system.cpu0.Branches 29123439 # Number of branches fetched +system.cpu0.num_cc_register_reads 504946337 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52296035 # number of times the CC registers were written +system.cpu0.num_mem_refs 45041487 # number of memory refs +system.cpu0.num_load_insts 25408167 # Number of load instructions +system.cpu0.num_store_insts 19633320 # Number of store instructions +system.cpu0.num_idle_cycles 5462153817.006098 # Number of idle cycles +system.cpu0.num_busy_cycles 279491508.993903 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048678 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951322 # Percentage of idle cycles +system.cpu0.Branches 29114863 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 98023875 68.44% 68.44% # Class of executed instruction -system.cpu0.op_class::IntMult 109907 0.08% 68.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::IntAlu 97984598 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109968 0.08% 68.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8149 0.01% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::MemRead 25426401 17.75% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 19648791 13.72% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 25408167 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19633320 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143219456 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 693439 # number of replacements -system.cpu0.dcache.tags.tagsinuse 491.449824 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43066582 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693951 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.059975 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.449824 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959863 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.959863 # Average percentage of cache occupancy +system.cpu0.op_class::total 143146475 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 692883 # number of replacements +system.cpu0.dcache.tags.tagsinuse 489.706194 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43033783 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693395 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.062436 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1207347000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.706194 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956457 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.956457 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88514427 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88514427 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 23911425 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23911425 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18032865 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18032865 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319065 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 319065 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365782 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365782 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362736 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362736 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41944290 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41944290 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42263355 # number of overall hits -system.cpu0.dcache.overall_hits::total 42263355 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 397667 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 397667 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324388 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324388 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127754 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127754 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21573 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21573 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19602 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19602 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 722055 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 722055 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 849809 # number of overall misses -system.cpu0.dcache.overall_misses::total 849809 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5269907000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5269907000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5597938000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5597938000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327322000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 327322000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 460475500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 460475500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1158000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1158000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10867845000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10867845000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10867845000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10867845000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24309092 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24309092 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18357253 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18357253 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446819 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446819 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387355 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387355 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42666345 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42666345 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43113164 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43113164 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017671 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017671 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285919 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285919 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055693 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055693 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051269 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051269 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016923 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016923 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13252.060141 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13252.060141 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17256.920725 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17256.920725 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15172.762249 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15172.762249 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23491.250893 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23491.250893 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88447658 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88447658 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 23895020 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23895020 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18016527 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18016527 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319201 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 319201 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365698 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365698 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362461 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362461 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41911547 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41911547 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42230748 # number of overall hits +system.cpu0.dcache.overall_hits::total 42230748 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 396353 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396353 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 325830 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 325830 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127542 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127542 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21311 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21311 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19654 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19654 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 722183 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 722183 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 849725 # number of overall misses +system.cpu0.dcache.overall_misses::total 849725 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5544958500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5544958500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6307912000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6307912000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337776000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 337776000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 461133500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 461133500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1598000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1598000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11852870500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11852870500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11852870500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11852870500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291373 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24291373 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18342357 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18342357 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446743 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446743 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387009 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387009 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42633730 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42633730 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43080473 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43080473 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016317 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016317 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017764 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017764 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285493 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285493 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055066 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055066 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051435 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051435 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016939 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016939 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019724 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019724 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13989.949616 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13989.949616 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19359.518767 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19359.518767 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15849.842804 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15849.842804 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.577592 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.577592 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15051.270333 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15051.270333 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12788.573668 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12788.573668 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16412.558174 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16412.558174 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13949.066463 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13949.066463 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 693439 # number of writebacks -system.cpu0.dcache.writebacks::total 693439 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25271 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25271 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15260 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15260 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25271 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25271 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25271 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25271 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372396 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 372396 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324388 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324388 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100689 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100689 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6313 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6313 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19602 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19602 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 696784 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 696784 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 797473 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 797473 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31786 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60249 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4503432000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4503432000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5273550000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5273550000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615902000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615902000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94571500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94571500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440907500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440907500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1124000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1124000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9776982000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9776982000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11392884000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11392884000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628627500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628627500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628627500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628627500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015319 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015319 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017671 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017671 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225346 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225346 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016298 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016298 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051269 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051269 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016331 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016331 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12093.126672 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12093.126672 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16256.920725 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16256.920725 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16048.446206 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16048.446206 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14980.437193 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14980.437193 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22492.985410 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22492.985410 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 692883 # number of writebacks +system.cpu0.dcache.writebacks::total 692883 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25228 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25228 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15026 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15026 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25229 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25229 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25229 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25229 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371125 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 371125 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325829 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325829 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100399 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100399 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19654 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19654 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 696954 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 696954 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 797353 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 797353 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31790 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60254 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4765649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4765649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5981552000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5981552000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664266000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664266000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 99162500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 99162500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 441526500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 441526500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1551000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1551000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10747201500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10747201500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12411467500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12411467500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6632422500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6632422500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6632422500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6632422500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015278 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015278 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224735 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224735 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016240 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016240 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051435 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051435 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016347 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016347 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018508 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018508 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.089929 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.089929 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18357.948494 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18357.948494 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16576.519686 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16576.519686 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15777.645187 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15777.645187 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.968963 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.968963 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14031.582241 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14031.582241 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14286.231634 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14286.231634 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208539.215378 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208539.215378 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110020.539760 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110020.539760 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1105141 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.449200 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 117971876 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1105653 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 106.698825 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14058125000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449200 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15420.245095 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15420.245095 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15565.837841 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15565.837841 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208632.352941 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208632.352941 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110074.393401 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110074.393401 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1103683 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.436898 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117915250 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1104195 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.788430 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14180312000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436898 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 239260738 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 239260738 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 117971876 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 117971876 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 117971876 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 117971876 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 117971876 # number of overall hits -system.cpu0.icache.overall_hits::total 117971876 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1105662 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1105662 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1105662 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1105662 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1105662 # number of overall misses -system.cpu0.icache.overall_misses::total 1105662 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11445416000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11445416000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11445416000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11445416000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11445416000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11445416000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 119077538 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 119077538 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 119077538 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 119077538 # number of demand (read+write) accesses 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overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10351.640917 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10351.640917 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 239143112 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 239143112 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 117915250 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117915250 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117915250 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117915250 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117915250 # number of overall hits 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-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836809 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1836835 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11358993000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11358993000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11358993000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11358993000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11358993000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11358993000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009278 # mshr miss rate for ReadReq accesses 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10287.042068 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1852661 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1852734 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 235109 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 260353 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15640.705301 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1686155 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 275976 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.109789 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236762 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 259898 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15638.452129 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1682248 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 275540 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.105277 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14471.492082 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.272651 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.132938 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1167.807630 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.883270 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000078 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 14455.048208 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.347817 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.124083 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1181.932022 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.882266 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071277 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.954633 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15308 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.072139 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954495 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 340 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15293 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 29 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 131 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 144 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 30 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 149 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 154 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 815 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6065 # Occupied blocks per task id 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of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2205065500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3053362500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3053362500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2745598500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2745598500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3053362500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4950664000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8013907000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2775500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3053362500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4950664000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 24766817842 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377687500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7173328000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377687500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7173328000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032543 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1199,118 +1211,118 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154909 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154909 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056407 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211578 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211578 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110166 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153928 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153928 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056280 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212451 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212451 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110222 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.249260 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17922.885572 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53346.929538 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17108.334694 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17108.334694 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15005.995510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15005.995510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 216874.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 216874.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40084.971472 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40084.971472 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41306.780830 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23832.746722 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23832.746722 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32406.137544 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44091.685230 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200526.253697 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174418.716918 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105793.083703 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102751.209020 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3740310 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1886004 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27868 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 209163 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 207471 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1692 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 61471 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1694410 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 706729 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1319793 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 79890 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 307615 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87684 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41751 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111919 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288494 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284839 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1105662 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 565382 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3277 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3334509 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561453 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10930 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24498 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5931390 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141527480 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96553100 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18124 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 238139696 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 885320 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18675332 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 2797680 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.089870 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.288103 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251989 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21248.387097 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63298.311238 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17135.000543 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17135.000543 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14982.087426 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14982.087426 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 399500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 399500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52937.665050 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52937.665050 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49132.874728 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27047.300293 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27047.300293 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38944.998178 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52645.959519 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200619.298522 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175765.167108 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105846.707273 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103547.087014 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 3736636 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1884055 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27898 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 214108 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212409 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 61364 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1691356 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28464 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28464 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 703950 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1320281 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 79590 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 311154 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41858 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112323 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 289865 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 286282 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104204 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 563680 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3258 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330135 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561187 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10874 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23944 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5926140 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141340856 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96515744 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17900 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39256 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 237913756 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 888922 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18673228 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 2798771 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.091578 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.290526 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2547944 91.07% 91.07% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 248044 8.87% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1692 0.06% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2544165 90.90% 90.90% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 252907 9.04% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1699 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2797680 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3721587498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2798771 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3717731500 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113922479 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114379544 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1667515000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1665328000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1206437474 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1206139485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14255489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14135489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1340,62 +1352,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 3379 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3379 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3379 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3379 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3379 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2609 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12498.275201 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11540.409783 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5547.212388 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 616 23.61% 23.61% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1660 63.63% 87.24% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 255 9.77% 97.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 67 2.57% 99.58% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 5 0.19% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2609 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2073200828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2073200828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2073200828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.13% 74.13% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 675 25.87% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2609 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3379 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 3333 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3333 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 662 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2671 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3333 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3333 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3333 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2563 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11950.253609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10994.949142 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5354.487249 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.12% 0.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 723 28.21% 28.33% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1059 41.32% 69.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 482 18.81% 88.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 76 2.97% 91.42% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 147 5.74% 97.15% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 46 1.79% 98.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 15 0.59% 99.53% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 4 0.16% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 2 0.08% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::53248-57343 2 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2563 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1936423828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1936423828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1936423828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1909 74.48% 74.48% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 654 25.52% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2563 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3333 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3379 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2609 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3333 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2563 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2609 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5988 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2563 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5896 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3943912 # DTB read hits -system.cpu1.dtb.read_misses 2863 # DTB read misses -system.cpu1.dtb.write_hits 3421052 # DTB write hits -system.cpu1.dtb.write_misses 516 # DTB write misses +system.cpu1.dtb.read_hits 3943012 # DTB read hits +system.cpu1.dtb.read_misses 2827 # DTB read misses +system.cpu1.dtb.write_hits 3420749 # DTB write hits +system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1981 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1972 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 312 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3946775 # DTB read accesses -system.cpu1.dtb.write_accesses 3421568 # DTB write accesses +system.cpu1.dtb.read_accesses 3945839 # DTB read accesses +system.cpu1.dtb.write_accesses 3421255 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7364964 # DTB hits -system.cpu1.dtb.misses 3379 # DTB misses -system.cpu1.dtb.accesses 7368343 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7363761 # DTB hits +system.cpu1.dtb.misses 3333 # DTB misses +system.cpu1.dtb.accesses 7367094 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1425,7 +1442,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1746 # Table walker walks requested system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate @@ -1434,24 +1451,24 @@ system.cpu1.itb.walker.walkWaitTime::samples 1746 system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13079.042457 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12148.751119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5740.258970 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 165 14.91% 14.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 593 53.57% 68.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 84.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 63 5.69% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.10% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12715.898826 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11637.572785 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6041.889650 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 210 18.97% 18.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 573 51.76% 70.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 161 14.54% 85.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 52 4.70% 94.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.90% 98.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -2073744828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -2073744828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -2073744828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::samples -1937292828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1937292828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1937292828 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated @@ -1462,7 +1479,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16566340 # ITB inst hits +system.cpu1.itb.inst_hits 16565425 # ITB inst hits system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1479,56 +1496,56 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16568086 # ITB inst accesses -system.cpu1.itb.hits 16566340 # DTB hits +system.cpu1.itb.inst_accesses 16567171 # ITB inst accesses +system.cpu1.itb.hits 16565425 # DTB hits system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 16568086 # DTB accesses -system.cpu1.numPwrStateTransitions 5497 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2749 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1034540641.602037 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25769735768.471432 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1960 71.30% 71.30% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 783 28.48% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 16567171 # DTB accesses +system.cpu1.numPwrStateTransitions 5507 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2754 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1032876592.840595 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25746480816.391750 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1963 71.28% 71.28% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 785 28.50% 99.78% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 929980464320 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2749 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 26048486236 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843952223764 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5739069639 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 929980503556 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2754 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 26280526317 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844542136683 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 5740713090 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2749 # number of quiesce instructions executed -system.cpu1.committedInsts 16210815 # Number of instructions committed -system.cpu1.committedOps 19752329 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17813732 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 1029438 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1815045 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17813732 # number of integer instructions -system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 32326512 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12493939 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read +system.cpu1.kern.inst.quiesce 2754 # number of quiesce instructions executed +system.cpu1.committedInsts 16209756 # Number of instructions committed +system.cpu1.committedOps 19749987 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17811459 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses +system.cpu1.num_func_calls 1029227 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1814790 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17811459 # number of integer instructions +system.cpu1.num_fp_insts 1792 # number of float instructions +system.cpu1.num_int_register_reads 32322640 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12491718 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 72207765 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6423893 # number of times the CC registers were written -system.cpu1.num_mem_refs 7598514 # number of memory refs -system.cpu1.num_load_insts 4055507 # Number of load instructions -system.cpu1.num_store_insts 3543007 # Number of store instructions -system.cpu1.num_idle_cycles 5686981123.489185 # Number of idle cycles -system.cpu1.num_busy_cycles 52088515.510815 # Number of busy cycles -system.cpu1.not_idle_fraction 0.009076 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.990924 # Percentage of idle cycles -system.cpu1.Branches 2922923 # Number of branches fetched +system.cpu1.num_cc_register_reads 72198073 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6423445 # number of times the CC registers were written +system.cpu1.num_mem_refs 7597281 # number of memory refs +system.cpu1.num_load_insts 4054552 # Number of load instructions +system.cpu1.num_store_insts 3542729 # Number of store instructions +system.cpu1.num_idle_cycles 5688160571.384175 # Number of idle cycles +system.cpu1.num_busy_cycles 52552518.615825 # Number of busy cycles +system.cpu1.not_idle_fraction 0.009154 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.990846 # Percentage of idle cycles +system.cpu1.Branches 2922489 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12474914 62.05% 62.05% # Class of executed instruction -system.cpu1.op_class::IntMult 26468 0.13% 62.19% # Class of executed instruction +system.cpu1.op_class::IntAlu 12473914 62.06% 62.06% # Class of executed instruction +system.cpu1.op_class::IntMult 26414 0.13% 62.19% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction @@ -1552,583 +1569,584 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3329 0.02% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3315 0.02% 62.20% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::MemRead 4055507 20.17% 82.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 3543007 17.62% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 4054552 20.17% 82.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 3542729 17.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 20103291 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 186972 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.131643 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7097155 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187306 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.890698 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 127531940000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.131643 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916273 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.916273 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14948788 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14948788 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3631994 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3631994 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3232351 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3232351 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48894 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48894 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78959 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78959 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70892 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70892 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6864345 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6864345 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6913239 # number of overall hits -system.cpu1.dcache.overall_hits::total 6913239 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133677 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133677 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 91948 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 91948 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30343 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30343 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16973 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16973 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23209 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23209 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 225625 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 225625 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255968 # number of overall misses -system.cpu1.dcache.overall_misses::total 255968 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2021367000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2021367000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2373794500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2373794500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317489000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 317489000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544203500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 544203500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1998500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4395161500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4395161500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4395161500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4395161500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3765671 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3765671 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3324299 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3324299 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79237 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79237 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95932 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95932 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94101 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94101 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7089970 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7089970 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7169207 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7169207 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035499 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027659 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027659 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382940 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382940 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176927 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176927 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246639 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246639 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031823 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031823 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035704 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035704 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15121.277407 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15121.277407 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25816.706182 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25816.706182 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18705.532316 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18705.532316 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23447.951226 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23447.951226 # average StoreCondReq miss latency +system.cpu1.op_class::total 20100990 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 186832 # number of replacements +system.cpu1.dcache.tags.tagsinuse 467.596388 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7094042 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187196 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.896333 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105561729000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.596388 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913274 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.913274 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14946466 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14946466 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3631076 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3631076 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3232073 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3232073 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48864 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48864 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70916 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70916 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6863149 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6863149 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6912013 # number of overall hits +system.cpu1.dcache.overall_hits::total 6912013 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133685 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133685 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 91868 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 91868 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30333 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30333 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17012 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17012 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23235 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23235 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225553 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225553 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255886 # number of overall misses +system.cpu1.dcache.overall_misses::total 255886 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2037941500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2037941500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2527681500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2527681500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319638500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 319638500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545121500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 545121500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1812500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1812500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4565623000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4565623000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4565623000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4565623000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3764761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3764761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3323941 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3323941 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79197 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79197 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95985 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95985 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94151 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94151 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7088702 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7088702 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7167899 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7167899 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035510 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035510 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027638 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027638 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.383007 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.383007 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177236 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177236 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246784 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246784 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031819 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031819 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035699 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035699 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.354266 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.354266 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27514.275918 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27514.275918 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18789.001881 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18789.001881 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23461.222294 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23461.222294 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19479.940166 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19479.940166 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17170.745953 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17170.745953 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20241.907667 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20241.907667 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17842.410292 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17842.410292 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 186972 # number of writebacks -system.cpu1.dcache.writebacks::total 186972 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12048 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12048 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133394 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133394 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91948 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91948 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29641 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29641 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23209 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23209 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 225342 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 225342 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254983 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254983 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3099 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3099 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5549 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5549 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1881488500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1881488500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2281846500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2281846500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 500338500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 500338500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85063000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85063000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521039500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521039500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1953500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1953500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4163335000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4163335000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4663673500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4663673500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443787500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443787500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443787500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443787500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035424 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035424 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027659 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027659 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374080 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374080 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051338 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051338 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246639 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246639 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.writebacks::writebacks 186832 # number of writebacks +system.cpu1.dcache.writebacks::total 186832 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 254 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12014 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12014 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 254 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 254 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 254 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133431 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133431 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91868 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91868 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29599 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29599 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4998 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4998 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23235 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23235 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254898 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254898 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3096 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5547 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1895035500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1895035500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2435813500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2435813500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 504348000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 504348000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87440500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87440500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521927500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521927500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1771500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1771500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4330849000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4330849000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4835197000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4835197000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443722000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443722000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443722000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443722000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027638 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027638 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373739 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373739 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052071 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052071 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246784 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246784 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031783 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.031783 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035566 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14104.746091 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14104.746091 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24816.706182 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24816.706182 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16879.946695 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16879.946695 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17271.675127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17271.675127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22449.890129 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22449.890129 # average StoreCondReq mshr miss latency +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035561 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035561 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14202.363019 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14202.363019 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26514.275918 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26514.275918 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17039.359438 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17039.359438 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17495.098039 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17495.098039 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22462.986873 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22462.986873 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18475.628156 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18475.628156 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18290.135029 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18290.135029 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143203.452727 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143203.452727 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79976.121824 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79976.121824 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 505656 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.477037 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16060167 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 506168 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.728926 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 85274966000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.477037 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973588 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973588 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19222.672981 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19222.672981 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18969.144521 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18969.144521 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143321.059432 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143321.059432 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79993.149450 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79993.149450 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 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system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33638838 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33638838 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 16060167 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16060167 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16060167 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16060167 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16060167 # number of overall hits -system.cpu1.icache.overall_hits::total 16060167 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 506168 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 506168 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 506168 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 506168 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 506168 # number of overall misses -system.cpu1.icache.overall_misses::total 506168 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4710776500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4710776500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4710776500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4710776500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4710776500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4710776500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16566335 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16566335 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16566335 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16566335 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16566335 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16566335 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030554 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030554 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030554 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030554 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030554 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030554 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9306.744994 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9306.744994 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9306.744994 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9306.744994 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33637116 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33637116 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 16059144 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16059144 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16059144 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16059144 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16059144 # number of overall hits +system.cpu1.icache.overall_hits::total 16059144 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 506276 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 506276 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 506276 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 506276 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 506276 # number of overall misses +system.cpu1.icache.overall_misses::total 506276 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4773110000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4773110000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4773110000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4773110000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4773110000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4773110000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16565420 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16565420 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16565420 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16565420 # number of demand (read+write) accesses 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overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9427.881235 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9427.881235 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 505656 # number of writebacks -system.cpu1.icache.writebacks::total 505656 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506168 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 506168 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 506168 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 506168 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 506168 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 506168 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 505764 # number of writebacks +system.cpu1.icache.writebacks::total 505764 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506276 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 506276 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 506276 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 506276 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 506276 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 506276 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4457692500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4457692500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4457692500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4457692500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4457692500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4457692500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15627500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15627500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15627500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15627500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030554 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030554 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030554 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8806.744994 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88290.960452 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88290.960452 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 198543 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 198543 # number of prefetch candidates identified +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4519972000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4519972000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4519972000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4519972000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4519972000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4519972000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17010500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17010500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17010500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 17010500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030562 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030562 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030562 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8927.881235 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96104.519774 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96104.519774 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 197759 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 197759 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58537 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 43670 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14604.323800 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 603874 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 58010 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.409826 # Average number of references to valid blocks. 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blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 304 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14134.079332 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.459040 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.079959 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 410.926752 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.862676 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000211 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025081 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.888095 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ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418649000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432949000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14300000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418649000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432949000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119638 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5724 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4606500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10656500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 879904235 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 451017000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 451017000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347632000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347632000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1463500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1463500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1270463000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1270463000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 708558500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 708558500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1173383500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1173383500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4606500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 708558500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2443846500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3163061500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4606500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 708558500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2443846500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4042965735 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15683000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418607000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 434290000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15683000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418607000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 434290000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.123333 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2137,118 +2155,118 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.557598 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.557598 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042134 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.416486 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.416486 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170670 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554559 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554559 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041716 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414300 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414300 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169714 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.205250 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14316.901408 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31612.145031 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15295.007590 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15295.007590 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14951.027707 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14951.027707 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 807750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 807750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32081.102476 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32081.102476 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30344.305341 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16498.234529 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16498.234529 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23082.885782 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24519.847717 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135091.642465 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132157.814408 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75445.846098 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75611.072302 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1488311 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751924 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 112911 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104591 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 12675 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 724258 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 148574 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 578366 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 28228 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30717 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71065 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40939 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85439 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 36 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69452 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66978 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506168 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 262948 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518346 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839098 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5647 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10280 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2373371 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64757444 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29422876 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9292 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16820 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94206432 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 332481 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4905948 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1059226 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.359953 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.203710 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14227.636849 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 34849.072637 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15267.492637 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15267.492637 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14962.854560 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.854560 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 731750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 731750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36756.827913 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36756.827913 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33549.171402 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16855.567846 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16855.567846 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25094.302125 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26722.224877 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135208.979328 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132688.664833 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75465.476834 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75871.767994 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1488382 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751796 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 112776 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104479 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8297 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 12601 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 724485 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2451 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2451 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 147576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 578148 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 27257 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30156 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71390 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40982 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85466 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69531 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66980 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506276 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 248 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518670 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839199 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5528 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9873 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2373270 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64771268 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29426964 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8816 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15476 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94222524 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 331491 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4839132 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1057684 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.131012 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.359912 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 928762 87.68% 87.68% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 122144 11.53% 99.21% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8320 0.79% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 927412 87.68% 87.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 121975 11.53% 99.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8297 0.78% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1059226 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1442372000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1057684 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1442349000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79594348 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79817806 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 759429000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 759591000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 376190500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 376283000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6075998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6005497 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution @@ -2299,27 +2317,27 @@ system.iobus.pkt_size_system.bridge.master::total 162796 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48721500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 48719500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 94000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) @@ -2333,32 +2351,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6166000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32045000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32044000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187728827 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187769062 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.386151 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.383154 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 289285136000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.386151 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899134 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899134 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 289903742000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.383154 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898947 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898947 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328311 # Number of tag accesses system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2367,14 +2385,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 34821377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 34821377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4306604450 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4306604450 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4341425827 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4341425827 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4341425827 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4341425827 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 40888377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 40888377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4391190685 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4391190685 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4432079062 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4432079062 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4432079062 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4432079062 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2391,19 +2409,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 136554.419608 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 136554.419608 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118888.152882 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118888.152882 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119011.645796 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119011.645796 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 160346.576471 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160346.576471 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121223.241083 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 121223.241083 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121496.725842 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121496.725842 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -2415,14 +2433,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 22071377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 22071377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493082245 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2493082245 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2515153622 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2515153622 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2515153622 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2515153622 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 28138377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 28138377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2577641992 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2577641992 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2605780369 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2605780369 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2605780369 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2605780369 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2431,591 +2449,565 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86554.419608 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 86554.419608 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68824.046074 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.046074 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 137913 # number of replacements -system.l2c.tags.tagsinuse 65077.078827 # Cycle average of tags in use -system.l2c.tags.total_refs 526584 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 203352 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.589520 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 102405123000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6467.156176 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.052663 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.040623 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7119.410088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6998.473757 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.432069 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.004586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1431.375532 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3211.021288 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2361.112045 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.098681 # Average percentage of cache occupancy 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6923.893951 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37646.371687 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1427.225105 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3211.431328 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2259.694892 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.097329 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.108634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.106788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571982 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021841 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.048996 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.992997 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 34227 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31208 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 194 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4904 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29129 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.110219 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.105650 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.574438 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021778 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.049003 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034480 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 34321 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31064 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4958 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29180 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1170 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29939 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.522263 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.476196 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6120881 # Number of tag accesses -system.l2c.tags.data_accesses 6120881 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 260820 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 260820 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 40104 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5060 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 45164 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2347 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2252 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4599 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4026 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1389 # number of ReadExReq hits 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task id +system.l2c.tags.tag_accesses 6089608 # Number of tag accesses +system.l2c.tags.data_accesses 6089608 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 259449 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 259449 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 40103 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4906 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 45009 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2386 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2218 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4604 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4006 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1413 # number of ReadExReq hits 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7 # number of ReadSharedReq misses +system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits +system.l2c.overall_hits::cpu1.inst 18793 # number of overall hits +system.l2c.overall_hits::cpu1.data 12238 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5311 # number of overall hits +system.l2c.overall_hits::total 183489 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 592 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 252 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 844 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 118 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 92 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 210 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11217 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8015 # number of ReadExReq misses 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(read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17886 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9091 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2327 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 875 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 169844 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17911 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20658 # number of demand (read+write) misses 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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153288.321522 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96296.444771 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.047962 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 90101.908166 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 504508 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 283356 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.048856 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.018407 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.047125 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.039827 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.043623 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736846 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850127 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.780171 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146823 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.074786 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.488132 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.507455 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.507455 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23138.513514 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21724.206349 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22716.232227 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26203.389831 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23603.260870 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25064.285714 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135808.282072 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92844.479102 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117902.974210 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113679.903201 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 114310.286857 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108684.198324 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182618.763762 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117321.532493 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154577.083617 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96349.628240 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65453.733766 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 90857.860981 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 501880 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 282396 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 44081 # Transaction distribution -system.membus.trans_dist::ReadResp 215279 # Transaction distribution -system.membus.trans_dist::WriteReq 30913 # Transaction distribution -system.membus.trans_dist::WriteResp 30913 # Transaction distribution -system.membus.trans_dist::WritebackDirty 137329 # Transaction distribution -system.membus.trans_dist::CleanEvict 16651 # Transaction distribution -system.membus.trans_dist::UpgradeReq 64792 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38133 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 44082 # Transaction distribution +system.membus.trans_dist::ReadResp 214165 # Transaction distribution +system.membus.trans_dist::WriteReq 30915 # Transaction distribution +system.membus.trans_dist::WriteResp 30915 # Transaction distribution +system.membus.trans_dist::WritebackDirty 136162 # Transaction distribution +system.membus.trans_dist::CleanEvict 16178 # Transaction distribution +system.membus.trans_dist::UpgradeReq 65137 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38197 # Transaction distribution system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40131 # Transaction distribution -system.membus.trans_dist::ReadExResp 19681 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171198 # Transaction distribution +system.membus.trans_dist::ReadExReq 39788 # Transaction distribution +system.membus.trans_dist::ReadExResp 19211 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170083 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650114 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 771800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645838 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 767530 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 844739 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 840469 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18707276 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18897612 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18531148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18721496 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21214732 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123049 # Total snoops (count) +system.membus.pkt_size::total 21038616 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123440 # Total snoops (count) system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 425474 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012172 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.109655 # Request fanout histogram +system.membus.snoop_fanout::samples 424426 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012207 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.109809 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 420295 98.78% 98.78% # Request fanout histogram -system.membus.snoop_fanout::1 5179 1.22% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 419245 98.78% 98.78% # Request fanout histogram +system.membus.snoop_fanout::1 5181 1.22% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 425474 # Request fanout histogram -system.membus.reqLayer0.occupancy 88273000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 424426 # Request fanout histogram +system.membus.reqLayer0.occupancy 88263500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11470000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11456000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 976922430 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 968117274 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1118158241 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1108847564 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1366131 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1391627 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3047,77 +3039,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1015113 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 540228 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 174806 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 29447 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 28379 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1068 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 44084 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 511780 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 361959 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 119582 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109939 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42732 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 152671 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51282 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51282 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 467698 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4573 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1273273 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316945 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1590218 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35272632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5631700 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 40904332 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 389588 # Total snoops (count) -system.toL2Bus.snoopTraffic 15743116 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 889230 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.395392 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.491385 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1012066 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 538478 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 175231 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 28833 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27811 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1022 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 44085 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 510917 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30915 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30915 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 359421 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 118152 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 110125 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42801 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 152926 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50897 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50897 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 466834 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4575 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1272193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 313311 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1585504 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35206412 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5504908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 40711320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 388372 # Total snoops (count) +system.toL2Bus.snoopTraffic 15694348 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 886366 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.396986 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.491624 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 538704 60.58% 60.58% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 349458 39.30% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1068 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 535513 60.42% 60.42% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 349831 39.47% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1022 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 889230 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 894701567 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 886366 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 892357874 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360373 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 677372101 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 676996738 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 239236747 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 237913566 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 657e88994..5d8ec5a8f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -153,7 +153,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -250,7 +250,7 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -382,7 +382,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -499,7 +499,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -544,7 +544,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -556,7 +556,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -588,29 +588,36 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -630,6 +637,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -639,7 +647,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -661,9 +669,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1016,7 +1024,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1333,6 +1341,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1340,7 +1349,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -1571,6 +1580,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1578,7 +1588,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 6d681649a..03ec36b9d 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:28:47 -gem5 executing on e108600-lin, pid 12530 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:01:25 +gem5 executing on e108600-lin, pid 17555 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2909582799500 because m5_exit instruction encountered +Exiting @ tick 2905297782500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index dd34564a7..aaea4a10c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903737 # Number of seconds simulated -sim_ticks 2903736790500 # Number of ticks simulated -final_tick 2903736790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.905298 # Number of seconds simulated +sim_ticks 2905297782500 # Number of ticks simulated +final_tick 2905297782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 515424 # Simulator instruction rate (inst/s) -host_op_rate 621448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13306386787 # Simulator tick rate (ticks/s) -host_mem_usage 582748 # Number of bytes of host memory used -host_seconds 218.22 # Real time elapsed on the host -sim_insts 112476413 # Number of instructions simulated -sim_ops 135613231 # Number of ops (including micro ops) simulated +host_inst_rate 483331 # Simulator instruction rate (inst/s) +host_op_rate 582745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12486239543 # Simulator tick rate (ticks/s) +host_mem_usage 580500 # Number of bytes of host memory used +host_seconds 232.68 # Real time elapsed on the host +sim_insts 112461365 # Number of instructions simulated +sim_ops 135593151 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 512 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1188964 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9028260 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1184612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8933156 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10218824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1188964 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1188964 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7618752 # Number of bytes written to this memory +system.physmem.bytes_read::total 10119304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1184612 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1184612 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7531136 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7636276 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7548660 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27031 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141586 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140100 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168642 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119043 # Number of write requests responded to by this memory +system.physmem.num_reads::total 167087 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117674 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123424 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 176 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 122055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 409460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3109187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3519198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 409460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2623775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2629810 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2623775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3074782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3483052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2592208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2598240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2592208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 409460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3115222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6149008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168642 # Number of read requests accepted -system.physmem.writeReqs 123424 # Number of write requests accepted -system.physmem.readBursts 168642 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123424 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10783744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 7648256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10218824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7636276 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.inst 407742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3080813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6081292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 167087 # Number of read requests accepted +system.physmem.writeReqs 122055 # Number of write requests accepted +system.physmem.readBursts 167087 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122055 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10685312 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue +system.physmem.bytesWritten 7561344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10119304 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7548660 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9943 # Per bank write bursts -system.physmem.perBankRdBursts::1 9648 # Per bank write bursts -system.physmem.perBankRdBursts::2 10560 # Per bank write bursts -system.physmem.perBankRdBursts::3 10245 # Per bank write bursts -system.physmem.perBankRdBursts::4 18706 # Per bank write bursts -system.physmem.perBankRdBursts::5 9867 # Per bank write bursts -system.physmem.perBankRdBursts::6 9999 # Per bank write bursts -system.physmem.perBankRdBursts::7 10271 # Per bank write bursts -system.physmem.perBankRdBursts::8 9694 # Per bank write bursts -system.physmem.perBankRdBursts::9 10419 # Per bank write bursts -system.physmem.perBankRdBursts::10 9828 # Per bank write bursts -system.physmem.perBankRdBursts::11 9028 # Per bank write bursts -system.physmem.perBankRdBursts::12 10140 # Per bank write bursts -system.physmem.perBankRdBursts::13 10489 # Per bank write bursts -system.physmem.perBankRdBursts::14 10151 # Per bank write bursts -system.physmem.perBankRdBursts::15 9508 # Per bank write bursts -system.physmem.perBankWrBursts::0 7397 # Per bank write bursts -system.physmem.perBankWrBursts::1 7199 # Per bank write bursts -system.physmem.perBankWrBursts::2 8385 # Per bank write bursts -system.physmem.perBankWrBursts::3 7801 # Per bank write bursts -system.physmem.perBankWrBursts::4 7213 # Per bank write bursts -system.physmem.perBankWrBursts::5 7134 # Per bank write bursts -system.physmem.perBankWrBursts::6 7314 # Per bank write bursts -system.physmem.perBankWrBursts::7 7590 # Per bank write bursts -system.physmem.perBankWrBursts::8 7388 # Per bank write bursts -system.physmem.perBankWrBursts::9 8015 # Per bank write bursts -system.physmem.perBankWrBursts::10 7407 # Per bank write bursts -system.physmem.perBankWrBursts::11 6899 # Per bank write bursts -system.physmem.perBankWrBursts::12 7622 # Per bank write bursts -system.physmem.perBankWrBursts::13 7751 # Per bank write bursts -system.physmem.perBankWrBursts::14 7507 # Per bank write bursts -system.physmem.perBankWrBursts::15 6882 # Per bank write bursts +system.physmem.perBankRdBursts::0 9954 # Per bank write bursts +system.physmem.perBankRdBursts::1 9813 # Per bank write bursts +system.physmem.perBankRdBursts::2 10094 # Per bank write bursts +system.physmem.perBankRdBursts::3 9518 # Per bank write bursts +system.physmem.perBankRdBursts::4 18811 # Per bank write bursts +system.physmem.perBankRdBursts::5 10188 # Per bank write bursts +system.physmem.perBankRdBursts::6 10467 # Per bank write bursts +system.physmem.perBankRdBursts::7 10858 # Per bank write bursts +system.physmem.perBankRdBursts::8 9262 # Per bank write bursts +system.physmem.perBankRdBursts::9 10094 # Per bank write bursts +system.physmem.perBankRdBursts::10 9505 # Per bank write bursts +system.physmem.perBankRdBursts::11 9184 # Per bank write bursts +system.physmem.perBankRdBursts::12 9983 # Per bank write bursts +system.physmem.perBankRdBursts::13 9847 # Per bank write bursts +system.physmem.perBankRdBursts::14 9958 # Per bank write bursts +system.physmem.perBankRdBursts::15 9422 # Per bank write bursts +system.physmem.perBankWrBursts::0 7103 # Per bank write bursts +system.physmem.perBankWrBursts::1 7218 # Per bank write bursts +system.physmem.perBankWrBursts::2 7869 # Per bank write bursts +system.physmem.perBankWrBursts::3 7374 # Per bank write bursts +system.physmem.perBankWrBursts::4 7424 # Per bank write bursts +system.physmem.perBankWrBursts::5 7558 # Per bank write bursts +system.physmem.perBankWrBursts::6 7579 # Per bank write bursts +system.physmem.perBankWrBursts::7 7921 # Per bank write bursts +system.physmem.perBankWrBursts::8 6916 # Per bank write bursts +system.physmem.perBankWrBursts::9 7516 # Per bank write bursts +system.physmem.perBankWrBursts::10 7047 # Per bank write bursts +system.physmem.perBankWrBursts::11 7122 # Per bank write bursts +system.physmem.perBankWrBursts::12 7779 # Per bank write bursts +system.physmem.perBankWrBursts::13 7383 # Per bank write bursts +system.physmem.perBankWrBursts::14 7451 # Per bank write bursts +system.physmem.perBankWrBursts::15 6886 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2903736355000 # Total gap between requests +system.physmem.numWrRetry 65 # Number of times write queue was full causing retry +system.physmem.totGap 2905297420500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159070 # Read request sizes (log2) +system.physmem.readPktSize::6 157515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119043 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 247 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117674 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 166128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -160,163 +160,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58618 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 314.441571 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.322128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.751512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21316 36.36% 36.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14773 25.20% 61.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5607 9.57% 71.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3267 5.57% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2505 4.27% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1471 2.51% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1045 1.78% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1040 1.77% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7594 12.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58618 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5878 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.661279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 584.674226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5877 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57323 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.311882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.988870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.470779 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20402 35.59% 35.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14531 25.35% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5716 9.97% 70.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3104 5.41% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2370 4.13% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1421 2.48% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1241 2.16% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 946 1.65% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7592 13.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57323 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5761 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.979865 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.542998 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5760 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5878 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.330725 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.604611 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.460490 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5095 86.68% 86.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 41 0.70% 87.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 85 1.45% 88.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 37 0.63% 89.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 285 4.85% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 59 1.00% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.22% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.24% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.07% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.14% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 168 2.86% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.10% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.12% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.09% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.19% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5761 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.507898 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.546505 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.055833 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5040 87.48% 87.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 23 0.40% 87.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 68 1.18% 89.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 38 0.66% 89.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 294 5.10% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 33 0.57% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.03% 95.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 6 0.10% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.05% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 158 2.74% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.10% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.17% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 11 0.19% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.14% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.12% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.07% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5878 # Writes before turning the bus around for reads -system.physmem.totQLat 1493636250 # Total ticks spent queuing -system.physmem.totMemAccLat 4652936250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 842480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8864.52 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5761 # Writes before turning the bus around for reads +system.physmem.totQLat 4504540500 # Total ticks spent queuing +system.physmem.totMemAccLat 7635003000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 834790000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26980.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27614.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45730.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing -system.physmem.readRowHits 138583 # Number of row buffer hits during reads -system.physmem.writeRowHits 90798 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes -system.physmem.avgGap 9942055.41 # Average gap between requests -system.physmem.pageHitRate 79.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 226187640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 123415875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 696064200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 389013840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86978464290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665943648500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1944014583705 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.487777 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2771286006000 # Time in different power states -system.physmem_0.memoryStateTime::REF 96962060000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35486192750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 216964440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118383375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 618196800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385372080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85605070095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1667148388500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943750164650 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.396712 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2773305848750 # Time in different power states -system.physmem_1.memoryStateTime::REF 96962060000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33468782750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing +system.physmem.readRowHits 138094 # Number of row buffer hits during reads +system.physmem.writeRowHits 89686 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.90 # Row buffer hit rate for writes +system.physmem.avgGap 10047995.17 # Average gap between requests +system.physmem.pageHitRate 79.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 210115920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 111679260 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 640479420 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 313440120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6609223920.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4735061820 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 414343200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13903412640 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 9310120320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 682719565725 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 718969243965 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.468348 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2893307612500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 778413000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2810438000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2839095824500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 24245244750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7877734000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 30490128250 # Time in different power states +system.physmem_1.actEnergy 199177440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 105861525 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 551600700 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 303282000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6621516720.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4536550200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 409678080 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13514783790 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 9490661760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 682993594335 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 718728215280 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.385386 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2894278953000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 777246000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2816412000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2839926040500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 24715420500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7425105000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 29637558500 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -329,9 +344,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -339,7 +354,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,58 +384,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 9520 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9520 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1252 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8268 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9520 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9520 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9520 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7356 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10060.290919 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8514.979061 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6541.334463 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6558 89.15% 89.15% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 793 10.78% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 9547 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9547 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1253 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8294 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9547 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9547 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9547 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7383 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9942.435324 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8397.692517 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6587.109188 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6605 89.46% 89.46% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 773 10.47% 99.93% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7356 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6151 83.62% 83.62% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1205 16.38% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7356 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9520 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 7383 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1003066500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1003066500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6177 83.67% 83.67% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1206 16.33% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7383 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9547 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9520 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7356 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9547 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7383 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7356 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16876 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7383 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16930 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24525489 # DTB read hits -system.cpu.dtb.read_misses 8109 # DTB read misses -system.cpu.dtb.write_hits 19608938 # DTB write hits -system.cpu.dtb.write_misses 1411 # DTB write misses +system.cpu.dtb.read_hits 24520121 # DTB read hits +system.cpu.dtb.read_misses 8133 # DTB read misses +system.cpu.dtb.write_hits 19605715 # DTB write hits +system.cpu.dtb.write_misses 1414 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4199 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4209 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1628 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24533598 # DTB read accesses -system.cpu.dtb.write_accesses 19610349 # DTB write accesses +system.cpu.dtb.read_accesses 24528254 # DTB read accesses +system.cpu.dtb.write_accesses 19607129 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44134427 # DTB hits -system.cpu.dtb.misses 9520 # DTB misses -system.cpu.dtb.accesses 44143947 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44125836 # DTB hits +system.cpu.dtb.misses 9547 # DTB misses +system.cpu.dtb.accesses 44135383 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -450,39 +465,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 4762 # Table walker walks requested -system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 4763 # Table walker walks requested +system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10273.897650 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8288.299297 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7346.561217 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1812 58.32% 58.32% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 745 23.98% 82.30% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 548 17.64% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10156.853282 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8221.468352 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7284.204444 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 769 24.74% 83.33% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 516 16.60% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 1002711000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 1002711000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115574516 # ITB inst hits -system.cpu.itb.inst_misses 4762 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115559307 # ITB inst hits +system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -498,55 +513,55 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115579278 # ITB inst accesses -system.cpu.itb.hits 115574516 # DTB hits -system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115579278 # DTB accesses -system.cpu.numPwrStateTransitions 6062 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3031 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 888232478.174860 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17469824950.226959 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2968 97.92% 97.92% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 57 1.88% 99.80% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 115564070 # ITB inst accesses +system.cpu.itb.hits 115559307 # DTB hits +system.cpu.itb.misses 4763 # DTB misses +system.cpu.itb.accesses 115564070 # DTB accesses +system.cpu.numPwrStateTransitions 6066 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887205638.526871 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17463817933.974155 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499964073052 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3031 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 211504149152 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2692232641348 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5807473581 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 499962880972 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 214403080848 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2690894701652 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5810595565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3031 # number of quiesce instructions executed -system.cpu.committedInsts 112476413 # Number of instructions committed -system.cpu.committedOps 135613231 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119916333 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9896179 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15232917 # number of instructions that are conditional controls -system.cpu.num_int_insts 119916333 # number of integer instructions -system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218092554 # number of times the integer registers were read -system.cpu.num_int_register_writes 82663252 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.committedInsts 112461365 # Number of instructions committed +system.cpu.committedOps 135593151 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119897812 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11226 # Number of float alu accesses +system.cpu.num_func_calls 9894928 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15231225 # number of instructions that are conditional controls +system.cpu.num_int_insts 119897812 # number of integer instructions +system.cpu.num_fp_insts 11226 # number of float instructions +system.cpu.num_int_register_reads 218061607 # number of times the integer registers were read +system.cpu.num_int_register_writes 82648736 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8514 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489835813 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51902110 # number of times the CC registers were written -system.cpu.num_mem_refs 45414800 # number of memory refs -system.cpu.num_load_insts 24847736 # Number of load instructions -system.cpu.num_store_insts 20567064 # Number of store instructions -system.cpu.num_idle_cycles 5384465282.694146 # Number of idle cycles -system.cpu.num_busy_cycles 423008298.305854 # Number of busy cycles -system.cpu.not_idle_fraction 0.072839 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927161 # Percentage of idle cycles -system.cpu.Branches 25923023 # Number of branches fetched +system.cpu.num_cc_register_reads 489758493 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51897030 # number of times the CC registers were written +system.cpu.num_mem_refs 45406070 # number of memory refs +system.cpu.num_load_insts 24842315 # Number of load instructions +system.cpu.num_store_insts 20563755 # Number of store instructions +system.cpu.num_idle_cycles 5381789403.302147 # Number of idle cycles +system.cpu.num_busy_cycles 428806161.697852 # Number of busy cycles +system.cpu.not_idle_fraction 0.073797 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.926203 # Percentage of idle cycles +system.cpu.Branches 25920117 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93194210 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114540 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93182494 67.18% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114558 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -570,502 +585,502 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24847736 17.91% 85.18% # Class of executed instruction -system.cpu.op_class::MemWrite 20567064 14.82% 100.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8431 0.01% 67.27% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction +system.cpu.op_class::MemRead 24842315 17.91% 85.18% # Class of executed instruction +system.cpu.op_class::MemWrite 20563755 14.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138734340 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 819770 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.827215 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43243016 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 820282 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.717256 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1013099500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.827215 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999663 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy +system.cpu.op_class::total 138713890 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 821351 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.816254 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43232645 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821863 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.603226 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.816254 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999641 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177141047 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177141047 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23117557 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23117557 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18826251 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18826251 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392764 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392764 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443415 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443415 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460277 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460277 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41943808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41943808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42336572 # number of overall hits -system.cpu.dcache.overall_hits::total 42336572 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 400061 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 400061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298752 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298752 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118460 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118460 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22645 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22645 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177108261 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177108261 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23111024 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23111024 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18823159 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18823159 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392414 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392414 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443071 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443071 # number of LoadLockedReq hits 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demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20802666000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20802666000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20802666000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512476 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512476 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19121896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19121896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511126 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511126 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465932 # number of LoadLockedReq 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accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14917.056399 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14917.056399 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42163.372965 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42163.372965 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12371.362332 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12371.362332 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016423 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016423 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018980 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018980 # miss rate for overall accesses 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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22714.716502 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22714.716502 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29710.072566 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29710.072566 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25403.151297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25403.151297 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 683946 # number of writebacks -system.cpu.dcache.writebacks::total 683946 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14146 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14146 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 399381 # number of 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-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19383034500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19383034500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281205500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281205500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281205500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281205500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses 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ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13910.005734 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41163.372965 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41163.372965 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13141.077395 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13141.077395 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12808.389222 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12808.389222 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016407 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016407 # mshr miss rate for demand accesses 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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.008310 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.008310 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1698000 # number of replacements -system.cpu.icache.tags.tagsinuse 510.728664 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113875998 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1698512 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.044565 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25832791500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.728664 # Average occupied blocks per requestor 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# Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117273034 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117273034 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 113875998 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113875998 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113875998 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113875998 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113875998 # number of overall hits -system.cpu.icache.overall_hits::total 113875998 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1698518 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1698518 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1698518 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1698518 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1698518 # number of overall misses -system.cpu.icache.overall_misses::total 1698518 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23414403500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23414403500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23414403500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23414403500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23414403500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23414403500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115574516 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115574516 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115574516 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115574516 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115574516 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115574516 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014696 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014696 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014696 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13785.195977 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13785.195977 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13785.195977 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13785.195977 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117259828 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117259828 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 113858786 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113858786 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113858786 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113858786 # number of demand (read+write) hits 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demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24021238000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24021238000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115559307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115559307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115559307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115559307 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115559307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115559307 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14125.810854 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14125.810854 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14125.810854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14125.810854 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1698000 # number of writebacks -system.cpu.icache.writebacks::total 1698000 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1698518 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1698518 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1698518 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1698518 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1698518 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1698518 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1700003 # number of writebacks +system.cpu.icache.writebacks::total 1700003 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700521 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1700521 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1700521 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1700521 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1700521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1700521 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21715885500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21715885500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21715885500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21715885500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21715885500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21715885500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 687287000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 687287000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12785.195977 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12785.195977 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 89464 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65017.694965 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4847707 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 154877 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 31.300367 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 144041988000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.877834 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.040783 # Average occupied blocks per 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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436872 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010607 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.431842 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.431842 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010555 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063103 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063103 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 89750 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19050 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19050 # average UpgradeReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062404 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062404 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138277.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19236.842105 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19236.842105 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67844.557863 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67844.557863 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71264.459369 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71264.459369 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73668.237044 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73668.237044 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189217.692209 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161015.251494 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100326.263899 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 95446.021343 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5058492 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539687 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38280 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82462.928039 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82462.928039 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 103832.265433 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 103832.265433 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115003.419296 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115003.419296 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.494829 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.945717 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100388.194527 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.566119 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5065968 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543576 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 219 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 219 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 67163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2290209 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 67217 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2293895 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 766799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1698000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 142435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2750 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 767045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1700003 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 142341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2814 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2752 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296002 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296002 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1698518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 524530 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 4455 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5113056 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2583569 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22910 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7731495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217411704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96469597 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10980 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313912769 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 113519 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5394688 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2710473 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021286 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.144336 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 526163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119073 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2588406 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22839 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7742205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217668600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96672157 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10684 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 19992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 314371433 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112178 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5305776 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2712615 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021718 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.145761 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2652778 97.87% 97.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 57695 2.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2653703 97.83% 97.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 58912 2.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2710473 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4962792000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2712615 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4970051500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 347876 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2556799000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2559803500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1276777495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1279174000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17788000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17841000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 30159 # Transaction distribution +system.iobus.trans_dist::ReadResp 30159 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1237,9 +1252,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178346 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -1260,22 +1275,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 338500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 642000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1297,56 +1312,56 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6273000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6292000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187671849 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187581870 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.078594 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36400 # number of replacements +system.iocache.tags.tagsinuse 1.079755 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309373303000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.078594 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067412 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067412 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 310620847000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079755 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067485 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067485 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.tags.tag_accesses 327906 # Number of tag accesses +system.iocache.tags.data_accesses 327906 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses +system.iocache.ReadReq_misses::total 210 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses -system.iocache.demand_misses::total 36458 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36458 # number of overall misses -system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28897377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28897377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4278807472 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4278807472 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4307704849 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4307704849 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4307704849 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4307704849 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36434 # number of demand (read+write) misses +system.iocache.demand_misses::total 36434 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36434 # number of overall misses +system.iocache.overall_misses::total 36434 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4367688494 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4367688494 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4401754870 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4401754870 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4401754870 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4401754870 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36434 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36434 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36434 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36434 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1355,14 +1370,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123493.064103 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118120.789311 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118120.789311 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118155.270421 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118155.270421 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120574.439432 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120574.439432 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120814.482901 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120814.482901 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1371,22 +1386,22 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 210 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17197377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17197377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465502723 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2465502723 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2482700100 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2482700100 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2482700100 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2482700100 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36434 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2554457612 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2554457612 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2578023988 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2578023988 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2578023988 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2578023988 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1395,90 +1410,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68062.685595 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68062.685595 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 321817 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 130498 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70518.374890 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70518.374890 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 318841 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 128997 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70519 # Transaction distribution +system.membus.trans_dist::ReadResp 70464 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 119043 # Transaction distribution -system.membus.trans_dist::CleanEvict 6845 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117674 # Transaction distribution +system.membus.trans_dist::CleanEvict 6761 # Transaction distribution system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 129207 # Transaction distribution -system.membus.trans_dist::ReadExResp 129207 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30359 # Transaction distribution +system.membus.trans_dist::ReadExReq 127683 # Transaction distribution +system.membus.trans_dist::ReadExResp 127683 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30304 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 435887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543479 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 538940 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 611789 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15537980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15701333 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15350844 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15514197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18018453 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoopTraffic 31744 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 263669 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018793 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.135792 # Request fanout histogram +system.membus.pkt_size::total 17831317 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 474 # Total snoops (count) +system.membus.snoopTraffic 30208 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 262090 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018417 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134455 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 258714 98.12% 98.12% # Request fanout histogram -system.membus.snoop_fanout::1 4955 1.88% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 257263 98.16% 98.16% # Request fanout histogram +system.membus.snoop_fanout::1 4827 1.84% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 263669 # Request fanout histogram -system.membus.reqLayer0.occupancy 90449000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 262090 # Request fanout histogram +system.membus.reqLayer0.occupancy 90471500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1734500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1726500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 828323280 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 819732726 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 954014500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 945419750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1085624 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1510,28 +1525,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |