Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

1 files changed, 143 insertions, 143 deletions

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 9447623bf..ba49bebdd 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    21979500                       # Number of ticks simulated
-final_tick                                   21979500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21628500                       # Number of ticks simulated
+final_tick                                   21628500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39186                       # Simulator instruction rate (inst/s)
-host_op_rate                                    39182                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              134757534                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222636                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  48865                       # Simulator instruction rate (inst/s)
+host_op_rate                                    48859                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              165354272                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218640                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           19264                       # Nu
 system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   469                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            876453059                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            489183102                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1365636161                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       876453059                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          876453059                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           876453059                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           489183102                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1365636161                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            890676653                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            497121853                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1387798507                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       890676653                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          890676653                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           890676653                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           497121853                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1387798507                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -60,7 +60,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            43960                       # number of cpu cycles simulated
+system.cpu.numCycles                            43258                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.lookups              1606                       # Number of BP lookups
@@ -90,12 +90,12 @@ system.cpu.execution_unit.executions             4463                       # Nu
 system.cpu.mult_div_unit.multiplies                 1                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         12066                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         11927                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             536                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           36556                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             7404                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         16.842584                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                             526                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           35855                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             7403                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         17.113597                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              1183                       # Number of Load instructions committed
 system.cpu.comStores                              865                       # Number of Store instructions committed
 system.cpu.comBranches                           1050                       # Number of Branches instructions committed
@@ -107,34 +107,34 @@ system.cpu.committedInsts                        6390                       # Nu
 system.cpu.committedOps                          6390                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  6390                       # Number of Instructions committed (Total)
-system.cpu.cpi                               6.879499                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               6.769640                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         6.879499                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.145359                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         6.769640                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.147718                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.145359                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    39048                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.147718                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    38346                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                      4912                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               11.173794                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    40082                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization               11.355125                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    39380                       # Number of cycles 0 instructions are processed.
 system.cpu.stage1.runCycles                      3878                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                8.821656                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    39789                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization                8.964816                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    39087                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                      4171                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                9.488171                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    42620                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization                9.642147                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    41918                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                      1340                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                3.048226                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    39501                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      4459                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               10.143312                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.utilization                3.097693                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    38800                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      4458                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               10.305608                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                138.677707                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                138.677886                       # Cycle average of tags in use
 system.cpu.icache.total_refs                      557                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    301                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   1.850498                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     138.677707                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     138.677886                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.067714                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.067714                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst          557                       # number of ReadReq hits
@@ -149,12 +149,12 @@ system.cpu.icache.demand_misses::cpu.inst          351                       # n
 system.cpu.icache.demand_misses::total            351                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          351                       # number of overall misses
 system.cpu.icache.overall_misses::total           351                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     19781500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     19781500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     19781500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     19781500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     19781500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     19781500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19444500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19444500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19444500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19444500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19444500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19444500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst          908                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total          908                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst          908                       # number of demand (read+write) accesses
@@ -167,12 +167,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.386564
 system.cpu.icache.demand_miss_rate::total     0.386564                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.386564                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.386564                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56357.549858                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56357.549858                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56357.549858                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56357.549858                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56357.549858                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56357.549858                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55397.435897                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55397.435897                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -193,34 +193,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          302
 system.cpu.icache.demand_mshr_misses::total          302                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          302                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16493500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16493500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16493500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16493500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16493500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16493500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16495000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     16495000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16495000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     16495000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16495000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     16495000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.332599                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.332599                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.332599                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.332599                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.332599                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.332599                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54614.238411                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54614.238411                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54614.238411                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54614.238411                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                102.489186                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                102.512660                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1700                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  10.119048                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     102.489186                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.025022                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.025022                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data     102.512660                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.025028                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.025028                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1086                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1086                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          614                       # number of WriteReq hits
@@ -237,14 +237,14 @@ system.cpu.dcache.demand_misses::cpu.data          348                       # n
 system.cpu.dcache.demand_misses::total            348                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          348                       # number of overall misses
 system.cpu.dcache.overall_misses::total           348                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5918000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5918000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     15290000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     15290000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     21208000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     21208000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     21208000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     21208000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5810500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5810500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     13883000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     13883000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     19693500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     19693500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     19693500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     19693500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1183                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1183                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
@@ -261,20 +261,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.169922
 system.cpu.dcache.demand_miss_rate::total     0.169922                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.169922                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.169922                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60916.334661                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60942.528736                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60942.528736                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60942.528736                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60942.528736                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56590.517241                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 56590.517241                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      1689000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1690000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              37                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 45648.648649                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 45675.675676                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
@@ -293,14 +293,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          168
 system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5509500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5509500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5512000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5512000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4096500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      4096500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9606000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9606000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9606000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9606000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9608500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9608500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9608500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9608500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
@@ -309,23 +309,23 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.082031
 system.cpu.dcache.demand_mshr_miss_rate::total     0.082031                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.082031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57178.571429                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 57178.571429                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               194.900917                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               194.915514                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   395                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002532                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    138.748296                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     56.152621                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    138.751655                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     56.163860                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::cpu.inst     0.004234                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.001714                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::total        0.005948                       # Average percentage of cache occupancy
@@ -346,17 +346,17 @@ system.cpu.l2cache.demand_misses::total           469                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          469                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     16152000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5390000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     21542000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4007500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4007500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     16152000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9397500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     25549500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     16152000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9397500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     25549500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     16176500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5410500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     21587000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4019000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4019000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     16176500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9429500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     25606000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     16176500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9429500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     25606000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          302                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           95                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          397                       # number of ReadReq accesses(hits+misses)
@@ -379,17 +379,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.997872                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996689                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997872                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53661.129568                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56736.842105                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 54398.989899                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54897.260274                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54897.260274                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53661.129568                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55937.500000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 54476.545842                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53661.129568                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55937.500000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 54476.545842                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -409,17 +409,17 @@ system.cpu.l2cache.demand_mshr_misses::total          469
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          469                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12487000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4239000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16726000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3129500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3129500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12487000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7368500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     19855500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12487000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7368500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     19855500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12511500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4259000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16770500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3141000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3141000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12511500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7400000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     19911500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12511500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7400000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     19911500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997481                       # mshr miss rate for ReadReq accesses
@@ -431,17 +431,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.997872
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997872                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41485.049834                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44621.052632                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42237.373737                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42869.863014                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42869.863014                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41485.049834                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43860.119048                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42335.820896                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41485.049834                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43860.119048                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42335.820896                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------