diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt | 528 |
1 files changed, 343 insertions, 185 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 062194e2a..ecf052997 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21628500 # Number of ticks simulated -final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 19841500 # Number of ticks simulated +final_tick 19841500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34038 # Simulator instruction rate (inst/s) -host_op_rate 34033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115179622 # Simulator tick rate (ticks/s) -host_mem_usage 212112 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 31060 # Simulator instruction rate (inst/s) +host_op_rate 31057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96425663 # Simulator tick rate (ticks/s) +host_mem_usage 216044 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::total 30016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 29952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19200 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 468 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 967668775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 541894514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1509563289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 967668775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 967668775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 967668775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 541894514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1509563289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 469 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 29952 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 19827000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 469 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1719468 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11463468 # Sum of mem lat for all requests +system.physmem.totBusLat 1876000 # Total cycles spent in databus access +system.physmem.totBankLat 7868000 # Total cycles spent in bank access +system.physmem.avgQLat 3666.24 # Average queueing delay per request +system.physmem.avgBankLat 16776.12 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24442.36 # Average memory access latency +system.physmem.avgRdBW 1509.56 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1509.56 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.43 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 401 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42275.05 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +218,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 43258 # number of cpu cycles simulated +system.cpu.numCycles 39684 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1606 # Number of BP lookups @@ -90,12 +248,12 @@ system.cpu.execution_unit.executions 4463 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11913 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7403 # Number of cycles cpu stages are processed. -system.cpu.activity 17.113597 # Percentage of cycles cpu is active +system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32282 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7402 # Number of cycles cpu stages are processed. +system.cpu.activity 18.652354 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -107,72 +265,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.210329 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.210329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.161022 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.161022 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34772 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 12.377784 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35806 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41918 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 9.772200 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 35512 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4172 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 10.513053 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38344 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.376676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35226 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 11.233747 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use -system.cpu.icache.total_refs 557 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 142.150123 # Cycle average of tags in use +system.cpu.icache.total_refs 558 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 557 # number of overall hits -system.cpu.icache.overall_hits::total 557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses -system.cpu.icache.overall_misses::total 351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 142.150123 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069409 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069409 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits +system.cpu.icache.overall_hits::total 558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17305000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17305000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17305000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17305000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17305000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17305000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49442.857143 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49442.857143 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49442.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49442.857143 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,46 +339,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 49 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16495000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14791500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14791500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14791500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14791500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14791500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14791500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48978.476821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48978.476821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.512660 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 104.047429 # Cycle average of tags in use system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.512660 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025028 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025028 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 104.047429 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025402 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits @@ -237,14 +395,14 @@ system.cpu.dcache.demand_misses::cpu.data 348 # n system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses system.cpu.dcache.overall_misses::total 348 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5810500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5810500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13883000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19693500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19693500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19693500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19693500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11296500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11296500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16650500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16650500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16650500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16650500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -261,20 +419,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.169922 system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55195.876289 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55195.876289 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45005.976096 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45005.976096 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47846.264368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47846.264368 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2586 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 69.891892 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits @@ -293,14 +451,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9608500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9608500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9608500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9608500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8525500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8525500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8525500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8525500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -309,26 +467,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53457.894737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53457.894737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47219.178082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47219.178082 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 194.915514 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.193487 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.751655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.163860 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.245680 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.947807 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006079 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -346,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16176500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5410500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21587000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4019000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4019000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16176500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9429500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25606000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16176500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9429500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25606000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14473000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19450000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3369500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3369500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8346500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22819500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8346500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22819500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -379,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48083.056478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52389.473684 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49116.161616 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46157.534247 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46157.534247 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48655.650320 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48655.650320 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12511500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4259000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16770500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3141000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3141000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19911500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19911500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10688499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3791620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14480119 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2447596 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2447596 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10688499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6239216 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16927715 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10688499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6239216 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16927715 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -431,17 +589,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35509.963455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39911.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36565.957071 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33528.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33528.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |