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authorAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:33 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:33 -0600
commitf3585c841e964c98911784a187fc4f081a02a0a6 (patch)
tree2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf /tests/quick/se/00.hello/ref/alpha/linux/inorder-timing
parentcfc4a999828a5b51f4c514e3a7c47b4eebc450b9 (diff)
downloadgem5-f3585c841e964c98911784a187fc4f081a02a0a6.tar.xz
stats: update stats for cache occupancy and clock domain changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/inorder-timing')
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini37
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr1
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt31
4 files changed, 65 insertions, 14 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 8be59c81c..38d5b70ef 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -56,6 +60,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
fetchBuffSize=4
function_trace=false
function_trace_start=0
@@ -90,6 +95,7 @@ BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
+eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
@@ -105,6 +111,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -113,6 +120,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
@@ -127,11 +135,14 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
+sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.icache]
@@ -140,6 +151,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -148,6 +160,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
@@ -162,17 +175,23 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
+sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.l2cache]
@@ -181,6 +200,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -189,6 +209,7 @@ mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
+sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
@@ -203,12 +224,15 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=20
+sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -218,6 +242,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -227,7 +252,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -241,11 +267,13 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+eventq_index=0
voltage_domain=system.voltage_domain
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -265,6 +293,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+eventq_index=0
in_addr_map=true
mem_sched_policy=frfcfs
null=false
@@ -276,17 +305,21 @@ static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCL=13750
+tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
+tRRD=6250
tWTR=7500
tXAW=40000
write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
@@ -1,2 +1 @@
warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
index b50e34b75..b1e32f7df 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:26
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:08
+gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 25046000 because target called exit()
+Exiting @ tick 25485000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 3b67933ac..116ba4c72 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds 0.000025 # Nu
sim_ticks 25485000 # Number of ticks simulated
final_tick 25485000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 27492 # Simulator instruction rate (inst/s)
-host_op_rate 27490 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 109632626 # Simulator tick rate (ticks/s)
-host_mem_usage 225100 # Number of bytes of host memory used
-host_seconds 0.23 # Real time elapsed on the host
+host_inst_rate 24806 # Simulator instruction rate (inst/s)
+host_op_rate 24805 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 98922905 # Simulator tick rate (ticks/s)
+host_mem_usage 229760 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 29952 # Number of bytes read from this memory
@@ -214,6 +216,7 @@ system.membus.reqLayer0.occupancy 560000 # La
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 4374750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 17.2 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 1632 # Number of BP lookups
system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
@@ -325,6 +328,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
system.cpu.icache.tags.occ_blocks::cpu.inst 142.311081 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.069488 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.146973 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 2131 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 2131 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
@@ -430,6 +439,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 56.745411
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004344 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006076 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012054 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 4228 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 4228 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@@ -553,6 +568,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy
system.cpu.dcache.tags.occ_blocks::cpu.data 103.493430 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025267 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025267 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits