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author | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-07-10 22:51:55 -0700 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-07-10 22:51:55 -0700 |
commit | b00fe08cc9338cb96a151a8cd3c3d1498c716989 (patch) | |
tree | e6fdf2b84d5c80ff492a9ff9522e860a7ccc1c7e /tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt | |
parent | 387f843d513dd80554cb6361da36ba805dfbcea2 (diff) | |
download | gem5-b00fe08cc9338cb96a151a8cd3c3d1498c716989.tar.xz |
regress: ruby stat additions and config changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt')
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index bae589857..dc174d88f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000279 # Nu sim_ticks 279353 # Number of ticks simulated final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12119 # Simulator instruction rate (inst/s) -host_op_rate 12118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 528605 # Simulator tick rate (ticks/s) -host_mem_usage 226340 # Number of bytes of host memory used -host_seconds 0.53 # Real time elapsed on the host +host_inst_rate 24575 # Simulator instruction rate (inst/s) +host_op_rate 24573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1071866 # Simulator tick rate (ticks/s) +host_mem_usage 236072 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory @@ -33,6 +33,24 @@ system.physmem.bw_write::total 23969673 # Wr system.physmem.bw_total::cpu.inst 91840789 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 55485354 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 147326143 # Total bandwidth to/from this memory (bytes/s) +system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads +system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes +system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv |