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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:32:57 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:32:57 -0500 |
commit | 5b49c3d255eb82089496f8a77d6ab50004b5a2c2 (patch) | |
tree | c27568e48e0c39d9943830a870dbf234273c5b7d /tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini | |
parent | 4ef466cc8a6890a63f504cec02a65ed3f6386e12 (diff) | |
download | gem5-5b49c3d255eb82089496f8a77d6ab50004b5a2c2.tar.xz |
stats: updates statistics for ruby regressions
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini')
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 97e4f32c9..56cc19d50 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -52,6 +52,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -183,10 +184,10 @@ tagArrayBanks=1 [system.ruby.l1_cntrl0] type=L1Cache_Controller -children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer -L1DcacheMemory=system.ruby.l1_cntrl0.L1DcacheMemory -L1IcacheMemory=system.ruby.l1_cntrl0.L1IcacheMemory -L2cacheMemory=system.ruby.l1_cntrl0.L2cacheMemory +children=L1Dcache L1Icache L2cache sequencer +L1Dcache=system.ruby.l1_cntrl0.L1Dcache +L1Icache=system.ruby.l1_cntrl0.L1Icache +L2cache=system.ruby.l1_cntrl0.L2cache buffer_size=0 cache_response_latency=10 clock=1 @@ -203,7 +204,7 @@ sequencer=system.ruby.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 -[system.ruby.l1_cntrl0.L1DcacheMemory] +[system.ruby.l1_cntrl0.L1Dcache] type=RubyCache assoc=2 dataAccessLatency=1 @@ -217,7 +218,7 @@ start_index_bit=6 tagAccessLatency=1 tagArrayBanks=1 -[system.ruby.l1_cntrl0.L1IcacheMemory] +[system.ruby.l1_cntrl0.L1Icache] type=RubyCache assoc=2 dataAccessLatency=1 @@ -231,7 +232,7 @@ start_index_bit=6 tagAccessLatency=1 tagArrayBanks=1 -[system.ruby.l1_cntrl0.L2cacheMemory] +[system.ruby.l1_cntrl0.L2cache] type=RubyCache assoc=2 dataAccessLatency=1 @@ -249,9 +250,9 @@ tagArrayBanks=1 type=RubySequencer access_phys_mem=false clock=1 -dcache=system.ruby.l1_cntrl0.L1DcacheMemory +dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 -icache=system.ruby.l1_cntrl0.L1IcacheMemory +icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby support_data_reqs=true |