diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/quick/se/00.hello/ref/alpha/linux/simple-timing | |
parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/simple-timing')
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt | 120 |
1 files changed, 60 insertions, 60 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 6a791ec60..aa2f4f81d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 34409000 # Number of ticks simulated -final_tick 34409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 32544000 # Number of ticks simulated +final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55813 # Simulator instruction rate (inst/s) -host_op_rate 55804 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 300451871 # Simulator tick rate (ticks/s) -host_mem_usage 222640 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 68117 # Simulator instruction rate (inst/s) +host_op_rate 68101 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 346770993 # Simulator tick rate (ticks/s) +host_mem_usage 218620 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 517074021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 312476387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 829550408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517074021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517074021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517074021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 312476387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 829550408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 68818 # number of cpu cycles simulated +system.cpu.numCycles 65088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 68818 # Number of busy cycles +system.cpu.num_busy_cycles 65088 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 128.208060 # Cycle average of tags in use +system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use system.cpu.icache.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 128.208060 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.062602 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.062602 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.892123 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.892123 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025364 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025364 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.769601 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 128.220906 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.548695 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003913 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001726 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005639 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits |