summaryrefslogtreecommitdiff
path: root/tests/quick/se/00.hello/ref/alpha/linux
diff options
context:
space:
mode:
authorJoel Hestness <hestness@cs.wisc.edu>2012-09-05 20:53:34 -0500
committerJoel Hestness <hestness@cs.wisc.edu>2012-09-05 20:53:34 -0500
commit4124ea09f8e2f6934fe746ff7c244dba7230cac9 (patch)
treeb2bfebc3b4e62ff6a06deec45852f58fa2aded23 /tests/quick/se/00.hello/ref/alpha/linux
parent6924e10978c5847fa33cf33c50f5b3511bf89ee4 (diff)
downloadgem5-4124ea09f8e2f6934fe746ff7c244dba7230cac9.tar.xz
stats: Update Ruby regressions for memory controller fix
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux')
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats120
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt40
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats106
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt40
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats108
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt38
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats98
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt40
16 files changed, 347 insertions, 323 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index 2e69d465e..80e83bbd8 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
system=system
@@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -119,9 +119,9 @@ bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
+clock=3
dimm_bit_0=12
dimms_per_channel=2
-mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -130,6 +130,7 @@ rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
+ruby_system=system.ruby
tFaw=0
version=0
@@ -183,6 +184,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
+clock=1
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
@@ -227,6 +229,7 @@ tagArrayBanks=1
[system.physmem]
type=SimpleMemory
+clock=1
conf_table_reported=false
file=
in_addr_map=true
@@ -351,6 +354,7 @@ ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
+clock=1
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index e4800c012..5862ff012 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -1,26 +1,26 @@
-Real time: Jul/10/2012 17:30:50
+Real time: Sep/01/2012 14:02:52
Profiler Stats
--------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.62
-Virtual_time_in_minutes: 0.0103333
-Virtual_time_in_hours: 0.000172222
-Virtual_time_in_days: 7.17593e-06
+Virtual_time_in_seconds: 0.56
+Virtual_time_in_minutes: 0.00933333
+Virtual_time_in_hours: 0.000155556
+Virtual_time_in_days: 6.48148e-06
-Ruby_current_time: 279353
+Ruby_current_time: 138616
Ruby_start_time: 0
-Ruby_cycles: 279353
+Ruby_cycles: 138616
-mbytes_resident: 47.9336
-mbytes_total: 230.535
-resident_ratio: 0.20794
+mbytes_resident: 49.5195
+mbytes_total: 259.898
+resident_ratio: 0.190594
-ruby_cycles_executed: [ 279354 ]
+ruby_cycles_executed: [ 138617 ]
Busy Controller Counts:
L1Cache-0:0
@@ -30,15 +30,15 @@ Directory-0:0
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_NULL: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 1 max: 113 count: 8448 average: 15.4081 | standard deviation: 27.0652 | 0 0 0 6958 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 269 472 460 8 43 37 35 30 26 2 16 29 14 0 4 0 0 2 0 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 1 0 1 6 0 0 1 ]
+miss_latency_LD: [binsize: 1 max: 113 count: 1183 average: 37.6915 | standard deviation: 35.8089 | 0 0 0 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 94 211 147 0 28 22 17 10 4 2 12 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 3 0 0 1 ]
+miss_latency_ST: [binsize: 1 max: 110 count: 865 average: 20.5237 | standard deviation: 31.2331 | 0 0 0 649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 37 82 0 6 10 3 3 6 0 4 20 5 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 ]
+miss_latency_IFETCH: [binsize: 1 max: 98 count: 6400 average: 10.5978 | standard deviation: 21.9071 | 0 0 0 5709 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 155 224 231 8 9 5 15 17 16 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 ]
+miss_latency_NULL: [binsize: 1 max: 113 count: 8448 average: 15.4081 | standard deviation: 27.0652 | 0 0 0 6958 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 269 472 460 8 43 37 35 30 26 2 16 29 14 0 4 0 0 2 0 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 1 0 1 6 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 0
-miss_latency_LD_NULL: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_NULL: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_NULL: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_NULL: [binsize: 1 max: 113 count: 1183 average: 37.6915 | standard deviation: 35.8089 | 0 0 0 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 94 211 147 0 28 22 17 10 4 2 12 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 3 0 0 1 ]
+miss_latency_ST_NULL: [binsize: 1 max: 110 count: 865 average: 20.5237 | standard deviation: 31.2331 | 0 0 0 649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 37 82 0 6 10 3 3 6 0 4 20 5 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 ]
+miss_latency_IFETCH_NULL: [binsize: 1 max: 98 count: 6400 average: 10.5978 | standard deviation: 21.9071 | 0 0 0 5709 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 155 224 231 8 9 5 15 17 16 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -65,10 +65,10 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 18 count: 9645 average: 0.0636599 | standard deviation: 0.52686 | 9495 0 1 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017 | standard deviation: 0.0240441 | 6919 0 1 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 2725 average: 0.224587 | standard deviation: 0.972266 | 2576 0 0 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 2 count: 5879 average: 0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ]
+Total_delay_cycles: [binsize: 1 max: 4 count: 9645 average: 0.0609642 | standard deviation: 0.490156 | 9498 0 0 0 147 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standard deviation: 0 | 6920 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 4 count: 2725 average: 0.21578 | standard deviation: 0.90398 | 2578 0 0 0 147 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 5879 average: 0 | standard deviation: 0 | 5879 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -83,11 +83,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 13465
-page_faults: 0
+page_reclaims: 10172
+page_faults: 15
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1112
+block_outputs: 80
Network Stats
-------------
@@ -102,9 +102,9 @@ total_msgs: 37671 total_bytes: 976248
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 1.87549
- links_utilized_percent_switch_0_link_0: 2.66455 bw: 16000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 1.08644 bw: 16000 base_latency: 1
+links_utilized_percent_switch_0: 3.77969
+ links_utilized_percent_switch_0_link_0: 5.36987 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 2.1895 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
@@ -116,9 +116,9 @@ links_utilized_percent_switch_0: 1.87549
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 3.64029
- links_utilized_percent_switch_1_link_0: 3.69819 bw: 16000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 3.58239 bw: 16000 base_latency: 1
+links_utilized_percent_switch_1: 7.33627
+ links_utilized_percent_switch_1_link_0: 7.45296 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 7.21959 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
@@ -132,9 +132,9 @@ links_utilized_percent_switch_1: 3.64029
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 1.76479
- links_utilized_percent_switch_2_link_0: 0.917835 bw: 16000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 2.61175 bw: 16000 base_latency: 1
+links_utilized_percent_switch_2: 3.55659
+ links_utilized_percent_switch_2_link_0: 1.84971 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 5.26346 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
@@ -144,10 +144,10 @@ links_utilized_percent_switch_2: 1.76479
switch_3_inlinks: 3
switch_3_outlinks: 3
-links_utilized_percent_switch_3: 2.42686
- links_utilized_percent_switch_3_link_0: 2.66455 bw: 16000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 3.69819 bw: 16000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0.917835 bw: 16000 base_latency: 1
+links_utilized_percent_switch_3: 4.89085
+ links_utilized_percent_switch_3_link_0: 5.36987 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 7.45296 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 1.84971 bw: 16000 base_latency: 1
outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
@@ -186,8 +186,8 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
--- L1Cache ---
- Event Counts -
-Load [1185 ] 1185
-Ifetch [6414 ] 6414
+Load [1183 ] 1183
+Ifetch [6400 ] 6400
Store [865 ] 865
Inv [1041 ] 1041
L1_Replacement [1354 ] 1354
@@ -216,12 +216,12 @@ I Inv [0 ] 0
I L1_Replacement [556 ] 556
S Load [0 ] 0
-S Ifetch [5723 ] 5723
+S Ifetch [5709 ] 5709
S Store [0 ] 0
S Inv [325 ] 325
S L1_Replacement [362 ] 362
-E Load [454 ] 454
+E Load [452 ] 452
E Ifetch [0 ] 0
E Store [71 ] 71
E Inv [219 ] 219
@@ -307,7 +307,7 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory
--- L2Cache ---
- Event Counts -
L1_GET_INSTR [691 ] 691
-L1_GETS [585 ] 585
+L1_GETS [583 ] 583
L1_GETX [216 ] 216
L1_UPGRADE [0 ] 0
L1_PUTX [436 ] 436
@@ -364,7 +364,7 @@ MT L2_Replacement_clean [352 ] 352
MT MEM_Inv [0 ] 0
M_I L1_GET_INSTR [0 ] 0
-M_I L1_GETS [2 ] 2
+M_I L1_GETS [0 ] 0
M_I L1_GETX [0 ] 0
M_I L1_UPGRADE [0 ] 0
M_I L1_PUTX [0 ] 0
@@ -518,19 +518,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1737
memory_reads: 1460
memory_writes: 277
- memory_refreshes: 582
- memory_total_request_delays: 821
- memory_delays_per_request: 0.472654
- memory_delays_in_input_queue: 84
+ memory_refreshes: 963
+ memory_total_request_delays: 341
+ memory_delays_per_request: 0.196315
+ memory_delays_in_input_queue: 0
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 737
- memory_stalls_for_bank_busy: 197
+ memory_delays_stalled_at_head_of_bank_queue: 341
+ memory_stalls_for_bank_busy: 166
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 40
- memory_stalls_for_bus: 242
+ memory_stalls_for_arbitration: 24
+ memory_stalls_for_bus: 147
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 258
+ memory_stalls_for_read_write_turnaround: 4
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index f5d6aede8..226bed9cc 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 16:55:16
-gem5 started Aug 13 2012 18:08:58
-gem5 executing on zizzer
+gem5 compiled Sep 1 2012 14:01:54
+gem5 started Sep 1 2012 14:02:52
+gem5 executing on doudou.cs.wisc.edu
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 279353 because target called exit()
+Exiting @ tick 138616 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 192390555..682a62f27 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000279 # Number of seconds simulated
-sim_ticks 279353 # Number of ticks simulated
-final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000139 # Number of seconds simulated
+sim_ticks 138616 # Number of ticks simulated
+final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 30486 # Simulator instruction rate (inst/s)
-host_op_rate 30483 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1332529 # Simulator tick rate (ticks/s)
-host_mem_usage 233960 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 27614 # Simulator instruction rate (inst/s)
+host_op_rate 27611 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 598893 # Simulator tick rate (ticks/s)
+host_mem_usage 266140 # Number of bytes of host memory used
+host_seconds 0.23 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
@@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 1183 # Nu
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 91640326 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 31458406 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 123098732 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 91640326 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 91640326 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 23969673 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 23969673 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 91640326 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 55428078 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 147068404 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 184682865 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 63398165 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 248081030 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 184682865 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 184682865 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 48306112 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 48306112 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 184682865 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 111704277 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 296387141 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@@ -84,7 +84,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 279353 # number of cpu cycles simulated
+system.cpu.numCycles 138616 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
@@ -103,7 +103,7 @@ system.cpu.num_mem_refs 2058 # nu
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 279353 # Number of busy cycles
+system.cpu.num_busy_cycles 138616 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index adbe51989..562053d7f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
system=system
@@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -118,9 +118,9 @@ bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
+clock=3
dimm_bit_0=12
dimms_per_channel=2
-mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -129,6 +129,7 @@ rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
+ruby_system=system.ruby
tFaw=0
version=0
@@ -180,6 +181,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
+clock=1
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
@@ -223,6 +225,7 @@ tagArrayBanks=1
[system.physmem]
type=SimpleMemory
+clock=1
conf_table_reported=false
file=
in_addr_map=true
@@ -347,6 +350,7 @@ ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
+clock=1
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index a84c970a4..1e3f433da 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Jul/10/2012 17:36:36
+Real time: Sep/01/2012 14:11:17
Profiler Stats
--------------
@@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.67
-Virtual_time_in_minutes: 0.0111667
-Virtual_time_in_hours: 0.000186111
-Virtual_time_in_days: 7.75463e-06
+Virtual_time_in_seconds: 0.58
+Virtual_time_in_minutes: 0.00966667
+Virtual_time_in_hours: 0.000161111
+Virtual_time_in_days: 6.71296e-06
-Ruby_current_time: 223694
+Ruby_current_time: 117611
Ruby_start_time: 0
-Ruby_cycles: 223694
+Ruby_cycles: 117611
-mbytes_resident: 48.0078
-mbytes_total: 230.77
-resident_ratio: 0.208051
+mbytes_resident: 49.6211
+mbytes_total: 260.035
+resident_ratio: 0.190885
-ruby_cycles_executed: [ 223695 ]
+ruby_cycles_executed: [ 117612 ]
Busy Controller Counts:
L2Cache-0:0
@@ -30,15 +30,15 @@ Directory-0:0
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4289 | standard deviation: 56.47 | 0 7102 0 0 0 0 0 0 0 164 89 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243 195 220 185 167 17 4 19 5 3 3 5 21 6 1 2 1 0 0 0 0 1 0 0 0 0 0 3 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 259 count: 1185 average: 62.8405 | standard deviation: 79.0945 | 0 660 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95 54 83 83 64 4 1 2 2 1 3 3 5 6 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 233 count: 865 average: 29.4509 | standard deviation: 59.7812 | 0 674 0 0 0 0 0 0 0 0 61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 41 10 37 6 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9746 | standard deviation: 47.4906 | 0 5768 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148 110 96 92 66 7 2 16 3 2 0 2 14 0 1 2 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_NULL: [binsize: 2 max: 276 count: 8464 average: 25.4289 | standard deviation: 56.47 | 0 7102 0 0 0 0 0 0 0 164 89 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243 195 220 185 167 17 4 19 5 3 3 5 21 6 1 2 1 0 0 0 0 1 0 0 0 0 0 3 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 1 max: 113 count: 8448 average: 12.9218 | standard deviation: 24.261 | 0 0 0 7086 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 88 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 316 301 294 68 55 13 19 22 2 2 1 2 1 0 0 0 0 0 0 0 3 2 3 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 1 ]
+miss_latency_LD: [binsize: 1 max: 113 count: 1183 average: 29.4725 | standard deviation: 33.3864 | 0 0 0 658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 136 145 102 9 2 2 3 3 1 0 0 1 0 0 0 0 0 0 0 0 2 2 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 ]
+miss_latency_ST: [binsize: 1 max: 95 count: 865 average: 15.259 | standard deviation: 26.186 | 0 0 0 674 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 47 44 1 2 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
+miss_latency_IFETCH: [binsize: 1 max: 105 count: 6400 average: 9.54656 | standard deviation: 20.3893 | 0 0 0 5754 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180 156 161 12 9 10 14 19 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 ]
+miss_latency_NULL: [binsize: 1 max: 113 count: 8448 average: 12.9218 | standard deviation: 24.261 | 0 0 0 7086 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 88 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 316 301 294 68 55 13 19 22 2 2 1 2 1 0 0 0 0 0 0 0 3 2 3 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 0
-miss_latency_LD_NULL: [binsize: 2 max: 259 count: 1185 average: 62.8405 | standard deviation: 79.0945 | 0 660 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95 54 83 83 64 4 1 2 2 1 3 3 5 6 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_NULL: [binsize: 2 max: 233 count: 865 average: 29.4509 | standard deviation: 59.7812 | 0 674 0 0 0 0 0 0 0 0 61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 41 10 37 6 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9746 | standard deviation: 47.4906 | 0 5768 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148 110 96 92 66 7 2 16 3 2 0 2 14 0 1 2 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_NULL: [binsize: 1 max: 113 count: 1183 average: 29.4725 | standard deviation: 33.3864 | 0 0 0 658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 136 145 102 9 2 2 3 3 1 0 0 1 0 0 0 0 0 0 0 0 2 2 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 ]
+miss_latency_ST_NULL: [binsize: 1 max: 95 count: 865 average: 15.259 | standard deviation: 26.186 | 0 0 0 674 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 47 44 1 2 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
+miss_latency_IFETCH_NULL: [binsize: 1 max: 105 count: 6400 average: 9.54656 | standard deviation: 20.3893 | 0 0 0 5754 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180 156 161 12 9 10 14 19 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -83,11 +83,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 13444
-page_faults: 0
+page_reclaims: 10188
+page_faults: 19
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1176
+block_outputs: 80
Network Stats
-------------
@@ -102,9 +102,9 @@ total_msgs: 44262 total_bytes: 1125744
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 5.24221
- links_utilized_percent_switch_0_link_0: 6.11058 bw: 16000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 4.37383 bw: 16000 base_latency: 1
+links_utilized_percent_switch_0: 9.97058
+ links_utilized_percent_switch_0_link_0: 11.6222 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 8.31895 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1
@@ -120,9 +120,9 @@ links_utilized_percent_switch_0: 5.24221
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 3.33894
- links_utilized_percent_switch_1_link_0: 3.04255 bw: 16000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 3.63532 bw: 16000 base_latency: 1
+links_utilized_percent_switch_1: 6.3506
+ links_utilized_percent_switch_1_link_0: 5.78687 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 6.91432 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 253 18216 [ 0 0 253 0 0 0 0 0 0 0 ] base_latency: 1
@@ -134,9 +134,9 @@ links_utilized_percent_switch_1: 3.33894
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 1.90327
- links_utilized_percent_switch_2_link_0: 1.33128 bw: 16000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 2.47526 bw: 16000 base_latency: 1
+links_utilized_percent_switch_2: 3.61998
+ links_utilized_percent_switch_2_link_0: 2.53208 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 4.70789 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Request_Control: 1109 8872 [ 0 1109 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1
@@ -147,10 +147,10 @@ links_utilized_percent_switch_2: 1.90327
switch_3_inlinks: 3
switch_3_outlinks: 3
-links_utilized_percent_switch_3: 3.4948
- links_utilized_percent_switch_3_link_0: 6.11058 bw: 16000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 3.04255 bw: 16000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 1.33128 bw: 16000 base_latency: 1
+links_utilized_percent_switch_3: 6.64705
+ links_utilized_percent_switch_3_link_0: 11.6222 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 5.78687 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 2.53208 bw: 16000 base_latency: 1
outgoing_messages_switch_3_link_0_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1
@@ -183,8 +183,8 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
--- L1Cache ---
- Event Counts -
-Load [1185 ] 1185
-Ifetch [6414 ] 6414
+Load [1183 ] 1183
+Ifetch [6400 ] 6400
Store [865 ] 865
L1_Replacement [1379 ] 1379
Own_GETX [0 ] 0
@@ -224,8 +224,8 @@ O Fwd_GETX [0 ] 0
O Fwd_GETS [0 ] 0
O Fwd_DMA [0 ] 0
-M Load [307 ] 307
-M Ifetch [3481 ] 3481
+M Load [305 ] 305
+M Ifetch [3467 ] 3467
M Store [51 ] 51
M L1_Replacement [1086 ] 1086
M Fwd_GETX [0 ] 0
@@ -1199,19 +1199,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1303
memory_reads: 1109
memory_writes: 194
- memory_refreshes: 466
- memory_total_request_delays: 279
- memory_delays_per_request: 0.214121
- memory_delays_in_input_queue: 12
+ memory_refreshes: 817
+ memory_total_request_delays: 115
+ memory_delays_per_request: 0.0882579
+ memory_delays_in_input_queue: 0
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 267
- memory_stalls_for_bank_busy: 123
+ memory_delays_stalled_at_head_of_bank_queue: 115
+ memory_stalls_for_bank_busy: 40
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 16
- memory_stalls_for_bus: 58
+ memory_stalls_for_arbitration: 17
+ memory_stalls_for_bus: 55
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 70
+ memory_stalls_for_read_write_turnaround: 3
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 74 17 45 40 54 99 29 16 19 22 31 34 52 48 38 30 39 21 21 27 28 37 55 22 31 21 32 69 84 103 13 52
@@ -1240,7 +1240,7 @@ I GETS [979 ] 979
I PUTX [0 ] 0
I PUTO [0 ] 0
I Memory_Data [0 ] 0
-I Memory_Ack [190 ] 190
+I Memory_Ack [193 ] 193
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
@@ -1281,7 +1281,7 @@ IS PUTO_SHARERS [0 ] 0
IS Unblock [0 ] 0
IS Exclusive_Unblock [979 ] 979
IS Memory_Data [979 ] 979
-IS Memory_Ack [3 ] 3
+IS Memory_Ack [1 ] 1
IS DMA_READ [0 ] 0
IS DMA_WRITE [0 ] 0
@@ -1328,7 +1328,7 @@ MM PUTO [0 ] 0
MM PUTO_SHARERS [0 ] 0
MM Exclusive_Unblock [130 ] 130
MM Memory_Data [130 ] 130
-MM Memory_Ack [1 ] 1
+MM Memory_Ack [0 ] 0
MM DMA_READ [0 ] 0
MM DMA_WRITE [0 ] 0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index 871e7f56e..0b27bcc43 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 16:57:01
-gem5 started Aug 13 2012 18:09:22
-gem5 executing on zizzer
+gem5 compiled Sep 1 2012 14:10:16
+gem5 started Sep 1 2012 14:11:17
+gem5 executing on doudou.cs.wisc.edu
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 223694 because target called exit()
+Exiting @ tick 117611 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 46c57187f..05d596c9a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000224 # Number of seconds simulated
-sim_ticks 223694 # Number of ticks simulated
-final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000118 # Number of seconds simulated
+sim_ticks 117611 # Number of ticks simulated
+final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 29074 # Simulator instruction rate (inst/s)
-host_op_rate 29072 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1017648 # Simulator tick rate (ticks/s)
-host_mem_usage 235156 # Number of bytes of host memory used
-host_seconds 0.22 # Real time elapsed on the host
+host_inst_rate 24451 # Simulator instruction rate (inst/s)
+host_op_rate 24449 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 449950 # Simulator tick rate (ticks/s)
+host_mem_usage 266280 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
@@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 1183 # Nu
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 114442050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 39285810 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 153727860 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 114442050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 114442050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 29933749 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 29933749 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 114442050 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 69219559 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 183661609 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 217666715 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 74720902 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 292387617 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 217666715 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 217666715 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 56933450 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 56933450 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 217666715 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 131654352 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 349321067 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@@ -84,7 +84,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 223694 # number of cpu cycles simulated
+system.cpu.numCycles 117611 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
@@ -103,7 +103,7 @@ system.cpu.num_mem_refs 2058 # nu
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 223694 # Number of busy cycles
+system.cpu.num_busy_cycles 117611 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index f5efe89cb..490417398 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
system=system
@@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -121,9 +121,9 @@ bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
+clock=3
dimm_bit_0=12
dimms_per_channel=2
-mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -132,6 +132,7 @@ rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
+ruby_system=system.ruby
tFaw=0
version=0
@@ -214,6 +215,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
+clock=1
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
@@ -229,6 +231,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+clock=1
conf_table_reported=false
file=
in_addr_map=true
@@ -330,6 +333,7 @@ ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
+clock=1
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index 16dff144b..6604bf6a9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Jul/10/2012 17:50:25
+Real time: Sep/01/2012 13:54:22
Profiler Stats
--------------
@@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.53
-Virtual_time_in_minutes: 0.00883333
-Virtual_time_in_hours: 0.000147222
-Virtual_time_in_days: 6.13426e-06
+Virtual_time_in_seconds: 0.47
+Virtual_time_in_minutes: 0.00783333
+Virtual_time_in_hours: 0.000130556
+Virtual_time_in_days: 5.43981e-06
-Ruby_current_time: 208400
+Ruby_current_time: 93341
Ruby_start_time: 0
-Ruby_cycles: 208400
+Ruby_cycles: 93341
-mbytes_resident: 45.6484
-mbytes_total: 228.203
-resident_ratio: 0.200068
+mbytes_resident: 47.3203
+mbytes_total: 257.496
+resident_ratio: 0.183832
-ruby_cycles_executed: [ 208401 ]
+ruby_cycles_executed: [ 93342 ]
Busy Controller Counts:
L1Cache-0:0
@@ -29,17 +29,17 @@ Directory-0:0
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ]
+miss_latency: [binsize: 1 max: 128 count: 8448 average: 10.0489 | standard deviation: 19.8982 | 0 0 7086 0 0 0 0 0 0 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 840 107 39 100 1 1 10 0 0 4 0 0 2 0 0 1 0 0 2 0 0 0 0 0 1 3 0 16 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 1 0 1 ]
+miss_latency_LD: [binsize: 1 max: 122 count: 1183 average: 22.776 | standard deviation: 26.5223 | 0 0 658 0 0 0 0 0 0 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 314 33 13 37 0 0 6 0 0 1 0 0 2 0 0 1 0 0 2 0 0 0 0 0 1 0 0 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ]
+miss_latency_ST: [binsize: 1 max: 128 count: 865 average: 14.3214 | standard deviation: 27.0647 | 0 0 674 0 0 0 0 0 0 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108 7 1 11 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 0 0 0 1 0 1 ]
+miss_latency_IFETCH: [binsize: 1 max: 90 count: 6400 average: 7.11891 | standard deviation: 15.9003 | 0 0 5754 0 0 0 0 0 0 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 418 67 25 52 0 1 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 7 0 0 2 0 0 0 1 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 7086 average: 2 | standard deviation: 0 | 0 0 7086 ]
miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
-miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 1 max: 128 count: 1159 average: 58.742 | standard deviation: 10.823 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 840 107 39 100 1 1 10 0 0 4 0 0 2 0 0 1 0 0 2 0 0 0 0 0 1 3 0 16 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 1 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -47,18 +47,18 @@ miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 avera
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
imcomplete_dir_Times: 1158
-miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 658 average: 2 | standard deviation: 0 | 0 0 658 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
-miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_Directory: [binsize: 1 max: 122 count: 420 average: 57.769 | standard deviation: 7.42617 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 314 33 13 37 0 0 6 0 0 1 0 0 2 0 0 1 0 0 2 0 0 0 0 0 1 0 0 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
-miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
+miss_latency_ST_Directory: [binsize: 1 max: 128 count: 158 average: 67.1582 | standard deviation: 23.8632 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108 7 1 11 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 0 0 0 1 0 1 ]
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5754 average: 2 | standard deviation: 0 | 0 0 5754 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_Directory: [binsize: 1 max: 90 count: 581 average: 57.1566 | standard deviation: 4.1703 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 418 67 25 52 0 1 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 7 0 0 2 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -90,11 +90,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 12815
-page_faults: 0
+page_reclaims: 9600
+page_faults: 19
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1136
+block_outputs: 80
Network Stats
-------------
@@ -108,9 +108,9 @@ total_msgs: 20718 total_bytes: 430512
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 2.15187
- links_utilized_percent_switch_0_link_0: 2.77687 bw: 16000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 1.52687 bw: 16000 base_latency: 1
+links_utilized_percent_switch_0: 4.80443
+ links_utilized_percent_switch_0_link_0: 6.19985 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 3.40901 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
@@ -121,9 +121,9 @@ links_utilized_percent_switch_0: 2.15187
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 2.15187
- links_utilized_percent_switch_1_link_0: 1.52687 bw: 16000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 2.77687 bw: 16000 base_latency: 1
+links_utilized_percent_switch_1: 4.80443
+ links_utilized_percent_switch_1_link_0: 3.40901 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 6.19985 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
@@ -134,9 +134,9 @@ links_utilized_percent_switch_1: 2.15187
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 2.15187
- links_utilized_percent_switch_2_link_0: 2.77687 bw: 16000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 1.52687 bw: 16000 base_latency: 1
+links_utilized_percent_switch_2: 4.80443
+ links_utilized_percent_switch_2_link_0: 6.19985 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 3.40901 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
@@ -183,8 +183,8 @@ Cache Stats: system.l1_cntrl0.L2cacheMemory
--- L1Cache ---
- Event Counts -
-Load [1193 ] 1193
-Ifetch [6425 ] 6425
+Load [1191 ] 1191
+Ifetch [6411 ] 6411
Store [892 ] 892
L2_Replacement [1143 ] 1143
L1_to_L2 [1354 ] 1354
@@ -253,8 +253,8 @@ O NC_DMA_GETS [0 ] 0
O Invalidate [0 ] 0
O Flush_line [0 ] 0
-M Load [306 ] 306
-M Ifetch [5768 ] 5768
+M Load [304 ] 304
+M Ifetch [5754 ] 5754
M Store [60 ] 60
M L2_Replacement [923 ] 923
M L1_to_L2 [1061 ] 1061
@@ -590,26 +590,26 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1379
memory_reads: 1159
memory_writes: 220
- memory_refreshes: 435
- memory_total_request_delays: 495
- memory_delays_per_request: 0.358956
- memory_delays_in_input_queue: 3
+ memory_refreshes: 649
+ memory_total_request_delays: 167
+ memory_delays_per_request: 0.121102
+ memory_delays_in_input_queue: 1
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 492
- memory_stalls_for_bank_busy: 124
+ memory_delays_stalled_at_head_of_bank_queue: 166
+ memory_stalls_for_bank_busy: 114
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 23
- memory_stalls_for_bus: 78
+ memory_stalls_for_arbitration: 11
+ memory_stalls_for_bus: 33
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 267
+ memory_stalls_for_read_write_turnaround: 8
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
--- Directory ---
- Event Counts -
-GETX [189 ] 189
-GETS [1027 ] 1027
+GETX [186 ] 186
+GETS [1022 ] 1022
PUT [1143 ] 1143
Unblock [0 ] 0
UnblockS [0 ] 0
@@ -909,8 +909,8 @@ WB_O_W DMA_WRITE [0 ] 0
WB_O_W Memory_Ack [0 ] 0
WB_O_W GETF [0 ] 0
-WB_E_W GETX [4 ] 4
-WB_E_W GETS [7 ] 7
+WB_E_W GETX [1 ] 1
+WB_E_W GETS [2 ] 2
WB_E_W PUT [0 ] 0
WB_E_W Pf_Replacement [0 ] 0
WB_E_W DMA_READ [0 ] 0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index d96b1791c..d752652fe 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 16:53:31
-gem5 started Aug 13 2012 18:06:43
-gem5 executing on zizzer
+gem5 compiled Sep 1 2012 13:53:26
+gem5 started Sep 1 2012 13:54:22
+gem5 executing on doudou.cs.wisc.edu
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 208110 because target called exit()
+Exiting @ tick 93341 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 02a4e6d9e..c852b744d 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000208 # Number of seconds simulated
-sim_ticks 208110 # Number of ticks simulated
-final_tick 208110 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000093 # Number of seconds simulated
+sim_ticks 93341 # Number of ticks simulated
+final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 43199 # Simulator instruction rate (inst/s)
-host_op_rate 43194 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1406596 # Simulator tick rate (ticks/s)
-host_mem_usage 231928 # Number of bytes of host memory used
+host_inst_rate 42148 # Simulator instruction rate (inst/s)
+host_op_rate 42141 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 615474 # Simulator tick rate (ticks/s)
+host_mem_usage 263680 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
@@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 1183 # Nu
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 123011869 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 42227668 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 165239537 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 123011869 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 123011869 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 32175292 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 32175292 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 123011869 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 74402960 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 197414829 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 274263186 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 94149409 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 368412595 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 274263186 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 274263186 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 71736964 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 71736964 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 274263186 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 165886374 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 440149559 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@@ -90,7 +90,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 208110 # number of cpu cycles simulated
+system.cpu.numCycles 93341 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
@@ -109,7 +109,7 @@ system.cpu.num_mem_refs 2058 # nu
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 208110 # Number of busy cycles
+system.cpu.num_busy_cycles 93341 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 0ae04efdd..e4e42d50c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
system=system
@@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -118,9 +118,9 @@ bank_busy_time=11
bank_queue_size=12
banks_per_rank=8
basic_bus_busy_time=2
+clock=3
dimm_bit_0=12
dimms_per_channel=2
-mem_bus_cycle_multiplier=10
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -129,6 +129,7 @@ rank_rank_delay=1
ranks_per_dimm=2
read_write_delay=2
refresh_period=1560
+ruby_system=system.ruby
tFaw=0
version=0
@@ -165,6 +166,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
+clock=1
dcache=system.l1_cntrl0.cacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.cacheMemory
@@ -180,6 +182,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+clock=1
conf_table_reported=false
file=
in_addr_map=true
@@ -281,6 +284,7 @@ ruby_system=system.ruby
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
+clock=1
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index a61eed778..12453125c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Jul/10/2012 17:16:10
+Real time: Sep/01/2012 13:43:15
Profiler Stats
--------------
@@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.53
-Virtual_time_in_minutes: 0.00883333
-Virtual_time_in_hours: 0.000147222
-Virtual_time_in_days: 6.13426e-06
+Virtual_time_in_seconds: 0.47
+Virtual_time_in_minutes: 0.00783333
+Virtual_time_in_hours: 0.000130556
+Virtual_time_in_days: 5.43981e-06
-Ruby_current_time: 342698
+Ruby_current_time: 143853
Ruby_start_time: 0
-Ruby_cycles: 342698
+Ruby_cycles: 143853
-mbytes_resident: 46.8906
-mbytes_total: 229.363
-resident_ratio: 0.204455
+mbytes_resident: 48.5508
+mbytes_total: 258.688
+resident_ratio: 0.187727
-ruby_cycles_executed: [ 342699 ]
+ruby_cycles_executed: [ 143854 ]
Busy Controller Counts:
L1Cache-0:0
@@ -29,16 +29,16 @@ Directory-0:0
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average: 3 | standard deviation: 0 | 0 0 0 6734 ]
-miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 1 max: 123 count: 8448 average: 16.0281 | standard deviation: 25.9113 | 0 0 0 6718 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 14 10 309 629 543 10 7 7 7 24 22 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 42 37 51 2 1 1 3 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD: [binsize: 1 max: 98 count: 1183 average: 41.5604 | standard deviation: 30.9227 | 0 0 0 456 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 9 4 103 318 220 1 4 2 4 12 9 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 10 13 11 1 0 0 0 0 1 ]
+miss_latency_ST: [binsize: 1 max: 95 count: 865 average: 23.8058 | standard deviation: 31.1488 | 0 0 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 27 63 122 1 2 4 0 3 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 6 30 0 0 1 ]
+miss_latency_IFETCH: [binsize: 1 max: 123 count: 6400 average: 10.2573 | standard deviation: 20.4119 | 0 0 0 5670 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 5 179 248 201 8 1 1 3 9 6 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 27 18 10 1 1 0 3 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
+miss_latency_L1Cache: [binsize: 1 max: 3 count: 6718 average: 3 | standard deviation: 0 | 0 0 0 6718 ]
+miss_latency_Directory: [binsize: 1 max: 123 count: 1730 average: 66.6191 | standard deviation: 7.72578 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 14 10 309 629 543 10 7 7 7 24 22 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 42 37 51 2 1 1 3 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -47,14 +47,14 @@ imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
-miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 1729
-miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average: 3 | standard deviation: 0 | 0 0 0 458 ]
-miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 456 average: 3 | standard deviation: 0 | 0 0 0 456 ]
+miss_latency_LD_Directory: [binsize: 1 max: 98 count: 727 average: 65.7469 | standard deviation: 6.09023 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 9 4 103 318 220 1 4 2 4 12 9 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 10 13 11 1 0 0 0 0 1 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average: 3 | standard deviation: 0 | 0 0 0 592 ]
-miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 1 max: 95 count: 273 average: 68.9231 | standard deviation: 9.83653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 27 63 122 1 2 4 0 3 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 6 30 0 0 1 ]
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5670 average: 3 | standard deviation: 0 | 0 0 0 5670 ]
+miss_latency_IFETCH_Directory: [binsize: 1 max: 123 count: 730 average: 66.626 | standard deviation: 8.11043 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 5 179 248 201 8 1 1 3 9 6 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 27 18 10 1 1 0 3 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -86,11 +86,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 13155
+page_reclaims: 9931
page_faults: 0
swaps: 0
block_inputs: 0
-block_outputs: 0
+block_outputs: 80
Network Stats
-------------
@@ -103,9 +103,9 @@ total_msgs: 20736 total_bytes: 829440
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 2.52117
- links_utilized_percent_switch_0_link_0: 2.5235 bw: 16000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 2.51884 bw: 16000 base_latency: 1
+links_utilized_percent_switch_0: 6.00613
+ links_utilized_percent_switch_0_link_0: 6.01169 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 6.00057 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
@@ -114,9 +114,9 @@ links_utilized_percent_switch_0: 2.52117
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 2.52117
- links_utilized_percent_switch_1_link_0: 2.51884 bw: 16000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 2.5235 bw: 16000 base_latency: 1
+links_utilized_percent_switch_1: 6.00613
+ links_utilized_percent_switch_1_link_0: 6.00057 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 6.01169 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
@@ -125,9 +125,9 @@ links_utilized_percent_switch_1: 2.52117
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 2.52117
- links_utilized_percent_switch_2_link_0: 2.5235 bw: 16000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 2.51884 bw: 16000 base_latency: 1
+links_utilized_percent_switch_2: 6.00613
+ links_utilized_percent_switch_2_link_0: 6.01169 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 6.00057 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
@@ -149,8 +149,8 @@ Cache Stats: system.l1_cntrl0.cacheMemory
--- L1Cache ---
- Event Counts -
-Load [1185 ] 1185
-Ifetch [6414 ] 6414
+Load [1183 ] 1183
+Ifetch [6400 ] 6400
Store [865 ] 865
Data [1730 ] 1730
Fwd_GETX [0 ] 0
@@ -168,8 +168,8 @@ I Replacement [0 ] 0
II Writeback_Nack [0 ] 0
-M Load [458 ] 458
-M Ifetch [5684 ] 5684
+M Load [456 ] 456
+M Ifetch [5670 ] 5670
M Store [592 ] 592
M Fwd_GETX [0 ] 0
M Inv [0 ] 0
@@ -190,19 +190,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 3456
memory_reads: 1730
memory_writes: 1726
- memory_refreshes: 714
- memory_total_request_delays: 4411
- memory_delays_per_request: 1.27633
- memory_delays_in_input_queue: 1083
- memory_delays_behind_head_of_bank_queue: 8
- memory_delays_stalled_at_head_of_bank_queue: 3320
- memory_stalls_for_bank_busy: 1509
+ memory_refreshes: 999
+ memory_total_request_delays: 3048
+ memory_delays_per_request: 0.881944
+ memory_delays_in_input_queue: 0
+ memory_delays_behind_head_of_bank_queue: 11
+ memory_delays_stalled_at_head_of_bank_queue: 3037
+ memory_stalls_for_bank_busy: 1500
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 99
- memory_stalls_for_bus: 1677
+ memory_stalls_for_arbitration: 107
+ memory_stalls_for_bus: 1375
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 35
+ memory_stalls_for_read_write_turnaround: 55
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index d2962a54f..c7e4dff49 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 16:51:51
-gem5 started Aug 13 2012 17:17:12
-gem5 executing on zizzer
+gem5 compiled Sep 1 2012 13:41:29
+gem5 started Sep 1 2012 13:43:15
+gem5 executing on doudou.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 342698 because target called exit()
+Exiting @ tick 143853 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index 5041c7f6a..c15797da9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000343 # Number of seconds simulated
-sim_ticks 342698 # Number of ticks simulated
-final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000144 # Number of seconds simulated
+sim_ticks 143853 # Number of ticks simulated
+final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 30637 # Simulator instruction rate (inst/s)
-host_op_rate 30634 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1642762 # Simulator tick rate (ticks/s)
-host_mem_usage 233644 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 43143 # Simulator instruction rate (inst/s)
+host_op_rate 43136 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 970941 # Simulator tick rate (ticks/s)
+host_mem_usage 264900 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
@@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 1183 # Nu
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 74701341 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 25643570 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 100344910 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 74701341 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 74701341 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 19539069 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 19539069 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 74701341 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 45182639 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 119883979 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 177959445 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 61090141 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 239049585 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 177959445 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 177959445 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 46547517 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 46547517 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 177959445 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 107637658 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 285597103 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads
@@ -72,7 +72,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 342698 # number of cpu cycles simulated
+system.cpu.numCycles 143853 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
@@ -91,7 +91,7 @@ system.cpu.num_mem_refs 2058 # nu
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 342698 # Number of busy cycles
+system.cpu.num_busy_cycles 143853 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles