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authorAndreas Sandberg <andreas.sandberg@arm.com>2016-06-06 17:16:44 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2016-06-06 17:16:44 +0100
commit85997e66a08b71d701e5b41462d1cfd42660b0c7 (patch)
treebc242f1a2bfc3a92b18da04805d9ebd8864b5320 /tests/quick/se/00.hello/ref/alpha/linux
parent21b66f45422bc449d4a8b86ab452d6b6ae5838bf (diff)
downloadgem5-85997e66a08b71d701e5b41462d1cfd42660b0c7.tar.xz
stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux')
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt21
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt21
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt24
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt24
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt24
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt22
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt22
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt19
9 files changed, 146 insertions, 43 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index 6544ab634..7fa71daaa 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000037 # Nu
sim_ticks 37494000 # Number of ticks simulated
final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 176621 # Simulator instruction rate (inst/s)
-host_op_rate 176529 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1031613588 # Simulator tick rate (ticks/s)
-host_mem_usage 248004 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 200557 # Simulator instruction rate (inst/s)
+host_op_rate 200498 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1171902214 # Simulator tick rate (ticks/s)
+host_mem_usage 294520 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 6413 # Number of instructions simulated
sim_ops 6413 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory
system.physmem.bytes_read::total 34048 # Number of bytes read from this memory
@@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 1040000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 28986000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 2009 # Number of BP lookups
system.cpu.branchPred.condPredicted 1241 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
@@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 37494000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 74988 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -343,6 +346,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class_0::total 6413 # Class of committed instruction
system.cpu.tickCycles 12653 # Number of cycles that the object actually ticked
system.cpu.idleCycles 62335 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 104.135823 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1980 # Total number of references to valid blocks.
@@ -358,6 +362,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 147
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4583 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4583 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1240 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1240 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
@@ -452,6 +457,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks.
@@ -467,6 +473,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 258
system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 5738 # Number of tag accesses
system.cpu.icache.tags.data_accesses 5738 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 2323 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2323 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2323 # number of demand (read+write) hits
@@ -533,6 +540,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780
system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
@@ -550,6 +558,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 337
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@@ -676,6 +685,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
@@ -705,6 +715,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 546000 # La
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 459 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index ead74abf4..8d95bb8b7 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000022 # Nu
sim_ticks 22019000 # Number of ticks simulated
final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 115969 # Simulator instruction rate (inst/s)
-host_op_rate 115940 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 399737091 # Simulator tick rate (ticks/s)
-host_mem_usage 249288 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 117755 # Simulator instruction rate (inst/s)
+host_op_rate 117735 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 405950936 # Simulator tick rate (ticks/s)
+host_mem_usage 294524 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 6385 # Number of instructions simulated
sim_ops 6385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
system.physmem.bytes_read::total 31040 # Number of bytes read from this memory
@@ -249,6 +250,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14308250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 2849 # Number of BP lookups
system.cpu.branchPred.condPredicted 1676 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect
@@ -296,6 +298,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 22019000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 44039 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -587,6 +590,7 @@ system.cpu.fp_regfile_reads 8 # nu
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 109.409218 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2405 # Total number of references to valid blocks.
@@ -602,6 +606,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 129
system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
@@ -696,6 +701,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503
system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks.
@@ -711,6 +717,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 174
system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4899 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4899 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1836 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1836 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1836 # number of demand (read+write) hits
@@ -783,6 +790,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182
system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
@@ -800,6 +808,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012604 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@@ -926,6 +935,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
@@ -955,6 +965,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 469500 # La
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 413 # Transaction distribution
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 9a58520d3..281db070e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu
sim_ticks 3214500 # Number of ticks simulated
final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1011674 # Simulator instruction rate (inst/s)
-host_op_rate 1009913 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 506215370 # Simulator tick rate (ticks/s)
-host_mem_usage 237756 # Number of bytes of host memory used
+host_inst_rate 879431 # Simulator instruction rate (inst/s)
+host_op_rate 878309 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 440397606 # Simulator tick rate (ticks/s)
+host_mem_usage 282472 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 25652 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34456 # Number of bytes read from this memory
@@ -35,6 +36,7 @@ system.physmem.bw_write::total 2083061129 # Wr
system.physmem.bw_total::cpu.inst 7980090216 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4821900762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12801990978 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 3214500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 6430 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 7598 # Transaction distribution
system.membus.trans_dist::ReadResp 7598 # Transaction distribution
system.membus.trans_dist::WriteReq 865 # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
index e07863c49..d17f0dc2a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000122 # Nu
sim_ticks 121535 # Number of ticks simulated
final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 71837 # Simulator instruction rate (inst/s)
-host_op_rate 71828 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1363198 # Simulator tick rate (ticks/s)
-host_mem_usage 407704 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 67126 # Simulator instruction rate (inst/s)
+host_op_rate 67120 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1273887 # Simulator tick rate (ticks/s)
+host_mem_usage 453732 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory
@@ -265,6 +266,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3900 # Ti
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 111353 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -299,6 +301,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 121535 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 121535 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -358,6 +361,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 9652 # delay histogram for all message
@@ -395,6 +399,7 @@ system.ruby.miss_latency_hist_seqr::gmean 66.961050
system.ruby.miss_latency_hist_seqr::stdev 30.103565
system.ruby.miss_latency_hist_seqr | 331 22.20% 22.20% | 1141 76.53% 98.73% | 4 0.27% 98.99% | 1 0.07% 99.06% | 8 0.54% 99.60% | 6 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1491
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
@@ -410,10 +415,14 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 4.310281
system.ruby.network.routers0.msg_count.Control::0 1491
system.ruby.network.routers0.msg_count.Request_Control::2 1041
@@ -431,6 +440,7 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6400
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 8.369194
system.ruby.network.routers1.msg_count.Control::0 2952
system.ruby.network.routers1.msg_count.Request_Control::2 1041
@@ -448,6 +458,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6400
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 4.058913
system.ruby.network.routers2.msg_count.Control::0 1461
system.ruby.network.routers2.msg_count.Response_Data::1 1738
@@ -455,6 +466,7 @@ system.ruby.network.routers2.msg_count.Response_Control::1 2629
system.ruby.network.routers2.msg_bytes.Control::0 11688
system.ruby.network.routers2.msg_bytes.Response_Data::1 125136
system.ruby.network.routers2.msg_bytes.Response_Control::1 21032
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 5.579463
system.ruby.network.routers3.msg_count.Control::0 2952
system.ruby.network.routers3.msg_count.Request_Control::2 1041
@@ -472,6 +484,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 6400
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 8856
system.ruby.network.msg_count.Request_Control 3123
system.ruby.network.msg_count.Response_Data 9687
@@ -484,6 +497,7 @@ system.ruby.network.msg_byte.Response_Data 697464
system.ruby.network.msg_byte.Response_Control 114384
system.ruby.network.msg_byte.Writeback_Data 61776
system.ruby.network.msg_byte.Writeback_Control 7008
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 6.128687
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1491
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 86b91c7c5..99bf8d33d 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000109 # Nu
sim_ticks 108878 # Number of ticks simulated
final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 68389 # Simulator instruction rate (inst/s)
-host_op_rate 68380 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1162621 # Simulator tick rate (ticks/s)
-host_mem_usage 413676 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 66441 # Simulator instruction rate (inst/s)
+host_op_rate 66435 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1129573 # Simulator tick rate (ticks/s)
+host_mem_usage 461124 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory
@@ -265,6 +266,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3380 # Ti
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 96382 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -299,6 +301,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 108878 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 108878 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -358,6 +361,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8464
@@ -388,16 +392,21 @@ system.ruby.miss_latency_hist_seqr::gmean 57.123275
system.ruby.miss_latency_hist_seqr::stdev 33.791401
system.ruby.miss_latency_hist_seqr | 412 28.97% 28.97% | 995 69.97% 98.95% | 2 0.14% 99.09% | 0 0.00% 99.09% | 9 0.63% 99.72% | 4 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1422
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 6.929545
system.ruby.network.routers0.msg_count.Request_Control::0 1422
system.ruby.network.routers0.msg_count.Response_Data::2 1183
@@ -411,6 +420,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 10.407520
system.ruby.network.routers1.msg_count.Request_Control::0 1422
system.ruby.network.routers1.msg_count.Request_Control::1 1183
@@ -428,6 +438,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108216
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 3.477975
system.ruby.network.routers2.msg_count.Request_Control::1 1183
system.ruby.network.routers2.msg_count.Response_Data::2 1183
@@ -439,6 +450,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 85176
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 6.938347
system.ruby.network.routers3.msg_count.Request_Control::0 1422
system.ruby.network.routers3.msg_count.Request_Control::1 1183
@@ -456,6 +468,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108216
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 7815
system.ruby.network.msg_count.Response_Data 7098
system.ruby.network.msg_count.ResponseL2hit_Data 717
@@ -468,6 +481,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624
system.ruby.network.msg_byte.Writeback_Data 324648
system.ruby.network.msg_byte.Writeback_Control 74352
system.ruby.network.msg_byte.Unblock_Control 63624
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 6.499476
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index bdd21635f..e5f292184 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000108 # Nu
sim_ticks 108253 # Number of ticks simulated
final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 4411 # Simulator instruction rate (inst/s)
-host_op_rate 4411 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 74577 # Simulator tick rate (ticks/s)
-host_mem_usage 409256 # Number of bytes of host memory used
-host_seconds 1.45 # Real time elapsed on the host
+host_inst_rate 94410 # Simulator instruction rate (inst/s)
+host_op_rate 94397 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1595747 # Simulator tick rate (ticks/s)
+host_mem_usage 455808 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory
@@ -264,6 +265,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3380 # Ti
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 95729 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -298,6 +300,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 108253 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 108253 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -357,6 +360,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8464
@@ -389,16 +393,21 @@ system.ruby.miss_latency_hist_seqr::stdev 28.099799
system.ruby.miss_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1179
system.ruby.Directory.incomplete_times_seqr 1178
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 6.022466
system.ruby.network.routers0.msg_count.Request_Control::1 1383
system.ruby.network.routers0.msg_count.Response_Data::4 1179
@@ -412,6 +421,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 416
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 4.541676
system.ruby.network.routers1.msg_count.Request_Control::1 1383
system.ruby.network.routers1.msg_count.Request_Control::2 1196
@@ -427,6 +437,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 208
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 3.432237
system.ruby.network.routers2.msg_count.Request_Control::2 1196
system.ruby.network.routers2.msg_count.Response_Data::4 1179
@@ -438,6 +449,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 84888
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 208
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 4.665460
system.ruby.network.routers3.msg_count.Request_Control::1 1383
system.ruby.network.routers3.msg_count.Request_Control::2 1196
@@ -455,6 +467,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4 8
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 114048
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers3.msg_bytes.Persistent_Control::3 416
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 7737
system.ruby.network.msg_count.Response_Data 3537
system.ruby.network.msg_count.ResponseL2hit_Data 612
@@ -469,6 +482,7 @@ system.ruby.network.msg_byte.Response_Control 24
system.ruby.network.msg_byte.Writeback_Data 342144
system.ruby.network.msg_byte.Writeback_Control 23232
system.ruby.network.msg_byte.Persistent_Control 1248
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 5.761503
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1179
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 463ba3cfb..9d52394d3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000087 # Nu
sim_ticks 86770 # Number of ticks simulated
final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 99240 # Simulator instruction rate (inst/s)
-host_op_rate 99218 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1344283 # Simulator tick rate (ticks/s)
-host_mem_usage 407932 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 95809 # Simulator instruction rate (inst/s)
+host_op_rate 95795 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1297998 # Simulator tick rate (ticks/s)
+host_mem_usage 453692 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory
@@ -264,6 +265,7 @@ system.mem_ctrls_1.memoryStateTime::REF 2860 # Ti
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 82150 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -298,6 +300,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 86770 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 86770 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -357,6 +360,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8464
@@ -392,6 +396,7 @@ system.ruby.Directory.incomplete_times_seqr 1159
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
@@ -401,8 +406,11 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 5.172295
system.ruby.network.routers0.msg_count.Request_Control::2 1160
system.ruby.network.routers0.msg_count.Response_Data::4 1160
@@ -418,6 +426,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9280
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 5.172006
system.ruby.network.routers1.msg_count.Request_Control::2 1160
system.ruby.network.routers1.msg_count.Response_Data::4 1160
@@ -433,6 +442,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 5.172295
system.ruby.network.routers2.msg_count.Request_Control::2 1160
system.ruby.network.routers2.msg_count.Response_Data::4 1160
@@ -448,6 +458,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9280
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 3480
system.ruby.network.msg_count.Response_Data 3480
system.ruby.network.msg_count.Writeback_Data 660
@@ -458,6 +469,7 @@ system.ruby.network.msg_byte.Response_Data 250560
system.ruby.network.msg_byte.Writeback_Data 47520
system.ruby.network.msg_byte.Writeback_Control 77088
system.ruby.network.msg_byte.Unblock_Control 27832
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 6.675118
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1160
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1144
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index d5526ad82..a33abfe97 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000107 # Nu
sim_ticks 107065 # Number of ticks simulated
final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 109103 # Simulator instruction rate (inst/s)
-host_op_rate 109072 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1823360 # Simulator tick rate (ticks/s)
-host_mem_usage 411068 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 58028 # Simulator instruction rate (inst/s)
+host_op_rate 58023 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 970128 # Simulator tick rate (ticks/s)
+host_mem_usage 456600 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory
@@ -267,6 +268,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3380 # Ti
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 92641 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -301,6 +303,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 107065 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 107065 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -360,6 +363,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 3458 # delay histogram for all message
@@ -396,10 +400,14 @@ system.ruby.miss_latency_hist_seqr::stdev 32.911544
system.ruby.miss_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1731
system.ruby.Directory.incomplete_times_seqr 1730
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 8.074534
system.ruby.network.routers0.msg_count.Control::2 1731
system.ruby.network.routers0.msg_count.Data::2 1727
@@ -409,6 +417,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 13848
system.ruby.network.routers0.msg_bytes.Data::2 124344
system.ruby.network.routers0.msg_bytes.Response_Data::4 124632
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 8.074534
system.ruby.network.routers1.msg_count.Control::2 1731
system.ruby.network.routers1.msg_count.Data::2 1727
@@ -418,6 +427,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 13848
system.ruby.network.routers1.msg_bytes.Data::2 124344
system.ruby.network.routers1.msg_bytes.Response_Data::4 124632
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 8.074534
system.ruby.network.routers2.msg_count.Control::2 1731
system.ruby.network.routers2.msg_count.Data::2 1727
@@ -427,6 +437,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 13848
system.ruby.network.routers2.msg_bytes.Data::2 124344
system.ruby.network.routers2.msg_bytes.Response_Data::4 124632
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 5193
system.ruby.network.msg_count.Data 5181
system.ruby.network.msg_count.Response_Data 5193
@@ -435,6 +446,7 @@ system.ruby.network.msg_byte.Control 41544
system.ruby.network.msg_byte.Data 373032
system.ruby.network.msg_byte.Response_Data 373896
system.ruby.network.msg_byte.Writeback_Control 41448
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 8.082006
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 4c1b7f48d..0b95c7449 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000036 # Nu
sim_ticks 35682500 # Number of ticks simulated
final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 581025 # Simulator instruction rate (inst/s)
-host_op_rate 580437 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3231677275 # Simulator tick rate (ticks/s)
-host_mem_usage 247496 # Number of bytes of host memory used
+host_inst_rate 516760 # Simulator instruction rate (inst/s)
+host_op_rate 516348 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2875227341 # Simulator tick rate (ticks/s)
+host_mem_usage 291440 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
@@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 498619772 # In
system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -63,6 +65,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 35682500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 71365 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -121,6 +124,7 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks.
@@ -136,6 +140,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 143
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
@@ -222,6 +227,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks.
@@ -237,6 +243,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 184
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13107 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits
@@ -303,6 +310,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104
system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
@@ -320,6 +328,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@@ -446,6 +455,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
@@ -475,6 +485,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La
system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 373 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution