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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-07-19 19:04:58 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-07-19 19:04:58 -0700 |
| commit | 040fa23d01109c68d194d2517df777844e4e2f13 (patch) | |
| tree | 822b7da72458db435480c20c1a3448f6158c62aa /tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout | |
| parent | 06bb6a473157a204bb7e77ea28e618aa08d2d811 (diff) | |
| download | gem5-040fa23d01109c68d194d2517df777844e4e2f13.tar.xz | |
stats: update for syscall DPRINTF change
Only printing one rather than two args for the ignored syscall
warning means the count of register accesses has changed on
a few runs. Oddly only Alpha Tru64 seems to have any ignored
syscalls in the regression tests.
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout')
| -rwxr-xr-x | tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 757b668d6..f39993dfb 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 10:36:29 -gem5 started Jun 21 2014 10:38:16 +gem5 compiled Jul 19 2014 12:27:06 +gem5 started Jul 19 2014 12:27:28 gem5 executing on phenom command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second |