stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.

1 files changed, 91 insertions, 74 deletions

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index a87953c0f..286f63d05 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    11765500                       # Number of ticks simulated
 final_tick                                   11765500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  45706                       # Simulator instruction rate (inst/s)
-host_op_rate                                    45696                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              225189511                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236100                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  81487                       # Simulator instruction rate (inst/s)
+host_op_rate                                    81445                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              401265305                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 288836                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895            1      2.56%     82.05% # By
 system.physmem.bytesPerActivate::896-1023            1      2.56%     84.62% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            6     15.38%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             39                       # Bytes accessed per row activation
-system.physmem.totQLat                        1710500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   6810500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        1802000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   6902000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1360000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6288.60                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6625.00                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25038.60                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25375.00                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                        1479.58                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                     1479.58                       # Average system read bandwidth in MiByte/s
@@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF            260000                       # Ti
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
 system.physmem.memoryStateTime::ACT           7778000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.membus.throughput                   1479580128                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 248                       # Transaction distribution
 system.membus.trans_dist::ReadResp                248                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                24                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               24                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          544                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    544                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        17408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               17408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  17408                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        17408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   17408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               272                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     272    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 272                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              339500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            2545000                       # Layer occupancy (ticks)
@@ -577,7 +585,6 @@ system.cpu.int_regfile_writes                    2774                       # nu
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1479580128                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            248                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           248                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           24                       # Transaction distribution
@@ -585,11 +592,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp           24                       # T
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          374                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total               544                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        11968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          17408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             17408                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        11968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              17408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          272                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                272    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            272                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         136000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        314250                       # Layer occupancy (ticks)
@@ -717,14 +734,14 @@ system.cpu.l2cache.overall_misses::total          272                       # nu
 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12706250                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4451500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total     17157750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1692250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1692250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1694250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1694250                       # number of ReadExReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     12706250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6143750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     18850000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6145750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     18852000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     12706250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6143750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     18850000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6145750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     18852000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          187                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           61                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          248                       # number of ReadReq accesses(hits+misses)
@@ -750,14 +767,14 @@ system.cpu.l2cache.overall_miss_rate::total            1                       #
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70510.416667                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70510.416667                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70593.750000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70593.750000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72279.411765                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69301.470588                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72302.941176                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69308.823529                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72279.411765                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69301.470588                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72302.941176                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69308.823529                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -780,14 +797,14 @@ system.cpu.l2cache.overall_mshr_misses::total          272
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10348750                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3702000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14050750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1398750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1398750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1400750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1400750                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10348750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5100750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     15449500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5102750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15451500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10348750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5100750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     15449500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5102750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15451500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -802,22 +819,22 @@ system.cpu.l2cache.overall_mshr_miss_rate::total            1
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.250000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.250000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58364.583333                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58364.583333                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60008.823529                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56799.632353                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60032.352941                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56806.985294                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60008.823529                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56799.632353                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            46.118379                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            46.118209                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                 729                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              8.576471                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    46.118379                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data    46.118209                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.011259                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.011259                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
@@ -842,14 +859,14 @@ system.cpu.dcache.demand_misses::cpu.data          198                       # n
 system.cpu.dcache.demand_misses::total            198                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          198                       # number of overall misses
 system.cpu.dcache.overall_misses::total           198                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7443000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7443000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5304000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5304000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     12747000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     12747000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     12747000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     12747000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7447000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7447000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5312000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5312000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     12759000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     12759000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     12759000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     12759000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          633                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          633                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
@@ -866,14 +883,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.213592
 system.cpu.dcache.demand_miss_rate::total     0.213592                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.213592                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.213592                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63615.384615                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63615.384615                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65481.481481                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65481.481481                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64378.787879                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64378.787879                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64378.787879                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64378.787879                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64439.393939                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64439.393939                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          131                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
@@ -900,12 +917,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data           85
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4512500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      4512500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1717750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1717750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6230250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6230250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6230250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6230250                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1719750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1719750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6232250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6232250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6232250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6232250                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.096367                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.096367                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
@@ -916,12 +933,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091694
 system.cpu.dcache.overall_mshr_miss_rate::total     0.091694                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71572.916667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71572.916667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73297.058824                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73297.058824                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73297.058824                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73297.058824                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------