diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 467 |
1 files changed, 253 insertions, 214 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 88231a1ee..5be5fa9ed 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12006500 # Number of ticks simulated -final_tick 12006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11975500 # Number of ticks simulated +final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60243 # Simulator instruction rate (inst/s) -host_op_rate 60220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 302796832 # Simulator tick rate (ticks/s) -host_mem_usage 264400 # Number of bytes of host memory used +host_inst_rate 56599 # Simulator instruction rate (inst/s) +host_op_rate 56579 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 283759448 # Simulator tick rate (ticks/s) +host_mem_usage 265424 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1002123850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 453087911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1455211760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1002123850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1002123850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1002123850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 453087911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1455211760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1004717966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 454260782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1458978748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1004717966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1004717966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1004717966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 454260782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1458978748 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 273 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11917000 # Total gap between requests +system.physmem.totGap 11886000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,33 +186,33 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 24 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 464 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 290.487911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.347726 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4 16.67% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 12.50% 54.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 4.17% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 8.33% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 8.33% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 25.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 24 # Bytes accessed per row activation -system.physmem.totQLat 1638000 # Total ticks spent queuing -system.physmem.totMemAccLat 7265500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 38 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.368421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.223359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 366.580725 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14 36.84% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 13.16% 50.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 10.53% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 5.26% 65.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 5.26% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 5.26% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 5.26% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 2.63% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 15.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38 # Bytes accessed per row activation +system.physmem.totQLat 2067500 # Total ticks spent queuing +system.physmem.totMemAccLat 7186250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers -system.physmem.totBankLat 4262500 # Total ticks spent accessing banks -system.physmem.avgQLat 6000.00 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15613.55 # Average bank access latency per DRAM burst +system.physmem.avgQLat 7573.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26613.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1455.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26323.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1458.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1455.21 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1458.98 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.37 # Data bus utilization in percentage -system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.40 # Data bus utilization in percentage +system.physmem.busUtilRead 11.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,10 +220,14 @@ system.physmem.readRowHits 225 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43652.01 # Average gap between requests +system.physmem.avgGap 43538.46 # Average gap between requests system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1455211760 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem.memoryStateTime::REF 260000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 7796750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1458978748 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 249 # Transaction distribution system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution @@ -234,9 +238,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 344500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2552500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2556250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1176 # Number of BP lookups @@ -281,42 +285,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 24014 # number of cpu cycles simulated +system.cpu.numCycles 23952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 4342 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 531 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.907925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.314691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.909929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.316850 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6513 84.34% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 176 2.28% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 76 0.98% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.83% 91.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.84% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6496 84.31% 84.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.69% 85.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.49% 86.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.23% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 2.28% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 76 0.99% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.83% 91.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.84% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.048971 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.291955 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5487 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 7705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.292710 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5480 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 569 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1153 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing @@ -325,9 +329,9 @@ system.cpu.decode.BranchMispred 81 # Nu system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5585 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 5578 # Number of cycles rename is idle system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1063 # Number of cycles rename is running system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 5900 # Number of instructions processed by rename @@ -354,23 +358,23 @@ system.cpu.iq.iqSquashedInstsIssued 54 # Nu system.cpu.iq.iqSquashedInstsExamined 2341 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 1389 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7722 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.523828 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.238657 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.524984 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.239779 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6098 78.97% 78.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 565 7.32% 86.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 401 5.19% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.41% 94.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 200 2.59% 97.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 120 1.55% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6081 78.92% 78.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 565 7.33% 86.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 401 5.20% 91.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 263 3.41% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 200 2.60% 97.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 120 1.56% 99.03% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7705 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available @@ -440,10 +444,10 @@ system.cpu.iq.FU_type_0::MemWrite 395 9.77% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 4045 # Type of FU issued -system.cpu.iq.rate 0.168443 # Inst issue rate +system.cpu.iq.rate 0.168879 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010878 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15897 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 15880 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 7311 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3652 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads @@ -484,26 +488,26 @@ system.cpu.iew.exec_nop 336 # nu system.cpu.iew.exec_refs 1130 # number of memory reference insts executed system.cpu.iew.exec_branches 644 # Number of branches executed system.cpu.iew.exec_stores 388 # Number of stores executed -system.cpu.iew.exec_rate 0.160531 # Inst execution rate +system.cpu.iew.exec_rate 0.160947 # Inst execution rate system.cpu.iew.wb_sent 3738 # cumulative count of insts sent to commit system.cpu.iew.wb_count 3658 # cumulative count of insts written-back system.cpu.iew.wb_producers 1710 # num instructions producing a value system.cpu.iew.wb_consumers 2211 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152328 # insts written-back per cycle +system.cpu.iew.wb_rate 0.152722 # insts written-back per cycle system.cpu.iew.wb_fanout 0.773406 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 2726 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7228 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.356392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.198445 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 7211 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.357232 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199732 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6359 87.98% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6342 87.95% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.83% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.27% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.58% 96.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle @@ -512,7 +516,7 @@ system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7228 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7211 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -523,25 +527,60 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 2576 # Class of committed instruction system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12220 # The number of ROB reads +system.cpu.rob.rob_reads 12203 # The number of ROB reads system.cpu.rob.rob_writes 11111 # The number of ROB writes -system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16292 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16247 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 10.060327 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.060327 # CPI: Total CPI of All Threads -system.cpu.ipc 0.099400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.099400 # IPC: Total IPC of All Threads +system.cpu.cpi 10.034353 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 4672 # number of integer regfile reads system.cpu.int_regfile_writes 2825 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1455211760 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1458978748 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -556,19 +595,19 @@ system.cpu.toL2Bus.data_through_bus 17472 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 315500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 316750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 133500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 93.163170 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 93.052511 # Cycle average of tags in use system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 93.163170 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.045490 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.045490 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 93.052511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.045436 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.045436 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id @@ -587,12 +626,12 @@ system.cpu.icache.demand_misses::cpu.inst 250 # n system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17591499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17591499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17591499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17591499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17591499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17591499 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17506249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17506249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17506249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17506249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17506249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17506249 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses @@ -605,12 +644,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70365.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70365.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70365.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70365.996000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70024.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70024.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70024.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70024.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -631,36 +670,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 188 system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13162249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13162249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13162249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13110499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13110499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13110499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13110499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13110499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13110499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70011.962766 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70011.962766 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69736.696809 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69736.696809 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 122.028433 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 121.888429 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.360563 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.667870 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002849 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003720 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 249 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -678,17 +717,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12973500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4680750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17654250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1693750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1693750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12973500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6374500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19348000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12973500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6374500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19348000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12921750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17574250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1688000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1688000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12921750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6340500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19262250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12921750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6340500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19262250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -711,17 +750,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69007.978723 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76733.606557 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70900.602410 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70572.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70572.916667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70871.794872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70871.794872 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68732.712766 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76270.491803 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70579.317269 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70557.692308 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70557.692308 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,17 +780,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10603500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3934250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14537750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1399750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1399750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10603500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5334000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15937500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10603500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5334000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15937500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14452750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1393500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1393500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5298500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5298500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15846250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -763,30 +802,30 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56401.595745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64495.901639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58384.538153 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58322.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58322.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56105.053191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64016.393443 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58043.172691 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58062.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58062.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.630537 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.583444 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 759 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.929412 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.630537 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011140 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011140 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.583444 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011129 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011129 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1995 # Number of data accesses @@ -806,14 +845,14 @@ system.cpu.dcache.demand_misses::cpu.data 196 # n system.cpu.dcache.demand_misses::total 196 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 196 # number of overall misses system.cpu.dcache.overall_misses::total 196 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7964000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5323250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5323250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13287250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13287250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13287250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13287250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7876750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7876750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5302250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5302250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13179000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13179000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13179000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13179000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -830,14 +869,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.205236 system.cpu.dcache.demand_miss_rate::total 0.205236 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.205236 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.205236 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69252.173913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69252.173913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65719.135802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65719.135802 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67792.091837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67792.091837 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65459.876543 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67239.795918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67239.795918 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -862,14 +901,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6461000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6461000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6427000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6427000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6427000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6427000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -878,14 +917,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089005 system.cpu.dcache.demand_mshr_miss_rate::total 0.089005 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.089005 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77733.606557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77733.606557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71635.416667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71635.416667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77270.491803 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77270.491803 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |