diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-12-11 10:06:01 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-12-11 10:06:01 -0600 |
commit | 141ee3879459eea62d6176119fbc2c432a5fb124 (patch) | |
tree | 495c71e7c8b3e8b726d5111277ef5b99377b35a7 /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini | |
parent | f3d0be210f889da927d921d21a6c27ba94fde746 (diff) | |
download | gem5-141ee3879459eea62d6176119fbc2c432a5fb124.tar.xz |
regressions: stats update due to stats from ruby prefetcher
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini')
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index 0b5dc966b..08d94aa42 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -107,7 +107,7 @@ version=0 [system.dir_cntrl0.directory] type=RubyDirectoryMemory map_levels=4 -numa_high_bit=6 +numa_high_bit=5 size=134217728 use_map=false version=0 @@ -136,15 +136,17 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=L1DcacheMemory L1IcacheMemory sequencer +children=L1DcacheMemory L1IcacheMemory prefetcher sequencer L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory buffer_size=0 cntrl_id=0 +enable_prefetch=false l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 +prefetcher=system.l1_cntrl0.prefetcher recycle_latency=10 ruby_system=system.ruby send_evictions=false @@ -172,7 +174,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 -is_icache=false +is_icache=true latency=3 replacement_policy=PSEUDO_LRU resourceStalls=false @@ -181,6 +183,16 @@ start_index_bit=6 tagAccessLatency=1 tagArrayBanks=1 +[system.l1_cntrl0.prefetcher] +type=Prefetcher +cross_page=false +nonunit_filter=8 +num_startup_pfs=1 +num_streams=4 +pf_per_stream=1 +train_misses=4 +unit_filter=8 + [system.l1_cntrl0.sequencer] type=RubySequencer access_phys_mem=true |