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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-06 21:57:10 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-06 21:57:10 -0600 |
| commit | d24d5446c5c96ad29bd6a690c7ba09cb8e3444e8 (patch) | |
| tree | f7ff9f21193905276d4639ed0ae931e9fc75e4ef /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini | |
| parent | c0618198908b592ff0c165b671cb5d8d785d83ca (diff) | |
| download | gem5-d24d5446c5c96ad29bd6a690c7ba09cb8e3444e8.tar.xz | |
regressions: stats updates due to no physmem in ruby
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index 918bf8974..02d1e74cd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -32,6 +32,7 @@ system_port=system.sys_port_proxy.slave[0] [system.cpu] type=TimingSimpleCPU children=dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clock=1 cpu_id=0 @@ -102,7 +103,7 @@ conf_table_reported=false in_addr_map=true latency=30 latency_var=0 -null=false +null=true range=0:134217727 zero=false @@ -225,7 +226,7 @@ unit_filter=8 [system.ruby.l1_cntrl0.sequencer] type=RubySequencer -access_phys_mem=true +access_phys_mem=false clock=1 dcache=system.ruby.l1_cntrl0.L1DcacheMemory deadlock_threshold=500000 |