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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-12-11 10:06:01 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-12-11 10:06:01 -0600 |
commit | 141ee3879459eea62d6176119fbc2c432a5fb124 (patch) | |
tree | 495c71e7c8b3e8b726d5111277ef5b99377b35a7 /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt | |
parent | f3d0be210f889da927d921d21a6c27ba94fde746 (diff) | |
download | gem5-141ee3879459eea62d6176119fbc2c432a5fb124.tar.xz |
regressions: stats update due to stats from ruby prefetcher
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt')
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index 84321c81e..381866200 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu sim_ticks 52575 # Number of ticks simulated final_tick 52575 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 27172 # Simulator instruction rate (inst/s) -host_op_rate 27165 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 554084 # Simulator tick rate (ticks/s) -host_mem_usage 263836 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 11415 # Simulator instruction rate (inst/s) +host_op_rate 11414 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 232838 # Simulator tick rate (ticks/s) +host_mem_usage 273512 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -45,6 +45,15 @@ system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed +system.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching +system.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made +system.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted +system.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped +system.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed +system.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched +system.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages +system.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads |