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authorNilay Vaish <nilay@cs.wisc.edu>2013-06-10 06:46:20 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2013-06-10 06:46:20 -0500
commit247e4e9ab41bafcfcbde725bb40e6a7b5628f1de (patch)
treeb4312f540772ef437b5b962cc1fff4bb54d90ce4 /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
parentd32ee94231251b8d07bb811142f6759f8655962b (diff)
downloadgem5-247e4e9ab41bafcfcbde725bb40e6a7b5628f1de.tar.xz
stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now. Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are also being updated.
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory')
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats476
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt97
2 files changed, 101 insertions, 472 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index e4af41b60..ff366244b 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Mar/06/2013 20:38:34
+Real time: Jun/08/2013 14:12:43
Profiler Stats
--------------
@@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.54
-Virtual_time_in_minutes: 0.009
-Virtual_time_in_hours: 0.00015
-Virtual_time_in_days: 6.25e-06
+Virtual_time_in_seconds: 0.48
+Virtual_time_in_minutes: 0.008
+Virtual_time_in_hours: 0.000133333
+Virtual_time_in_days: 5.55556e-06
Ruby_current_time: 52575
Ruby_start_time: 0
Ruby_cycles: 52575
-mbytes_resident: 53.8125
-mbytes_total: 145.805
-resident_ratio: 0.369126
-
-ruby_cycles_executed: [ 52576 ]
+mbytes_resident: 54.0742
+mbytes_total: 141.93
+resident_ratio: 0.381048
Busy Controller Counts:
L1Cache-0:0
@@ -61,7 +59,6 @@ Request vs. RubySystem State Profile
--------------------------------
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
@@ -82,7 +79,7 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11068
+page_reclaims: 11040
page_faults: 0
swaps: 0
block_inputs: 0
@@ -160,458 +157,3 @@ links_utilized_percent_switch_3: 4.8648
outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
- --- L1Cache ---
- - Event Counts -
-Load [415 ] 415
-Ifetch [2585 ] 2585
-Store [294 ] 294
-Inv [431 ] 431
-L1_Replacement [502 ] 502
-Fwd_GETX [0 ] 0
-Fwd_GETS [0 ] 0
-Fwd_GET_INSTR [0 ] 0
-Data [0 ] 0
-Data_Exclusive [204 ] 204
-DataS_fromL1 [0 ] 0
-Data_all_Acks [368 ] 368
-Ack [0 ] 0
-Ack_all [0 ] 0
-WB_Ack [124 ] 124
-PF_Load [0 ] 0
-PF_Ifetch [0 ] 0
-PF_Store [0 ] 0
-
- - Transitions -
-NP Load [182 ] 182
-NP Ifetch [270 ] 270
-NP Store [58 ] 58
-NP Inv [162 ] 162
-NP L1_Replacement [0 ] 0
-NP PF_Load [0 ] 0
-NP PF_Ifetch [0 ] 0
-NP PF_Store [0 ] 0
-
-I Load [22 ] 22
-I Ifetch [30 ] 30
-I Store [10 ] 10
-I Inv [0 ] 0
-I L1_Replacement [206 ] 206
-I PF_Load [0 ] 0
-I PF_Ifetch [0 ] 0
-I PF_Store [0 ] 0
-
-S Load [0 ] 0
-S Ifetch [2285 ] 2285
-S Store [0 ] 0
-S Inv [124 ] 124
-S L1_Replacement [172 ] 172
-S PF_Load [0 ] 0
-S PF_Store [0 ] 0
-
-E Load [140 ] 140
-E Ifetch [0 ] 0
-E Store [41 ] 41
-E Inv [83 ] 83
-E L1_Replacement [79 ] 79
-E Fwd_GETX [0 ] 0
-E Fwd_GETS [0 ] 0
-E Fwd_GET_INSTR [0 ] 0
-E PF_Load [0 ] 0
-E PF_Store [0 ] 0
-
-M Load [71 ] 71
-M Ifetch [0 ] 0
-M Store [185 ] 185
-M Inv [62 ] 62
-M L1_Replacement [45 ] 45
-M Fwd_GETX [0 ] 0
-M Fwd_GETS [0 ] 0
-M Fwd_GET_INSTR [0 ] 0
-M PF_Load [0 ] 0
-M PF_Store [0 ] 0
-
-IS Load [0 ] 0
-IS Ifetch [0 ] 0
-IS Store [0 ] 0
-IS Inv [0 ] 0
-IS L1_Replacement [0 ] 0
-IS Data_Exclusive [204 ] 204
-IS DataS_fromL1 [0 ] 0
-IS Data_all_Acks [300 ] 300
-IS PF_Load [0 ] 0
-IS PF_Store [0 ] 0
-
-IM Load [0 ] 0
-IM Ifetch [0 ] 0
-IM Store [0 ] 0
-IM Inv [0 ] 0
-IM L1_Replacement [0 ] 0
-IM Data [0 ] 0
-IM Data_all_Acks [68 ] 68
-IM Ack [0 ] 0
-IM PF_Load [0 ] 0
-IM PF_Store [0 ] 0
-
-SM Load [0 ] 0
-SM Ifetch [0 ] 0
-SM Store [0 ] 0
-SM Inv [0 ] 0
-SM L1_Replacement [0 ] 0
-SM Ack [0 ] 0
-SM Ack_all [0 ] 0
-SM PF_Load [0 ] 0
-SM PF_Store [0 ] 0
-
-IS_I Load [0 ] 0
-IS_I Ifetch [0 ] 0
-IS_I Store [0 ] 0
-IS_I Inv [0 ] 0
-IS_I L1_Replacement [0 ] 0
-IS_I Data_Exclusive [0 ] 0
-IS_I DataS_fromL1 [0 ] 0
-IS_I Data_all_Acks [0 ] 0
-IS_I PF_Load [0 ] 0
-IS_I PF_Store [0 ] 0
-
-M_I Load [0 ] 0
-M_I Ifetch [0 ] 0
-M_I Store [0 ] 0
-M_I Inv [0 ] 0
-M_I L1_Replacement [0 ] 0
-M_I Fwd_GETX [0 ] 0
-M_I Fwd_GETS [0 ] 0
-M_I Fwd_GET_INSTR [0 ] 0
-M_I WB_Ack [124 ] 124
-M_I PF_Load [0 ] 0
-M_I PF_Store [0 ] 0
-
-SINK_WB_ACK Load [0 ] 0
-SINK_WB_ACK Ifetch [0 ] 0
-SINK_WB_ACK Store [0 ] 0
-SINK_WB_ACK Inv [0 ] 0
-SINK_WB_ACK L1_Replacement [0 ] 0
-SINK_WB_ACK WB_Ack [0 ] 0
-SINK_WB_ACK PF_Load [0 ] 0
-SINK_WB_ACK PF_Store [0 ] 0
-
-PF_IS Load [0 ] 0
-PF_IS Ifetch [0 ] 0
-PF_IS Store [0 ] 0
-PF_IS Inv [0 ] 0
-PF_IS L1_Replacement [0 ] 0
-PF_IS Data_Exclusive [0 ] 0
-PF_IS DataS_fromL1 [0 ] 0
-PF_IS Data_all_Acks [0 ] 0
-PF_IS PF_Load [0 ] 0
-PF_IS PF_Store [0 ] 0
-
-PF_IM Load [0 ] 0
-PF_IM Ifetch [0 ] 0
-PF_IM Store [0 ] 0
-PF_IM Inv [0 ] 0
-PF_IM L1_Replacement [0 ] 0
-PF_IM Data [0 ] 0
-PF_IM Data_all_Acks [0 ] 0
-PF_IM Ack [0 ] 0
-PF_IM PF_Load [0 ] 0
-PF_IM PF_Store [0 ] 0
-
-PF_SM Load [0 ] 0
-PF_SM Ifetch [0 ] 0
-PF_SM Store [0 ] 0
-PF_SM Inv [0 ] 0
-PF_SM L1_Replacement [0 ] 0
-PF_SM Ack [0 ] 0
-PF_SM Ack_all [0 ] 0
-
-PF_IS_I Load [0 ] 0
-PF_IS_I Store [0 ] 0
-PF_IS_I Inv [0 ] 0
-PF_IS_I L1_Replacement [0 ] 0
-PF_IS_I Data_Exclusive [0 ] 0
-PF_IS_I DataS_fromL1 [0 ] 0
-PF_IS_I Data_all_Acks [0 ] 0
-
- --- L2Cache ---
- - Event Counts -
-L1_GET_INSTR [300 ] 300
-L1_GETS [204 ] 204
-L1_GETX [68 ] 68
-L1_UPGRADE [0 ] 0
-L1_PUTX [124 ] 124
-L1_PUTX_old [0 ] 0
-Fwd_L1_GETX [0 ] 0
-Fwd_L1_GETS [0 ] 0
-Fwd_L1_GET_INSTR [0 ] 0
-L2_Replacement [43 ] 43
-L2_Replacement_clean [496 ] 496
-Mem_Data [547 ] 547
-Mem_Ack [539 ] 539
-WB_Data [62 ] 62
-WB_Data_clean [0 ] 0
-Ack [0 ] 0
-Ack_all [369 ] 369
-Unblock [0 ] 0
-Unblock_Cancel [0 ] 0
-Exclusive_Unblock [272 ] 272
-MEM_Inv [0 ] 0
-
- - Transitions -
-NP L1_GET_INSTR [291 ] 291
-NP L1_GETS [192 ] 192
-NP L1_GETX [64 ] 64
-NP L1_PUTX [0 ] 0
-NP L1_PUTX_old [0 ] 0
-
-SS L1_GET_INSTR [9 ] 9
-SS L1_GETS [0 ] 0
-SS L1_GETX [0 ] 0
-SS L1_UPGRADE [0 ] 0
-SS L1_PUTX [0 ] 0
-SS L1_PUTX_old [0 ] 0
-SS L2_Replacement [0 ] 0
-SS L2_Replacement_clean [286 ] 286
-SS MEM_Inv [0 ] 0
-
-M L1_GET_INSTR [0 ] 0
-M L1_GETS [12 ] 12
-M L1_GETX [4 ] 4
-M L1_PUTX [0 ] 0
-M L1_PUTX_old [0 ] 0
-M L2_Replacement [39 ] 39
-M L2_Replacement_clean [69 ] 69
-M MEM_Inv [0 ] 0
-
-MT L1_GET_INSTR [0 ] 0
-MT L1_GETS [0 ] 0
-MT L1_GETX [0 ] 0
-MT L1_PUTX [124 ] 124
-MT L1_PUTX_old [0 ] 0
-MT L2_Replacement [4 ] 4
-MT L2_Replacement_clean [141 ] 141
-MT MEM_Inv [0 ] 0
-
-M_I L1_GET_INSTR [0 ] 0
-M_I L1_GETS [0 ] 0
-M_I L1_GETX [0 ] 0
-M_I L1_UPGRADE [0 ] 0
-M_I L1_PUTX [0 ] 0
-M_I L1_PUTX_old [0 ] 0
-M_I Mem_Ack [539 ] 539
-M_I MEM_Inv [0 ] 0
-
-MT_I L1_GET_INSTR [0 ] 0
-MT_I L1_GETS [0 ] 0
-MT_I L1_GETX [0 ] 0
-MT_I L1_UPGRADE [0 ] 0
-MT_I L1_PUTX [0 ] 0
-MT_I L1_PUTX_old [0 ] 0
-MT_I WB_Data [2 ] 2
-MT_I WB_Data_clean [0 ] 0
-MT_I Ack_all [2 ] 2
-MT_I MEM_Inv [0 ] 0
-
-MCT_I L1_GET_INSTR [0 ] 0
-MCT_I L1_GETS [0 ] 0
-MCT_I L1_GETX [0 ] 0
-MCT_I L1_UPGRADE [0 ] 0
-MCT_I L1_PUTX [0 ] 0
-MCT_I L1_PUTX_old [0 ] 0
-MCT_I WB_Data [60 ] 60
-MCT_I WB_Data_clean [0 ] 0
-MCT_I Ack_all [81 ] 81
-
-I_I L1_GET_INSTR [0 ] 0
-I_I L1_GETS [0 ] 0
-I_I L1_GETX [0 ] 0
-I_I L1_UPGRADE [0 ] 0
-I_I L1_PUTX [0 ] 0
-I_I L1_PUTX_old [0 ] 0
-I_I Ack [0 ] 0
-I_I Ack_all [286 ] 286
-
-S_I L1_GET_INSTR [0 ] 0
-S_I L1_GETS [0 ] 0
-S_I L1_GETX [0 ] 0
-S_I L1_UPGRADE [0 ] 0
-S_I L1_PUTX [0 ] 0
-S_I L1_PUTX_old [0 ] 0
-S_I Ack [0 ] 0
-S_I Ack_all [0 ] 0
-S_I MEM_Inv [0 ] 0
-
-ISS L1_GET_INSTR [0 ] 0
-ISS L1_GETS [0 ] 0
-ISS L1_GETX [0 ] 0
-ISS L1_PUTX [0 ] 0
-ISS L1_PUTX_old [0 ] 0
-ISS L2_Replacement [0 ] 0
-ISS L2_Replacement_clean [0 ] 0
-ISS Mem_Data [192 ] 192
-ISS MEM_Inv [0 ] 0
-
-IS L1_GET_INSTR [0 ] 0
-IS L1_GETS [0 ] 0
-IS L1_GETX [0 ] 0
-IS L1_PUTX [0 ] 0
-IS L1_PUTX_old [0 ] 0
-IS L2_Replacement [0 ] 0
-IS L2_Replacement_clean [0 ] 0
-IS Mem_Data [291 ] 291
-IS MEM_Inv [0 ] 0
-
-IM L1_GET_INSTR [0 ] 0
-IM L1_GETS [0 ] 0
-IM L1_GETX [0 ] 0
-IM L1_PUTX [0 ] 0
-IM L1_PUTX_old [0 ] 0
-IM L2_Replacement [0 ] 0
-IM L2_Replacement_clean [0 ] 0
-IM Mem_Data [64 ] 64
-IM MEM_Inv [0 ] 0
-
-SS_MB L1_GET_INSTR [0 ] 0
-SS_MB L1_GETS [0 ] 0
-SS_MB L1_GETX [0 ] 0
-SS_MB L1_UPGRADE [0 ] 0
-SS_MB L1_PUTX [0 ] 0
-SS_MB L1_PUTX_old [0 ] 0
-SS_MB L2_Replacement [0 ] 0
-SS_MB L2_Replacement_clean [0 ] 0
-SS_MB Unblock_Cancel [0 ] 0
-SS_MB Exclusive_Unblock [0 ] 0
-SS_MB MEM_Inv [0 ] 0
-
-MT_MB L1_GET_INSTR [0 ] 0
-MT_MB L1_GETS [0 ] 0
-MT_MB L1_GETX [0 ] 0
-MT_MB L1_UPGRADE [0 ] 0
-MT_MB L1_PUTX [0 ] 0
-MT_MB L1_PUTX_old [0 ] 0
-MT_MB L2_Replacement [0 ] 0
-MT_MB L2_Replacement_clean [0 ] 0
-MT_MB Unblock_Cancel [0 ] 0
-MT_MB Exclusive_Unblock [272 ] 272
-MT_MB MEM_Inv [0 ] 0
-
-MT_IIB L1_GET_INSTR [0 ] 0
-MT_IIB L1_GETS [0 ] 0
-MT_IIB L1_GETX [0 ] 0
-MT_IIB L1_UPGRADE [0 ] 0
-MT_IIB L1_PUTX [0 ] 0
-MT_IIB L1_PUTX_old [0 ] 0
-MT_IIB L2_Replacement [0 ] 0
-MT_IIB L2_Replacement_clean [0 ] 0
-MT_IIB WB_Data [0 ] 0
-MT_IIB WB_Data_clean [0 ] 0
-MT_IIB Unblock [0 ] 0
-MT_IIB MEM_Inv [0 ] 0
-
-MT_IB L1_GET_INSTR [0 ] 0
-MT_IB L1_GETS [0 ] 0
-MT_IB L1_GETX [0 ] 0
-MT_IB L1_UPGRADE [0 ] 0
-MT_IB L1_PUTX [0 ] 0
-MT_IB L1_PUTX_old [0 ] 0
-MT_IB L2_Replacement [0 ] 0
-MT_IB L2_Replacement_clean [0 ] 0
-MT_IB WB_Data [0 ] 0
-MT_IB WB_Data_clean [0 ] 0
-MT_IB Unblock_Cancel [0 ] 0
-MT_IB MEM_Inv [0 ] 0
-
-MT_SB L1_GET_INSTR [0 ] 0
-MT_SB L1_GETS [0 ] 0
-MT_SB L1_GETX [0 ] 0
-MT_SB L1_UPGRADE [0 ] 0
-MT_SB L1_PUTX [0 ] 0
-MT_SB L1_PUTX_old [0 ] 0
-MT_SB L2_Replacement [0 ] 0
-MT_SB L2_Replacement_clean [0 ] 0
-MT_SB Unblock [0 ] 0
-MT_SB MEM_Inv [0 ] 0
-
-Memory controller: system.ruby.dir_cntrl0.memBuffer:
- memory_total_requests: 650
- memory_reads: 547
- memory_writes: 103
- memory_refreshes: 365
- memory_total_request_delays: 117
- memory_delays_per_request: 0.18
- memory_delays_in_input_queue: 0
- memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 117
- memory_stalls_for_bank_busy: 63
- memory_stalls_for_random_busy: 0
- memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 8
- memory_stalls_for_bus: 46
- memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 0
- memory_stalls_for_read_read_turnaround: 0
- accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92
-
- --- Directory ---
- - Event Counts -
-Fetch [547 ] 547
-Data [103 ] 103
-Memory_Data [547 ] 547
-Memory_Ack [103 ] 103
-DMA_READ [0 ] 0
-DMA_WRITE [0 ] 0
-CleanReplacement [436 ] 436
-
- - Transitions -
-I Fetch [547 ] 547
-I DMA_READ [0 ] 0
-I DMA_WRITE [0 ] 0
-
-ID Fetch [0 ] 0
-ID Data [0 ] 0
-ID Memory_Data [0 ] 0
-ID DMA_READ [0 ] 0
-ID DMA_WRITE [0 ] 0
-
-ID_W Fetch [0 ] 0
-ID_W Data [0 ] 0
-ID_W Memory_Ack [0 ] 0
-ID_W DMA_READ [0 ] 0
-ID_W DMA_WRITE [0 ] 0
-
-M Data [103 ] 103
-M DMA_READ [0 ] 0
-M DMA_WRITE [0 ] 0
-M CleanReplacement [436 ] 436
-
-IM Fetch [0 ] 0
-IM Data [0 ] 0
-IM Memory_Data [547 ] 547
-IM DMA_READ [0 ] 0
-IM DMA_WRITE [0 ] 0
-
-MI Fetch [0 ] 0
-MI Data [0 ] 0
-MI Memory_Ack [103 ] 103
-MI DMA_READ [0 ] 0
-MI DMA_WRITE [0 ] 0
-
-M_DRD Data [0 ] 0
-M_DRD DMA_READ [0 ] 0
-M_DRD DMA_WRITE [0 ] 0
-
-M_DRDI Fetch [0 ] 0
-M_DRDI Data [0 ] 0
-M_DRDI Memory_Ack [0 ] 0
-M_DRDI DMA_READ [0 ] 0
-M_DRDI DMA_WRITE [0 ] 0
-
-M_DWR Data [0 ] 0
-M_DWR DMA_READ [0 ] 0
-M_DWR DMA_WRITE [0 ] 0
-
-M_DWRI Fetch [0 ] 0
-M_DWRI Data [0 ] 0
-M_DWRI Memory_Ack [0 ] 0
-M_DWRI DMA_READ [0 ] 0
-M_DWRI DMA_WRITE [0 ] 0
-
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index e400893c2..6569b99b5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu
sim_ticks 52575 # Number of ticks simulated
final_tick 52575 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 12497 # Simulator instruction rate (inst/s)
-host_op_rate 12496 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 254920 # Simulator tick rate (ticks/s)
-host_mem_usage 152164 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 18867 # Simulator instruction rate (inst/s)
+host_op_rate 18864 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 384805 # Simulator tick rate (ticks/s)
+host_mem_usage 145340 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits
@@ -29,6 +29,19 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles 117 # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls 117 # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.180000 # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy 63 # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy 46 # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memArbWait 8 # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount | 26 4.00% 4.00% | 14 2.15% 6.15% | 0 0.00% 6.15% | 49 7.54% 13.69% | 21 3.23% 16.92% | 21 3.23% 20.15% | 42 6.46% 26.62% | 25 3.85% 30.46% | 6 0.92% 31.38% | 4 0.62% 32.00% | 7 1.08% 33.08% | 4 0.62% 33.69% | 24 3.69% 37.38% | 42 6.46% 43.85% | 26 4.00% 47.85% | 3 0.46% 48.31% | 5 0.77% 49.08% | 7 1.08% 50.15% | 7 1.08% 51.23% | 18 2.77% 54.00% | 10 1.54% 55.54% | 29 4.46% 60.00% | 15 2.31% 62.31% | 50 7.69% 70.00% | 19 2.92% 72.92% | 5 0.77% 73.69% | 6 0.92% 74.62% | 16 2.46% 77.08% | 14 2.15% 79.23% | 24 3.69% 82.92% | 19 2.92% 85.85% | 92 14.15% 100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total 650 # Number of accesses per bank
+
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -84,5 +97,79 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 52575 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.ruby.l2_cntrl0.L1_GET_INSTR 300 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETS 204 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETX 68 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_PUTX 124 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement 43 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement_clean 496 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Data 547 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Ack 539 0.00% 0.00%
+system.ruby.l2_cntrl0.WB_Data 62 0.00% 0.00%
+system.ruby.l2_cntrl0.Ack_all 369 0.00% 0.00%
+system.ruby.l2_cntrl0.Exclusive_Unblock 272 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GET_INSTR 291 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETS 192 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETX 64 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GET_INSTR 9 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L2_Replacement_clean 286 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETS 12 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETX 4 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement 39 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement_clean 69 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_PUTX 124 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement 4 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement_clean 141 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.Mem_Ack 539 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.WB_Data 2 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.WB_Data 60 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.Ack_all 81 0.00% 0.00%
+system.ruby.l2_cntrl0.I_I.Ack_all 286 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.Mem_Data 192 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.Mem_Data 291 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.Mem_Data 64 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 272 0.00% 0.00%
+system.ruby.l1_cntrl0.Load 415 0.00% 0.00%
+system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00%
+system.ruby.l1_cntrl0.Store 294 0.00% 0.00%
+system.ruby.l1_cntrl0.Inv 431 0.00% 0.00%
+system.ruby.l1_cntrl0.L1_Replacement 502 0.00% 0.00%
+system.ruby.l1_cntrl0.Data_Exclusive 204 0.00% 0.00%
+system.ruby.l1_cntrl0.Data_all_Acks 368 0.00% 0.00%
+system.ruby.l1_cntrl0.WB_Ack 124 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Load 182 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Ifetch 270 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Store 58 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Inv 162 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Load 22 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Ifetch 30 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Store 10 0.00% 0.00%
+system.ruby.l1_cntrl0.I.L1_Replacement 206 0.00% 0.00%
+system.ruby.l1_cntrl0.S.Ifetch 2285 0.00% 0.00%
+system.ruby.l1_cntrl0.S.Inv 124 0.00% 0.00%
+system.ruby.l1_cntrl0.S.L1_Replacement 172 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Load 140 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Store 41 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Inv 83 0.00% 0.00%
+system.ruby.l1_cntrl0.E.L1_Replacement 79 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Load 71 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Store 185 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Inv 62 0.00% 0.00%
+system.ruby.l1_cntrl0.M.L1_Replacement 45 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Data_Exclusive 204 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Data_all_Acks 300 0.00% 0.00%
+system.ruby.l1_cntrl0.IM.Data_all_Acks 68 0.00% 0.00%
+system.ruby.l1_cntrl0.M_I.WB_Ack 124 0.00% 0.00%
+system.ruby.dir_cntrl0.Fetch 547 0.00% 0.00%
+system.ruby.dir_cntrl0.Data 103 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Data 547 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Ack 103 0.00% 0.00%
+system.ruby.dir_cntrl0.CleanReplacement 436 0.00% 0.00%
+system.ruby.dir_cntrl0.I.Fetch 547 0.00% 0.00%
+system.ruby.dir_cntrl0.M.Data 103 0.00% 0.00%
+system.ruby.dir_cntrl0.M.CleanReplacement 436 0.00% 0.00%
+system.ruby.dir_cntrl0.IM.Memory_Data 547 0.00% 0.00%
+system.ruby.dir_cntrl0.MI.Memory_Ack 103 0.00% 0.00%
---------- End Simulation Statistics ----------
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 10:09:30 +0000