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author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
commit | f3585c841e964c98911784a187fc4f081a02a0a6 (patch) | |
tree | 2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt | |
parent | cfc4a999828a5b51f4c514e3a7c47b4eebc450b9 (diff) | |
download | gem5-f3585c841e964c98911784a187fc4f081a02a0a6.tar.xz |
stats: update stats for cache occupancy and clock domain changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt')
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 1d9a45506..96547c7d5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000053 # Nu sim_ticks 52548 # Number of ticks simulated final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16682 # Simulator instruction rate (inst/s) -host_op_rate 16680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 340078 # Simulator tick rate (ticks/s) -host_mem_usage 169540 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 25744 # Simulator instruction rate (inst/s) +host_op_rate 25740 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 524809 # Simulator tick rate (ticks/s) +host_mem_usage 124924 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 3612 # delay histogram for all message @@ -100,6 +103,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 2176 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes @@ -148,6 +152,7 @@ system.ruby.network.msg_byte.Response_Data 263952 system.ruby.network.msg_byte.Response_Control 41760 system.ruby.network.msg_byte.Writeback_Data 23112 system.ruby.network.msg_byte.Writeback_Control 1896 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv |