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author | Joel Hestness <hestness@cs.wisc.edu> | 2012-09-05 20:53:34 -0500 |
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committer | Joel Hestness <hestness@cs.wisc.edu> | 2012-09-05 20:53:34 -0500 |
commit | 4124ea09f8e2f6934fe746ff7c244dba7230cac9 (patch) | |
tree | b2bfebc3b4e62ff6a06deec45852f58fa2aded23 /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt | |
parent | 6924e10978c5847fa33cf33c50f5b3511bf89ee4 (diff) | |
download | gem5-4124ea09f8e2f6934fe746ff7c244dba7230cac9.tar.xz |
stats: Update Ruby regressions for memory controller fix
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt')
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 2737629f8..b192d2700 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000085 # Number of seconds simulated -sim_ticks 85418 # Number of ticks simulated -final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000045 # Number of seconds simulated +sim_ticks 44968 # Number of ticks simulated +final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 1284 # Simulator instruction rate (inst/s) -host_op_rate 1284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42571 # Simulator tick rate (ticks/s) -host_mem_usage 232824 # Number of bytes of host memory used -host_seconds 2.01 # Real time elapsed on the host +host_inst_rate 22673 # Simulator instruction rate (inst/s) +host_op_rate 22668 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 395469 # Simulator tick rate (ticks/s) +host_mem_usage 264056 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 415 # Nu system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory system.physmem.num_writes::total 294 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 121051769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35308717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 156360486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 121051769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 121051769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 24093282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24093282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 229941292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 67069916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 297011208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 229941292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 229941292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 45765878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45765878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 229941292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 112835794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 342777086 # Total bandwidth to/from this memory (bytes/s) system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -84,7 +84,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 85418 # number of cpu cycles simulated +system.cpu.numCycles 44968 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -103,7 +103,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 85418 # Number of busy cycles +system.cpu.num_busy_cycles 44968 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles |