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| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-28 13:48:04 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-28 13:48:04 -0400 |
| commit | 19cc023cf51268f3c4f3a83d95319f37660d94f7 (patch) | |
| tree | c6ffa5082e735787c7f2e55c45eedc3116f8e952 /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt | |
| parent | fe2faa1975fb2c03ad7e493489d62ea06767f52f (diff) | |
| download | gem5-19cc023cf51268f3c4f3a83d95319f37660d94f7.tar.xz | |
stats: fix some miss-committed changes from the icache change
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 07e9173f4..2737629f8 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000085 # Nu sim_ticks 85418 # Number of ticks simulated final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 30509 # Simulator instruction rate (inst/s) -host_op_rate 30502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1010829 # Simulator tick rate (ticks/s) -host_mem_usage 224228 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 1284 # Simulator instruction rate (inst/s) +host_op_rate 1284 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42571 # Simulator tick rate (ticks/s) +host_mem_usage 232824 # Number of bytes of host memory used +host_seconds 2.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -33,6 +33,24 @@ system.physmem.bw_write::total 24093282 # Wr system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s) +system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads +system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes +system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv |