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authorNilay Vaish <nilay@cs.wisc.edu>2013-05-21 11:32:57 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2013-05-21 11:32:57 -0500
commit5b49c3d255eb82089496f8a77d6ab50004b5a2c2 (patch)
treec27568e48e0c39d9943830a870dbf234273c5b7d /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
parent4ef466cc8a6890a63f504cec02a65ed3f6386e12 (diff)
downloadgem5-5b49c3d255eb82089496f8a77d6ab50004b5a2c2.tar.xz
stats: updates statistics for ruby regressions
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory')
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini21
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats24
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt37
3 files changed, 25 insertions, 57 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index fc72761f4..713cafbd1 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -52,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+simpoint_start_insts=
switched_out=false
system=system
tracer=system.cpu.tracer
@@ -166,9 +167,9 @@ version=0
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory sequencer
-L1DcacheMemory=system.ruby.l1_cntrl0.L1DcacheMemory
-L1IcacheMemory=system.ruby.l1_cntrl0.L1IcacheMemory
+children=L1Dcache L1Icache sequencer
+L1Dcache=system.ruby.l1_cntrl0.L1Dcache
+L1Icache=system.ruby.l1_cntrl0.L1Icache
buffer_size=0
clock=1
cntrl_id=0
@@ -184,7 +185,7 @@ transitions_per_cycle=32
use_timeout_latency=50
version=0
-[system.ruby.l1_cntrl0.L1DcacheMemory]
+[system.ruby.l1_cntrl0.L1Dcache]
type=RubyCache
assoc=2
dataAccessLatency=1
@@ -198,7 +199,7 @@ start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
-[system.ruby.l1_cntrl0.L1IcacheMemory]
+[system.ruby.l1_cntrl0.L1Icache]
type=RubyCache
assoc=2
dataAccessLatency=1
@@ -216,9 +217,9 @@ tagArrayBanks=1
type=RubySequencer
access_phys_mem=false
clock=1
-dcache=system.ruby.l1_cntrl0.L1DcacheMemory
+dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
-icache=system.ruby.l1_cntrl0.L1IcacheMemory
+icache=system.ruby.l1_cntrl0.L1Icache
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
@@ -231,8 +232,8 @@ slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.l2_cntrl0]
type=L2Cache_Controller
-children=L2cacheMemory
-L2cacheMemory=system.ruby.l2_cntrl0.L2cacheMemory
+children=L2cache
+L2cache=system.ruby.l2_cntrl0.L2cache
buffer_size=0
clock=1
cntrl_id=1
@@ -245,7 +246,7 @@ ruby_system=system.ruby
transitions_per_cycle=32
version=0
-[system.ruby.l2_cntrl0.L2cacheMemory]
+[system.ruby.l2_cntrl0.L2cache]
type=RubyCache
assoc=2
dataAccessLatency=1
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 5885ff77b..1cbdf7fce 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -164,22 +164,6 @@ links_utilized_percent_switch_3: 6.52835
outgoing_messages_switch_3_link_2_Writeback_Control: 738 5904 [ 0 407 331 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Unblock_Control: 423 3384 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory
- system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 0
- system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
- system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
- system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
- system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
-
-
-Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory
- system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 0
- system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
- system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
- system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
- system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
-
-
--- L1Cache ---
- Event Counts -
Load [415 ] 415
@@ -342,14 +326,6 @@ II Writeback_Ack [0 ] 0
II Writeback_Ack_Data [0 ] 0
II Writeback_Nack [0 ] 0
-Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory
- system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 0
- system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
- system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0
- system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
- system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
-
-
--- L2Cache ---
- Event Counts -
L1_GETS [454 ] 454
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 21dd911d3..8f2c45ec9 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,31 +4,22 @@ sim_seconds 0.000045 # Nu
sim_ticks 44968 # Number of ticks simulated
final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 8988 # Simulator instruction rate (inst/s)
-host_op_rate 8987 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 156818 # Simulator tick rate (ticks/s)
-host_mem_usage 149468 # Number of bytes of host memory used
-host_seconds 0.29 # Real time elapsed on the host
+host_inst_rate 13243 # Simulator instruction rate (inst/s)
+host_op_rate 13241 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 231036 # Simulator tick rate (ticks/s)
+host_mem_usage 152316 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
-system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
-system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
-system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
-system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
-system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
-system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
-system.ruby.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
-system.ruby.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
-system.ruby.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
-system.ruby.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
-system.ruby.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
-system.ruby.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
-system.ruby.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
-system.ruby.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
-system.ruby.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
-system.ruby.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
-system.ruby.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
-system.ruby.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
+system.ruby.l2_cntrl0.L2cache.demand_hits 87 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 423 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv