stats: fix some miss-committed changes from the icache change

3 files changed, 71 insertions, 34 deletions

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 34c479e22..e62cfb199 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -152,20 +152,30 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
+resourceStalls=false
 size=256
 start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
+resourceStalls=false
 size=256
 start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -200,11 +210,16 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
+resourceStalls=false
 size=512
 start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -241,56 +256,76 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
+routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
+children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.routers0
+int_node=system.ruby.network.topology.ext_links0.int_node
 latency=1
 link_id=0
 weight=1
 
+[system.ruby.network.topology.ext_links0.int_node]
+type=BasicRouter
+router_id=0
+
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
+children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.routers1
+int_node=system.ruby.network.topology.ext_links1.int_node
 latency=1
 link_id=1
 weight=1
 
+[system.ruby.network.topology.ext_links1.int_node]
+type=BasicRouter
+router_id=1
+
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
+children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.routers2
+int_node=system.ruby.network.topology.ext_links2.int_node
 latency=1
 link_id=2
 weight=1
 
+[system.ruby.network.topology.ext_links2.int_node]
+type=BasicRouter
+router_id=2
+
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
+children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.routers0
-node_b=system.ruby.network.topology.routers3
+node_a=system.ruby.network.topology.ext_links0.int_node
+node_b=system.ruby.network.topology.int_links0.node_b
 weight=1
 
+[system.ruby.network.topology.int_links0.node_b]
+type=BasicRouter
+router_id=3
+
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.routers1
-node_b=system.ruby.network.topology.routers3
+node_a=system.ruby.network.topology.ext_links1.int_node
+node_b=system.ruby.network.topology.int_links0.node_b
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -298,26 +333,10 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.routers2
-node_b=system.ruby.network.topology.routers3
+node_a=system.ruby.network.topology.ext_links2.int_node
+node_b=system.ruby.network.topology.int_links0.node_b
 weight=1
 
-[system.ruby.network.topology.routers0]
-type=BasicRouter
-router_id=0
-
-[system.ruby.network.topology.routers1]
-type=BasicRouter
-router_id=1
-
-[system.ruby.network.topology.routers2]
-type=BasicRouter
-router_id=2
-
-[system.ruby.network.topology.routers3]
-type=BasicRouter
-router_id=3
-
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index dc8b54148..6a5f96ccf 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:54:55
-gem5 started Jun  4 2012 14:41:15
+gem5 compiled Jul 28 2012 11:32:56
+gem5 started Jul 28 2012 11:35:53
 gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 07e9173f4..2737629f8 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000085                       # Nu
 sim_ticks                                       85418                       # Number of ticks simulated
 final_tick                                      85418                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  30509                       # Simulator instruction rate (inst/s)
-host_op_rate                                    30502                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1010829                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224228                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                   1284                       # Simulator instruction rate (inst/s)
+host_op_rate                                     1284                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                  42571                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232824                       # Number of bytes of host memory used
+host_seconds                                     2.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
@@ -33,6 +33,24 @@ system.physmem.bw_write::total               24093282                       # Wr
 system.physmem.bw_total::cpu.inst           121051769                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            59402000                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              180453769                       # Total bandwidth to/from this memory (bytes/s)
+system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
+system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
+system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
+system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
+system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
+system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
+system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
+system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
+system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
+system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
+system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
+system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
+system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
+system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
+system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
+system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv