stats: updates due to changes to ruby

Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.

2 files changed, 106 insertions, 1261 deletions

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 1cbdf7fce..619a67ae6 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Mar/06/2013 20:42:20
+Real time: Jun/08/2013 14:13:05
 
 Profiler Stats
 --------------
@@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.58
-Virtual_time_in_minutes: 0.00966667
-Virtual_time_in_hours:   0.000161111
-Virtual_time_in_days:    6.71296e-06
+Virtual_time_in_seconds: 0.51
+Virtual_time_in_minutes: 0.0085
+Virtual_time_in_hours:   0.000141667
+Virtual_time_in_days:    5.90278e-06
 
 Ruby_current_time: 44968
 Ruby_start_time: 0
 Ruby_cycles: 44968
 
-mbytes_resident: 53.8398
-mbytes_total: 145.961
-resident_ratio: 0.368918
-
-ruby_cycles_executed: [ 44969 ]
+mbytes_resident: 55.6133
+mbytes_total: 143.102
+resident_ratio: 0.388683
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -61,7 +59,6 @@ Request vs. RubySystem State Profile
 --------------------------------
 
 
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 
 Message Delayed Cycles
 ----------------------
@@ -82,11 +79,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11071
+page_reclaims: 11425
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 96
+block_outputs: 88
 
 Network Stats
 -------------
@@ -164,1246 +161,3 @@ links_utilized_percent_switch_3: 6.52835
   outgoing_messages_switch_3_link_2_Writeback_Control: 738 5904 [ 0 407 331 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_2_Unblock_Control: 423 3384 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1
 
- --- L1Cache ---
- - Event Counts -
-Load [415 ] 415
-Ifetch [2585 ] 2585
-Store [294 ] 294
-L1_Replacement [506 ] 506
-Own_GETX [0 ] 0
-Fwd_GETX [0 ] 0
-Fwd_GETS [0 ] 0
-Fwd_DMA [0 ] 0
-Inv [0 ] 0
-Ack [0 ] 0
-Data [0 ] 0
-Exclusive_Data [510 ] 510
-Writeback_Ack [0 ] 0
-Writeback_Ack_Data [502 ] 502
-Writeback_Nack [0 ] 0
-All_acks [58 ] 58
-Use_Timeout [509 ] 509
-
- - Transitions -
-I  Load [182 ] 182
-I  Ifetch [270 ] 270
-I  Store [58 ] 58
-I  L1_Replacement [0 ] 0
-I  Inv [0 ] 0
-
-S  Load [0 ] 0
-S  Ifetch [0 ] 0
-S  Store [0 ] 0
-S  L1_Replacement [0 ] 0
-S  Fwd_GETS [0 ] 0
-S  Fwd_DMA [0 ] 0
-S  Inv [0 ] 0
-
-O  Load [0 ] 0
-O  Ifetch [0 ] 0
-O  Store [0 ] 0
-O  L1_Replacement [0 ] 0
-O  Fwd_GETX [0 ] 0
-O  Fwd_GETS [0 ] 0
-O  Fwd_DMA [0 ] 0
-
-M  Load [82 ] 82
-M  Ifetch [1220 ] 1220
-M  Store [33 ] 33
-M  L1_Replacement [406 ] 406
-M  Fwd_GETX [0 ] 0
-M  Fwd_GETS [0 ] 0
-M  Fwd_DMA [0 ] 0
-
-M_W  Load [49 ] 49
-M_W  Ifetch [1095 ] 1095
-M_W  Store [7 ] 7
-M_W  L1_Replacement [4 ] 4
-M_W  Own_GETX [0 ] 0
-M_W  Fwd_GETX [0 ] 0
-M_W  Fwd_GETS [0 ] 0
-M_W  Fwd_DMA [0 ] 0
-M_W  Inv [0 ] 0
-M_W  Use_Timeout [444 ] 444
-
-MM  Load [99 ] 99
-MM  Ifetch [0 ] 0
-MM  Store [114 ] 114
-MM  L1_Replacement [96 ] 96
-MM  Fwd_GETX [0 ] 0
-MM  Fwd_GETS [0 ] 0
-MM  Fwd_DMA [0 ] 0
-
-MM_W  Load [3 ] 3
-MM_W  Ifetch [0 ] 0
-MM_W  Store [82 ] 82
-MM_W  L1_Replacement [0 ] 0
-MM_W  Own_GETX [0 ] 0
-MM_W  Fwd_GETX [0 ] 0
-MM_W  Fwd_GETS [0 ] 0
-MM_W  Fwd_DMA [0 ] 0
-MM_W  Inv [0 ] 0
-MM_W  Use_Timeout [65 ] 65
-
-IM  Load [0 ] 0
-IM  Ifetch [0 ] 0
-IM  Store [0 ] 0
-IM  L1_Replacement [0 ] 0
-IM  Inv [0 ] 0
-IM  Ack [0 ] 0
-IM  Data [0 ] 0
-IM  Exclusive_Data [58 ] 58
-
-SM  Load [0 ] 0
-SM  Ifetch [0 ] 0
-SM  Store [0 ] 0
-SM  L1_Replacement [0 ] 0
-SM  Fwd_GETS [0 ] 0
-SM  Fwd_DMA [0 ] 0
-SM  Inv [0 ] 0
-SM  Ack [0 ] 0
-SM  Data [0 ] 0
-SM  Exclusive_Data [0 ] 0
-
-OM  Load [0 ] 0
-OM  Ifetch [0 ] 0
-OM  Store [0 ] 0
-OM  L1_Replacement [0 ] 0
-OM  Own_GETX [0 ] 0
-OM  Fwd_GETX [0 ] 0
-OM  Fwd_GETS [0 ] 0
-OM  Fwd_DMA [0 ] 0
-OM  Ack [0 ] 0
-OM  All_acks [58 ] 58
-
-IS  Load [0 ] 0
-IS  Ifetch [0 ] 0
-IS  Store [0 ] 0
-IS  L1_Replacement [0 ] 0
-IS  Inv [0 ] 0
-IS  Data [0 ] 0
-IS  Exclusive_Data [452 ] 452
-
-SI  Load [0 ] 0
-SI  Ifetch [0 ] 0
-SI  Store [0 ] 0
-SI  L1_Replacement [0 ] 0
-SI  Fwd_GETS [0 ] 0
-SI  Fwd_DMA [0 ] 0
-SI  Inv [0 ] 0
-SI  Writeback_Ack [0 ] 0
-SI  Writeback_Ack_Data [0 ] 0
-SI  Writeback_Nack [0 ] 0
-
-OI  Load [0 ] 0
-OI  Ifetch [0 ] 0
-OI  Store [0 ] 0
-OI  L1_Replacement [0 ] 0
-OI  Fwd_GETX [0 ] 0
-OI  Fwd_GETS [0 ] 0
-OI  Fwd_DMA [0 ] 0
-OI  Writeback_Ack [0 ] 0
-OI  Writeback_Ack_Data [0 ] 0
-OI  Writeback_Nack [0 ] 0
-
-MI  Load [0 ] 0
-MI  Ifetch [0 ] 0
-MI  Store [0 ] 0
-MI  L1_Replacement [0 ] 0
-MI  Fwd_GETX [0 ] 0
-MI  Fwd_GETS [0 ] 0
-MI  Fwd_DMA [0 ] 0
-MI  Writeback_Ack [0 ] 0
-MI  Writeback_Ack_Data [502 ] 502
-MI  Writeback_Nack [0 ] 0
-
-II  Load [0 ] 0
-II  Ifetch [0 ] 0
-II  Store [0 ] 0
-II  L1_Replacement [0 ] 0
-II  Inv [0 ] 0
-II  Writeback_Ack [0 ] 0
-II  Writeback_Ack_Data [0 ] 0
-II  Writeback_Nack [0 ] 0
-
- --- L2Cache ---
- - Event Counts -
-L1_GETS [454 ] 454
-L1_GETX [58 ] 58
-L1_PUTO [0 ] 0
-L1_PUTX [502 ] 502
-L1_PUTS_only [0 ] 0
-L1_PUTS [0 ] 0
-Fwd_GETX [0 ] 0
-Fwd_GETS [0 ] 0
-Fwd_DMA [0 ] 0
-Own_GETX [0 ] 0
-Inv [0 ] 0
-IntAck [0 ] 0
-ExtAck [0 ] 0
-All_Acks [43 ] 43
-Data [43 ] 43
-Data_Exclusive [380 ] 380
-L1_WBCLEANDATA [396 ] 396
-L1_WBDIRTYDATA [106 ] 106
-Writeback_Ack [407 ] 407
-Writeback_Nack [0 ] 0
-Unblock [0 ] 0
-Exclusive_Unblock [510 ] 510
-DmaAck [0 ] 0
-L2_Replacement [407 ] 407
-
- - Transitions -
-NP  L1_GETS [380 ] 380
-NP  L1_GETX [43 ] 43
-NP  L1_PUTO [0 ] 0
-NP  L1_PUTX [0 ] 0
-NP  L1_PUTS [0 ] 0
-NP  Inv [0 ] 0
-
-I  L1_GETS [0 ] 0
-I  L1_GETX [0 ] 0
-I  L1_PUTO [0 ] 0
-I  L1_PUTX [0 ] 0
-I  L1_PUTS [0 ] 0
-I  Inv [0 ] 0
-I  L2_Replacement [0 ] 0
-
-ILS  L1_GETS [0 ] 0
-ILS  L1_GETX [0 ] 0
-ILS  L1_PUTO [0 ] 0
-ILS  L1_PUTX [0 ] 0
-ILS  L1_PUTS_only [0 ] 0
-ILS  L1_PUTS [0 ] 0
-ILS  Inv [0 ] 0
-ILS  L2_Replacement [0 ] 0
-
-ILX  L1_GETS [0 ] 0
-ILX  L1_GETX [0 ] 0
-ILX  L1_PUTO [0 ] 0
-ILX  L1_PUTX [502 ] 502
-ILX  L1_PUTS_only [0 ] 0
-ILX  L1_PUTS [0 ] 0
-ILX  Fwd_GETX [0 ] 0
-ILX  Fwd_GETS [0 ] 0
-ILX  Fwd_DMA [0 ] 0
-ILX  Inv [0 ] 0
-ILX  Data [0 ] 0
-ILX  L2_Replacement [0 ] 0
-
-ILO  L1_GETS [0 ] 0
-ILO  L1_GETX [0 ] 0
-ILO  L1_PUTO [0 ] 0
-ILO  L1_PUTX [0 ] 0
-ILO  L1_PUTS [0 ] 0
-ILO  Fwd_GETX [0 ] 0
-ILO  Fwd_GETS [0 ] 0
-ILO  Fwd_DMA [0 ] 0
-ILO  Inv [0 ] 0
-ILO  Data [0 ] 0
-ILO  L2_Replacement [0 ] 0
-
-ILOX  L1_GETS [0 ] 0
-ILOX  L1_GETX [0 ] 0
-ILOX  L1_PUTO [0 ] 0
-ILOX  L1_PUTX [0 ] 0
-ILOX  L1_PUTS [0 ] 0
-ILOX  Fwd_GETX [0 ] 0
-ILOX  Fwd_GETS [0 ] 0
-ILOX  Fwd_DMA [0 ] 0
-ILOX  Data [0 ] 0
-
-ILOS  L1_GETS [0 ] 0
-ILOS  L1_GETX [0 ] 0
-ILOS  L1_PUTO [0 ] 0
-ILOS  L1_PUTX [0 ] 0
-ILOS  L1_PUTS_only [0 ] 0
-ILOS  L1_PUTS [0 ] 0
-ILOS  Fwd_GETX [0 ] 0
-ILOS  Fwd_GETS [0 ] 0
-ILOS  Fwd_DMA [0 ] 0
-ILOS  Data [0 ] 0
-ILOS  L2_Replacement [0 ] 0
-
-ILOSX  L1_GETS [0 ] 0
-ILOSX  L1_GETX [0 ] 0
-ILOSX  L1_PUTO [0 ] 0
-ILOSX  L1_PUTX [0 ] 0
-ILOSX  L1_PUTS_only [0 ] 0
-ILOSX  L1_PUTS [0 ] 0
-ILOSX  Fwd_GETX [0 ] 0
-ILOSX  Fwd_GETS [0 ] 0
-ILOSX  Fwd_DMA [0 ] 0
-ILOSX  Data [0 ] 0
-
-S  L1_GETS [0 ] 0
-S  L1_GETX [0 ] 0
-S  L1_PUTX [0 ] 0
-S  L1_PUTS [0 ] 0
-S  Inv [0 ] 0
-S  L2_Replacement [0 ] 0
-
-O  L1_GETS [0 ] 0
-O  L1_GETX [0 ] 0
-O  L1_PUTX [0 ] 0
-O  Fwd_GETX [0 ] 0
-O  Fwd_GETS [0 ] 0
-O  Fwd_DMA [0 ] 0
-O  L2_Replacement [0 ] 0
-
-OLS  L1_GETS [0 ] 0
-OLS  L1_GETX [0 ] 0
-OLS  L1_PUTX [0 ] 0
-OLS  L1_PUTS_only [0 ] 0
-OLS  L1_PUTS [0 ] 0
-OLS  Fwd_GETX [0 ] 0
-OLS  Fwd_GETS [0 ] 0
-OLS  Fwd_DMA [0 ] 0
-OLS  L2_Replacement [0 ] 0
-
-OLSX  L1_GETS [0 ] 0
-OLSX  L1_GETX [0 ] 0
-OLSX  L1_PUTO [0 ] 0
-OLSX  L1_PUTX [0 ] 0
-OLSX  L1_PUTS_only [0 ] 0
-OLSX  L1_PUTS [0 ] 0
-OLSX  Fwd_GETX [0 ] 0
-OLSX  Fwd_GETS [0 ] 0
-OLSX  Fwd_DMA [0 ] 0
-OLSX  L2_Replacement [0 ] 0
-
-SLS  L1_GETS [0 ] 0
-SLS  L1_GETX [0 ] 0
-SLS  L1_PUTX [0 ] 0
-SLS  L1_PUTS_only [0 ] 0
-SLS  L1_PUTS [0 ] 0
-SLS  Inv [0 ] 0
-SLS  L2_Replacement [0 ] 0
-
-M  L1_GETS [72 ] 72
-M  L1_GETX [15 ] 15
-M  L1_PUTO [0 ] 0
-M  L1_PUTX [0 ] 0
-M  L1_PUTS [0 ] 0
-M  Fwd_GETX [0 ] 0
-M  Fwd_GETS [0 ] 0
-M  Fwd_DMA [0 ] 0
-M  L2_Replacement [407 ] 407
-
-IFGX  L1_GETS [0 ] 0
-IFGX  L1_GETX [0 ] 0
-IFGX  L1_PUTO [0 ] 0
-IFGX  L1_PUTX [0 ] 0
-IFGX  L1_PUTS_only [0 ] 0
-IFGX  L1_PUTS [0 ] 0
-IFGX  Fwd_GETX [0 ] 0
-IFGX  Fwd_GETS [0 ] 0
-IFGX  Fwd_DMA [0 ] 0
-IFGX  Inv [0 ] 0
-IFGX  Data [0 ] 0
-IFGX  Data_Exclusive [0 ] 0
-IFGX  L2_Replacement [0 ] 0
-
-IFGS  L1_GETS [0 ] 0
-IFGS  L1_GETX [0 ] 0
-IFGS  L1_PUTO [0 ] 0
-IFGS  L1_PUTX [0 ] 0
-IFGS  L1_PUTS_only [0 ] 0
-IFGS  L1_PUTS [0 ] 0
-IFGS  Fwd_GETX [0 ] 0
-IFGS  Fwd_GETS [0 ] 0
-IFGS  Fwd_DMA [0 ] 0
-IFGS  Inv [0 ] 0
-IFGS  Data [0 ] 0
-IFGS  Data_Exclusive [0 ] 0
-IFGS  L2_Replacement [0 ] 0
-
-ISFGS  L1_GETS [0 ] 0
-ISFGS  L1_GETX [0 ] 0
-ISFGS  L1_PUTO [0 ] 0
-ISFGS  L1_PUTX [0 ] 0
-ISFGS  L1_PUTS_only [0 ] 0
-ISFGS  L1_PUTS [0 ] 0
-ISFGS  Fwd_GETX [0 ] 0
-ISFGS  Fwd_GETS [0 ] 0
-ISFGS  Fwd_DMA [0 ] 0
-ISFGS  Inv [0 ] 0
-ISFGS  Data [0 ] 0
-ISFGS  L2_Replacement [0 ] 0
-
-IFGXX  L1_GETS [0 ] 0
-IFGXX  L1_GETX [0 ] 0
-IFGXX  L1_PUTO [0 ] 0
-IFGXX  L1_PUTX [0 ] 0
-IFGXX  L1_PUTS_only [0 ] 0
-IFGXX  L1_PUTS [0 ] 0
-IFGXX  Fwd_GETX [0 ] 0
-IFGXX  Fwd_GETS [0 ] 0
-IFGXX  Fwd_DMA [0 ] 0
-IFGXX  Inv [0 ] 0
-IFGXX  IntAck [0 ] 0
-IFGXX  All_Acks [0 ] 0
-IFGXX  Data_Exclusive [0 ] 0
-IFGXX  L2_Replacement [0 ] 0
-
-OFGX  L1_GETS [0 ] 0
-OFGX  L1_GETX [0 ] 0
-OFGX  L1_PUTO [0 ] 0
-OFGX  L1_PUTX [0 ] 0
-OFGX  L1_PUTS_only [0 ] 0
-OFGX  L1_PUTS [0 ] 0
-OFGX  Fwd_GETX [0 ] 0
-OFGX  Fwd_GETS [0 ] 0
-OFGX  Fwd_DMA [0 ] 0
-OFGX  Inv [0 ] 0
-OFGX  L2_Replacement [0 ] 0
-
-OLSF  L1_GETS [0 ] 0
-OLSF  L1_GETX [0 ] 0
-OLSF  L1_PUTO [0 ] 0
-OLSF  L1_PUTX [0 ] 0
-OLSF  L1_PUTS_only [0 ] 0
-OLSF  L1_PUTS [0 ] 0
-OLSF  Fwd_GETX [0 ] 0
-OLSF  Fwd_GETS [0 ] 0
-OLSF  Fwd_DMA [0 ] 0
-OLSF  Inv [0 ] 0
-OLSF  IntAck [0 ] 0
-OLSF  All_Acks [0 ] 0
-OLSF  L2_Replacement [0 ] 0
-
-ILOW  L1_GETS [0 ] 0
-ILOW  L1_GETX [0 ] 0
-ILOW  L1_PUTO [0 ] 0
-ILOW  L1_PUTX [0 ] 0
-ILOW  L1_PUTS_only [0 ] 0
-ILOW  L1_PUTS [0 ] 0
-ILOW  Fwd_GETX [0 ] 0
-ILOW  Fwd_GETS [0 ] 0
-ILOW  Fwd_DMA [0 ] 0
-ILOW  Inv [0 ] 0
-ILOW  L1_WBCLEANDATA [0 ] 0
-ILOW  L1_WBDIRTYDATA [0 ] 0
-ILOW  Unblock [0 ] 0
-ILOW  L2_Replacement [0 ] 0
-
-ILOXW  L1_GETS [0 ] 0
-ILOXW  L1_GETX [0 ] 0
-ILOXW  L1_PUTO [0 ] 0
-ILOXW  L1_PUTX [0 ] 0
-ILOXW  L1_PUTS_only [0 ] 0
-ILOXW  L1_PUTS [0 ] 0
-ILOXW  Fwd_GETX [0 ] 0
-ILOXW  Fwd_GETS [0 ] 0
-ILOXW  Fwd_DMA [0 ] 0
-ILOXW  Inv [0 ] 0
-ILOXW  L1_WBCLEANDATA [0 ] 0
-ILOXW  L1_WBDIRTYDATA [0 ] 0
-ILOXW  Unblock [0 ] 0
-ILOXW  L2_Replacement [0 ] 0
-
-ILOSW  L1_GETS [0 ] 0
-ILOSW  L1_GETX [0 ] 0
-ILOSW  L1_PUTO [0 ] 0
-ILOSW  L1_PUTX [0 ] 0
-ILOSW  L1_PUTS_only [0 ] 0
-ILOSW  L1_PUTS [0 ] 0
-ILOSW  Fwd_GETX [0 ] 0
-ILOSW  Fwd_GETS [0 ] 0
-ILOSW  Fwd_DMA [0 ] 0
-ILOSW  Inv [0 ] 0
-ILOSW  L1_WBCLEANDATA [0 ] 0
-ILOSW  L1_WBDIRTYDATA [0 ] 0
-ILOSW  Unblock [0 ] 0
-ILOSW  L2_Replacement [0 ] 0
-
-ILOSXW  L1_GETS [0 ] 0
-ILOSXW  L1_GETX [0 ] 0
-ILOSXW  L1_PUTO [0 ] 0
-ILOSXW  L1_PUTX [0 ] 0
-ILOSXW  L1_PUTS_only [0 ] 0
-ILOSXW  L1_PUTS [0 ] 0
-ILOSXW  Fwd_GETX [0 ] 0
-ILOSXW  Fwd_GETS [0 ] 0
-ILOSXW  Fwd_DMA [0 ] 0
-ILOSXW  Inv [0 ] 0
-ILOSXW  L1_WBCLEANDATA [0 ] 0
-ILOSXW  L1_WBDIRTYDATA [0 ] 0
-ILOSXW  Unblock [0 ] 0
-ILOSXW  L2_Replacement [0 ] 0
-
-SLSW  L1_GETS [0 ] 0
-SLSW  L1_GETX [0 ] 0
-SLSW  L1_PUTO [0 ] 0
-SLSW  L1_PUTX [0 ] 0
-SLSW  L1_PUTS_only [0 ] 0
-SLSW  L1_PUTS [0 ] 0
-SLSW  Fwd_GETX [0 ] 0
-SLSW  Fwd_GETS [0 ] 0
-SLSW  Fwd_DMA [0 ] 0
-SLSW  Inv [0 ] 0
-SLSW  Unblock [0 ] 0
-SLSW  L2_Replacement [0 ] 0
-
-OLSW  L1_GETS [0 ] 0
-OLSW  L1_GETX [0 ] 0
-OLSW  L1_PUTO [0 ] 0
-OLSW  L1_PUTX [0 ] 0
-OLSW  L1_PUTS_only [0 ] 0
-OLSW  L1_PUTS [0 ] 0
-OLSW  Fwd_GETX [0 ] 0
-OLSW  Fwd_GETS [0 ] 0
-OLSW  Fwd_DMA [0 ] 0
-OLSW  Inv [0 ] 0
-OLSW  Unblock [0 ] 0
-OLSW  L2_Replacement [0 ] 0
-
-ILSW  L1_GETS [0 ] 0
-ILSW  L1_GETX [0 ] 0
-ILSW  L1_PUTO [0 ] 0
-ILSW  L1_PUTX [0 ] 0
-ILSW  L1_PUTS_only [0 ] 0
-ILSW  L1_PUTS [0 ] 0
-ILSW  Fwd_GETX [0 ] 0
-ILSW  Fwd_GETS [0 ] 0
-ILSW  Fwd_DMA [0 ] 0
-ILSW  Inv [0 ] 0
-ILSW  L1_WBCLEANDATA [0 ] 0
-ILSW  Unblock [0 ] 0
-ILSW  L2_Replacement [0 ] 0
-
-IW  L1_GETS [0 ] 0
-IW  L1_GETX [0 ] 0
-IW  L1_PUTO [0 ] 0
-IW  L1_PUTX [0 ] 0
-IW  L1_PUTS_only [0 ] 0
-IW  L1_PUTS [0 ] 0
-IW  Fwd_GETX [0 ] 0
-IW  Fwd_GETS [0 ] 0
-IW  Fwd_DMA [0 ] 0
-IW  Inv [0 ] 0
-IW  L1_WBCLEANDATA [0 ] 0
-IW  L2_Replacement [0 ] 0
-
-OW  L1_GETS [0 ] 0
-OW  L1_GETX [0 ] 0
-OW  L1_PUTO [0 ] 0
-OW  L1_PUTX [0 ] 0
-OW  L1_PUTS_only [0 ] 0
-OW  L1_PUTS [0 ] 0
-OW  Fwd_GETX [0 ] 0
-OW  Fwd_GETS [0 ] 0
-OW  Fwd_DMA [0 ] 0
-OW  Inv [0 ] 0
-OW  Unblock [0 ] 0
-OW  L2_Replacement [0 ] 0
-
-SW  L1_GETS [0 ] 0
-SW  L1_GETX [0 ] 0
-SW  L1_PUTO [0 ] 0
-SW  L1_PUTX [0 ] 0
-SW  L1_PUTS_only [0 ] 0
-SW  L1_PUTS [0 ] 0
-SW  Fwd_GETX [0 ] 0
-SW  Fwd_GETS [0 ] 0
-SW  Fwd_DMA [0 ] 0
-SW  Inv [0 ] 0
-SW  Unblock [0 ] 0
-SW  L2_Replacement [0 ] 0
-
-OXW  L1_GETS [0 ] 0
-OXW  L1_GETX [0 ] 0
-OXW  L1_PUTO [0 ] 0
-OXW  L1_PUTX [0 ] 0
-OXW  L1_PUTS_only [0 ] 0
-OXW  L1_PUTS [0 ] 0
-OXW  Fwd_GETX [0 ] 0
-OXW  Fwd_GETS [0 ] 0
-OXW  Fwd_DMA [0 ] 0
-OXW  Inv [0 ] 0
-OXW  Unblock [0 ] 0
-OXW  L2_Replacement [0 ] 0
-
-OLSXW  L1_GETS [0 ] 0
-OLSXW  L1_GETX [0 ] 0
-OLSXW  L1_PUTO [0 ] 0
-OLSXW  L1_PUTX [0 ] 0
-OLSXW  L1_PUTS_only [0 ] 0
-OLSXW  L1_PUTS [0 ] 0
-OLSXW  Fwd_GETX [0 ] 0
-OLSXW  Fwd_GETS [0 ] 0
-OLSXW  Fwd_DMA [0 ] 0
-OLSXW  Inv [0 ] 0
-OLSXW  Unblock [0 ] 0
-OLSXW  L2_Replacement [0 ] 0
-
-ILXW  L1_GETS [0 ] 0
-ILXW  L1_GETX [0 ] 0
-ILXW  L1_PUTO [0 ] 0
-ILXW  L1_PUTX [0 ] 0
-ILXW  L1_PUTS_only [0 ] 0
-ILXW  L1_PUTS [0 ] 0
-ILXW  Fwd_GETX [0 ] 0
-ILXW  Fwd_GETS [0 ] 0
-ILXW  Fwd_DMA [0 ] 0
-ILXW  Inv [0 ] 0
-ILXW  Data [0 ] 0
-ILXW  L1_WBCLEANDATA [396 ] 396
-ILXW  L1_WBDIRTYDATA [106 ] 106
-ILXW  Unblock [0 ] 0
-ILXW  L2_Replacement [0 ] 0
-
-IFLS  L1_GETS [0 ] 0
-IFLS  L1_GETX [0 ] 0
-IFLS  L1_PUTO [0 ] 0
-IFLS  L1_PUTX [0 ] 0
-IFLS  L1_PUTS_only [0 ] 0
-IFLS  L1_PUTS [0 ] 0
-IFLS  Fwd_GETX [0 ] 0
-IFLS  Fwd_GETS [0 ] 0
-IFLS  Fwd_DMA [0 ] 0
-IFLS  Inv [0 ] 0
-IFLS  Unblock [0 ] 0
-IFLS  L2_Replacement [0 ] 0
-
-IFLO  L1_GETS [0 ] 0
-IFLO  L1_GETX [0 ] 0
-IFLO  L1_PUTO [0 ] 0
-IFLO  L1_PUTX [0 ] 0
-IFLO  L1_PUTS_only [0 ] 0
-IFLO  L1_PUTS [0 ] 0
-IFLO  Fwd_GETX [0 ] 0
-IFLO  Fwd_GETS [0 ] 0
-IFLO  Fwd_DMA [0 ] 0
-IFLO  Inv [0 ] 0
-IFLO  Unblock [0 ] 0
-IFLO  L2_Replacement [0 ] 0
-
-IFLOX  L1_GETS [0 ] 0
-IFLOX  L1_GETX [0 ] 0
-IFLOX  L1_PUTO [0 ] 0
-IFLOX  L1_PUTX [0 ] 0
-IFLOX  L1_PUTS_only [0 ] 0
-IFLOX  L1_PUTS [0 ] 0
-IFLOX  Fwd_GETX [0 ] 0
-IFLOX  Fwd_GETS [0 ] 0
-IFLOX  Fwd_DMA [0 ] 0
-IFLOX  Inv [0 ] 0
-IFLOX  Unblock [0 ] 0
-IFLOX  Exclusive_Unblock [0 ] 0
-IFLOX  L2_Replacement [0 ] 0
-
-IFLOXX  L1_GETS [0 ] 0
-IFLOXX  L1_GETX [0 ] 0
-IFLOXX  L1_PUTO [0 ] 0
-IFLOXX  L1_PUTX [0 ] 0
-IFLOXX  L1_PUTS_only [0 ] 0
-IFLOXX  L1_PUTS [0 ] 0
-IFLOXX  Fwd_GETX [0 ] 0
-IFLOXX  Fwd_GETS [0 ] 0
-IFLOXX  Fwd_DMA [0 ] 0
-IFLOXX  Inv [0 ] 0
-IFLOXX  Unblock [0 ] 0
-IFLOXX  Exclusive_Unblock [0 ] 0
-IFLOXX  L2_Replacement [0 ] 0
-
-IFLOSX  L1_GETS [0 ] 0
-IFLOSX  L1_GETX [0 ] 0
-IFLOSX  L1_PUTO [0 ] 0
-IFLOSX  L1_PUTX [0 ] 0
-IFLOSX  L1_PUTS_only [0 ] 0
-IFLOSX  L1_PUTS [0 ] 0
-IFLOSX  Fwd_GETX [0 ] 0
-IFLOSX  Fwd_GETS [0 ] 0
-IFLOSX  Fwd_DMA [0 ] 0
-IFLOSX  Inv [0 ] 0
-IFLOSX  Unblock [0 ] 0
-IFLOSX  Exclusive_Unblock [0 ] 0
-IFLOSX  L2_Replacement [0 ] 0
-
-IFLXO  L1_GETS [0 ] 0
-IFLXO  L1_GETX [0 ] 0
-IFLXO  L1_PUTO [0 ] 0
-IFLXO  L1_PUTX [0 ] 0
-IFLXO  L1_PUTS_only [0 ] 0
-IFLXO  L1_PUTS [0 ] 0
-IFLXO  Fwd_GETX [0 ] 0
-IFLXO  Fwd_GETS [0 ] 0
-IFLXO  Fwd_DMA [0 ] 0
-IFLXO  Inv [0 ] 0
-IFLXO  Exclusive_Unblock [0 ] 0
-IFLXO  L2_Replacement [0 ] 0
-
-IGS  L1_GETS [0 ] 0
-IGS  L1_GETX [0 ] 0
-IGS  L1_PUTO [0 ] 0
-IGS  L1_PUTX [0 ] 0
-IGS  L1_PUTS_only [0 ] 0
-IGS  L1_PUTS [0 ] 0
-IGS  Fwd_GETX [0 ] 0
-IGS  Fwd_GETS [0 ] 0
-IGS  Fwd_DMA [0 ] 0
-IGS  Own_GETX [0 ] 0
-IGS  Inv [0 ] 0
-IGS  Data [0 ] 0
-IGS  Data_Exclusive [380 ] 380
-IGS  Unblock [0 ] 0
-IGS  Exclusive_Unblock [380 ] 380
-IGS  L2_Replacement [0 ] 0
-
-IGM  L1_GETS [0 ] 0
-IGM  L1_GETX [0 ] 0
-IGM  L1_PUTO [0 ] 0
-IGM  L1_PUTX [0 ] 0
-IGM  L1_PUTS_only [0 ] 0
-IGM  L1_PUTS [0 ] 0
-IGM  Fwd_GETX [0 ] 0
-IGM  Fwd_GETS [0 ] 0
-IGM  Fwd_DMA [0 ] 0
-IGM  Own_GETX [0 ] 0
-IGM  Inv [0 ] 0
-IGM  ExtAck [0 ] 0
-IGM  Data [43 ] 43
-IGM  Data_Exclusive [0 ] 0
-IGM  L2_Replacement [0 ] 0
-
-IGMLS  L1_GETS [0 ] 0
-IGMLS  L1_GETX [0 ] 0
-IGMLS  L1_PUTO [0 ] 0
-IGMLS  L1_PUTX [0 ] 0
-IGMLS  L1_PUTS_only [0 ] 0
-IGMLS  L1_PUTS [0 ] 0
-IGMLS  Inv [0 ] 0
-IGMLS  IntAck [0 ] 0
-IGMLS  ExtAck [0 ] 0
-IGMLS  All_Acks [0 ] 0
-IGMLS  Data [0 ] 0
-IGMLS  Data_Exclusive [0 ] 0
-IGMLS  L2_Replacement [0 ] 0
-
-IGMO  L1_GETS [0 ] 0
-IGMO  L1_GETX [0 ] 0
-IGMO  L1_PUTO [0 ] 0
-IGMO  L1_PUTX [0 ] 0
-IGMO  L1_PUTS_only [0 ] 0
-IGMO  L1_PUTS [0 ] 0
-IGMO  Fwd_GETX [0 ] 0
-IGMO  Fwd_GETS [0 ] 0
-IGMO  Fwd_DMA [0 ] 0
-IGMO  Own_GETX [0 ] 0
-IGMO  ExtAck [0 ] 0
-IGMO  All_Acks [43 ] 43
-IGMO  Exclusive_Unblock [43 ] 43
-IGMO  L2_Replacement [0 ] 0
-
-IGMIO  L1_GETS [0 ] 0
-IGMIO  L1_GETX [0 ] 0
-IGMIO  L1_PUTO [0 ] 0
-IGMIO  L1_PUTX [0 ] 0
-IGMIO  L1_PUTS_only [0 ] 0
-IGMIO  L1_PUTS [0 ] 0
-IGMIO  Fwd_GETX [0 ] 0
-IGMIO  Fwd_GETS [0 ] 0
-IGMIO  Fwd_DMA [0 ] 0
-IGMIO  Own_GETX [0 ] 0
-IGMIO  ExtAck [0 ] 0
-IGMIO  All_Acks [0 ] 0
-
-OGMIO  L1_GETS [0 ] 0
-OGMIO  L1_GETX [0 ] 0
-OGMIO  L1_PUTO [0 ] 0
-OGMIO  L1_PUTX [0 ] 0
-OGMIO  L1_PUTS_only [0 ] 0
-OGMIO  L1_PUTS [0 ] 0
-OGMIO  Fwd_GETX [0 ] 0
-OGMIO  Fwd_GETS [0 ] 0
-OGMIO  Fwd_DMA [0 ] 0
-OGMIO  Own_GETX [0 ] 0
-OGMIO  ExtAck [0 ] 0
-OGMIO  All_Acks [0 ] 0
-
-IGMIOF  L1_GETS [0 ] 0
-IGMIOF  L1_GETX [0 ] 0
-IGMIOF  L1_PUTO [0 ] 0
-IGMIOF  L1_PUTX [0 ] 0
-IGMIOF  L1_PUTS_only [0 ] 0
-IGMIOF  L1_PUTS [0 ] 0
-IGMIOF  IntAck [0 ] 0
-IGMIOF  All_Acks [0 ] 0
-IGMIOF  Data_Exclusive [0 ] 0
-
-IGMIOFS  L1_GETS [0 ] 0
-IGMIOFS  L1_GETX [0 ] 0
-IGMIOFS  L1_PUTO [0 ] 0
-IGMIOFS  L1_PUTX [0 ] 0
-IGMIOFS  L1_PUTS_only [0 ] 0
-IGMIOFS  L1_PUTS [0 ] 0
-IGMIOFS  Fwd_GETX [0 ] 0
-IGMIOFS  Fwd_GETS [0 ] 0
-IGMIOFS  Fwd_DMA [0 ] 0
-IGMIOFS  Inv [0 ] 0
-IGMIOFS  Data [0 ] 0
-IGMIOFS  L2_Replacement [0 ] 0
-
-OGMIOF  L1_GETS [0 ] 0
-OGMIOF  L1_GETX [0 ] 0
-OGMIOF  L1_PUTO [0 ] 0
-OGMIOF  L1_PUTX [0 ] 0
-OGMIOF  L1_PUTS_only [0 ] 0
-OGMIOF  L1_PUTS [0 ] 0
-OGMIOF  IntAck [0 ] 0
-OGMIOF  All_Acks [0 ] 0
-
-II  L1_GETS [0 ] 0
-II  L1_GETX [0 ] 0
-II  L1_PUTO [0 ] 0
-II  L1_PUTX [0 ] 0
-II  L1_PUTS_only [0 ] 0
-II  L1_PUTS [0 ] 0
-II  IntAck [0 ] 0
-II  All_Acks [0 ] 0
-
-MM  L1_GETS [0 ] 0
-MM  L1_GETX [0 ] 0
-MM  L1_PUTO [0 ] 0
-MM  L1_PUTX [0 ] 0
-MM  L1_PUTS_only [0 ] 0
-MM  L1_PUTS [0 ] 0
-MM  Fwd_GETX [0 ] 0
-MM  Fwd_GETS [0 ] 0
-MM  Fwd_DMA [0 ] 0
-MM  Inv [0 ] 0
-MM  Exclusive_Unblock [15 ] 15
-MM  L2_Replacement [0 ] 0
-
-SS  L1_GETS [0 ] 0
-SS  L1_GETX [0 ] 0
-SS  L1_PUTO [0 ] 0
-SS  L1_PUTX [0 ] 0
-SS  L1_PUTS_only [0 ] 0
-SS  L1_PUTS [0 ] 0
-SS  Fwd_GETX [0 ] 0
-SS  Fwd_GETS [0 ] 0
-SS  Fwd_DMA [0 ] 0
-SS  Inv [0 ] 0
-SS  Unblock [0 ] 0
-SS  L2_Replacement [0 ] 0
-
-OO  L1_GETS [0 ] 0
-OO  L1_GETX [0 ] 0
-OO  L1_PUTO [0 ] 0
-OO  L1_PUTX [0 ] 0
-OO  L1_PUTS_only [0 ] 0
-OO  L1_PUTS [0 ] 0
-OO  Fwd_GETX [0 ] 0
-OO  Fwd_GETS [0 ] 0
-OO  Fwd_DMA [0 ] 0
-OO  Inv [0 ] 0
-OO  Unblock [0 ] 0
-OO  Exclusive_Unblock [72 ] 72
-OO  L2_Replacement [0 ] 0
-
-OLSS  L1_GETS [0 ] 0
-OLSS  L1_GETX [0 ] 0
-OLSS  L1_PUTO [0 ] 0
-OLSS  L1_PUTX [0 ] 0
-OLSS  L1_PUTS_only [0 ] 0
-OLSS  L1_PUTS [0 ] 0
-OLSS  Fwd_GETX [0 ] 0
-OLSS  Fwd_GETS [0 ] 0
-OLSS  Fwd_DMA [0 ] 0
-OLSS  Inv [0 ] 0
-OLSS  Unblock [0 ] 0
-OLSS  L2_Replacement [0 ] 0
-
-OLSXS  L1_GETS [0 ] 0
-OLSXS  L1_GETX [0 ] 0
-OLSXS  L1_PUTO [0 ] 0
-OLSXS  L1_PUTX [0 ] 0
-OLSXS  L1_PUTS_only [0 ] 0
-OLSXS  L1_PUTS [0 ] 0
-OLSXS  Fwd_GETX [0 ] 0
-OLSXS  Fwd_GETS [0 ] 0
-OLSXS  Fwd_DMA [0 ] 0
-OLSXS  Inv [0 ] 0
-OLSXS  Unblock [0 ] 0
-OLSXS  L2_Replacement [0 ] 0
-
-SLSS  L1_GETS [0 ] 0
-SLSS  L1_GETX [0 ] 0
-SLSS  L1_PUTO [0 ] 0
-SLSS  L1_PUTX [0 ] 0
-SLSS  L1_PUTS_only [0 ] 0
-SLSS  L1_PUTS [0 ] 0
-SLSS  Fwd_GETX [0 ] 0
-SLSS  Fwd_GETS [0 ] 0
-SLSS  Fwd_DMA [0 ] 0
-SLSS  Inv [0 ] 0
-SLSS  Unblock [0 ] 0
-SLSS  L2_Replacement [0 ] 0
-
-OI  L1_GETS [0 ] 0
-OI  L1_GETX [0 ] 0
-OI  L1_PUTO [0 ] 0
-OI  L1_PUTX [0 ] 0
-OI  L1_PUTS_only [0 ] 0
-OI  L1_PUTS [0 ] 0
-OI  Fwd_GETX [0 ] 0
-OI  Fwd_GETS [0 ] 0
-OI  Fwd_DMA [0 ] 0
-OI  Writeback_Ack [0 ] 0
-OI  Writeback_Nack [0 ] 0
-OI  L2_Replacement [0 ] 0
-
-MI  L1_GETS [2 ] 2
-MI  L1_GETX [0 ] 0
-MI  L1_PUTO [0 ] 0
-MI  L1_PUTX [0 ] 0
-MI  L1_PUTS_only [0 ] 0
-MI  L1_PUTS [0 ] 0
-MI  Fwd_GETX [0 ] 0
-MI  Fwd_GETS [0 ] 0
-MI  Fwd_DMA [0 ] 0
-MI  Writeback_Ack [407 ] 407
-MI  L2_Replacement [0 ] 0
-
-MII  L1_GETS [0 ] 0
-MII  L1_GETX [0 ] 0
-MII  L1_PUTO [0 ] 0
-MII  L1_PUTX [0 ] 0
-MII  L1_PUTS_only [0 ] 0
-MII  L1_PUTS [0 ] 0
-MII  Writeback_Ack [0 ] 0
-MII  Writeback_Nack [0 ] 0
-MII  L2_Replacement [0 ] 0
-
-OLSI  L1_GETS [0 ] 0
-OLSI  L1_GETX [0 ] 0
-OLSI  L1_PUTO [0 ] 0
-OLSI  L1_PUTX [0 ] 0
-OLSI  L1_PUTS_only [0 ] 0
-OLSI  L1_PUTS [0 ] 0
-OLSI  Fwd_GETX [0 ] 0
-OLSI  Fwd_GETS [0 ] 0
-OLSI  Fwd_DMA [0 ] 0
-OLSI  Writeback_Ack [0 ] 0
-OLSI  L2_Replacement [0 ] 0
-
-ILSI  L1_GETS [0 ] 0
-ILSI  L1_GETX [0 ] 0
-ILSI  L1_PUTO [0 ] 0
-ILSI  L1_PUTX [0 ] 0
-ILSI  L1_PUTS_only [0 ] 0
-ILSI  L1_PUTS [0 ] 0
-ILSI  IntAck [0 ] 0
-ILSI  All_Acks [0 ] 0
-ILSI  Writeback_Ack [0 ] 0
-ILSI  L2_Replacement [0 ] 0
-
-ILOSD  L1_GETS [0 ] 0
-ILOSD  L1_GETX [0 ] 0
-ILOSD  L1_PUTO [0 ] 0
-ILOSD  L1_PUTX [0 ] 0
-ILOSD  L1_PUTS_only [0 ] 0
-ILOSD  L1_PUTS [0 ] 0
-ILOSD  Fwd_GETX [0 ] 0
-ILOSD  Fwd_GETS [0 ] 0
-ILOSD  Fwd_DMA [0 ] 0
-ILOSD  Own_GETX [0 ] 0
-ILOSD  Inv [0 ] 0
-ILOSD  DmaAck [0 ] 0
-ILOSD  L2_Replacement [0 ] 0
-
-ILOSXD  L1_GETS [0 ] 0
-ILOSXD  L1_GETX [0 ] 0
-ILOSXD  L1_PUTO [0 ] 0
-ILOSXD  L1_PUTX [0 ] 0
-ILOSXD  L1_PUTS_only [0 ] 0
-ILOSXD  L1_PUTS [0 ] 0
-ILOSXD  Fwd_GETX [0 ] 0
-ILOSXD  Fwd_GETS [0 ] 0
-ILOSXD  Fwd_DMA [0 ] 0
-ILOSXD  Own_GETX [0 ] 0
-ILOSXD  Inv [0 ] 0
-ILOSXD  DmaAck [0 ] 0
-ILOSXD  L2_Replacement [0 ] 0
-
-ILOD  L1_GETS [0 ] 0
-ILOD  L1_GETX [0 ] 0
-ILOD  L1_PUTO [0 ] 0
-ILOD  L1_PUTX [0 ] 0
-ILOD  L1_PUTS_only [0 ] 0
-ILOD  L1_PUTS [0 ] 0
-ILOD  Fwd_GETX [0 ] 0
-ILOD  Fwd_GETS [0 ] 0
-ILOD  Fwd_DMA [0 ] 0
-ILOD  Own_GETX [0 ] 0
-ILOD  Inv [0 ] 0
-ILOD  DmaAck [0 ] 0
-ILOD  L2_Replacement [0 ] 0
-
-ILXD  L1_GETS [0 ] 0
-ILXD  L1_GETX [0 ] 0
-ILXD  L1_PUTO [0 ] 0
-ILXD  L1_PUTX [0 ] 0
-ILXD  L1_PUTS_only [0 ] 0
-ILXD  L1_PUTS [0 ] 0
-ILXD  Fwd_GETX [0 ] 0
-ILXD  Fwd_GETS [0 ] 0
-ILXD  Fwd_DMA [0 ] 0
-ILXD  Own_GETX [0 ] 0
-ILXD  Inv [0 ] 0
-ILXD  DmaAck [0 ] 0
-ILXD  L2_Replacement [0 ] 0
-
-ILOXD  L1_GETS [0 ] 0
-ILOXD  L1_GETX [0 ] 0
-ILOXD  L1_PUTO [0 ] 0
-ILOXD  L1_PUTX [0 ] 0
-ILOXD  L1_PUTS_only [0 ] 0
-ILOXD  L1_PUTS [0 ] 0
-ILOXD  Fwd_GETX [0 ] 0
-ILOXD  Fwd_GETS [0 ] 0
-ILOXD  Fwd_DMA [0 ] 0
-ILOXD  Own_GETX [0 ] 0
-ILOXD  Inv [0 ] 0
-ILOXD  DmaAck [0 ] 0
-ILOXD  L2_Replacement [0 ] 0
-
-Memory controller: system.ruby.dir_cntrl0.memBuffer:
-  memory_total_requests: 499
-  memory_reads: 423
-  memory_writes: 76
-  memory_refreshes: 313
-  memory_total_request_delays: 77
-  memory_delays_per_request: 0.154309
-  memory_delays_in_input_queue: 0
-  memory_delays_behind_head_of_bank_queue: 0
-  memory_delays_stalled_at_head_of_bank_queue: 77
-  memory_stalls_for_bank_busy: 41
-  memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 9
-  memory_stalls_for_bus: 25
-  memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 2
-  memory_stalls_for_read_read_turnaround: 0
-  accesses_per_bank: 18  10  0  34  20  19  28  21  5  3  6  4  21  40  20  3  4  5  7  13  10  16  14  41  15  5  5  12  12  18  14  56  
-
- --- Directory ---
- - Event Counts -
-GETX [43 ] 43
-GETS [380 ] 380
-PUTX [407 ] 407
-PUTO [0 ] 0
-PUTO_SHARERS [0 ] 0
-Unblock [0 ] 0
-Last_Unblock [0 ] 0
-Exclusive_Unblock [422 ] 422
-Clean_Writeback [331 ] 331
-Dirty_Writeback [76 ] 76
-Memory_Data [423 ] 423
-Memory_Ack [76 ] 76
-DMA_READ [0 ] 0
-DMA_WRITE [0 ] 0
-DMA_ACK [0 ] 0
-Data [0 ] 0
-
- - Transitions -
-I  GETX [43 ] 43
-I  GETS [380 ] 380
-I  PUTX [0 ] 0
-I  PUTO [0 ] 0
-I  Memory_Data [0 ] 0
-I  Memory_Ack [74 ] 74
-I  DMA_READ [0 ] 0
-I  DMA_WRITE [0 ] 0
-
-S  GETX [0 ] 0
-S  GETS [0 ] 0
-S  PUTX [0 ] 0
-S  PUTO [0 ] 0
-S  Memory_Data [0 ] 0
-S  Memory_Ack [0 ] 0
-S  DMA_READ [0 ] 0
-S  DMA_WRITE [0 ] 0
-
-O  GETX [0 ] 0
-O  GETS [0 ] 0
-O  PUTX [0 ] 0
-O  PUTO [0 ] 0
-O  PUTO_SHARERS [0 ] 0
-O  Memory_Data [0 ] 0
-O  Memory_Ack [0 ] 0
-O  DMA_READ [0 ] 0
-O  DMA_WRITE [0 ] 0
-
-M  GETX [0 ] 0
-M  GETS [0 ] 0
-M  PUTX [407 ] 407
-M  PUTO [0 ] 0
-M  PUTO_SHARERS [0 ] 0
-M  Memory_Data [0 ] 0
-M  Memory_Ack [0 ] 0
-M  DMA_READ [0 ] 0
-M  DMA_WRITE [0 ] 0
-
-IS  GETX [0 ] 0
-IS  GETS [0 ] 0
-IS  PUTX [0 ] 0
-IS  PUTO [0 ] 0
-IS  PUTO_SHARERS [0 ] 0
-IS  Unblock [0 ] 0
-IS  Exclusive_Unblock [379 ] 379
-IS  Memory_Data [380 ] 380
-IS  Memory_Ack [2 ] 2
-IS  DMA_READ [0 ] 0
-IS  DMA_WRITE [0 ] 0
-
-SS  GETX [0 ] 0
-SS  GETS [0 ] 0
-SS  PUTX [0 ] 0
-SS  PUTO [0 ] 0
-SS  PUTO_SHARERS [0 ] 0
-SS  Unblock [0 ] 0
-SS  Last_Unblock [0 ] 0
-SS  Memory_Data [0 ] 0
-SS  Memory_Ack [0 ] 0
-SS  DMA_READ [0 ] 0
-SS  DMA_WRITE [0 ] 0
-
-OO  GETX [0 ] 0
-OO  GETS [0 ] 0
-OO  PUTX [0 ] 0
-OO  PUTO [0 ] 0
-OO  PUTO_SHARERS [0 ] 0
-OO  Unblock [0 ] 0
-OO  Last_Unblock [0 ] 0
-OO  Memory_Data [0 ] 0
-OO  Memory_Ack [0 ] 0
-OO  DMA_READ [0 ] 0
-OO  DMA_WRITE [0 ] 0
-
-MO  GETX [0 ] 0
-MO  GETS [0 ] 0
-MO  PUTX [0 ] 0
-MO  PUTO [0 ] 0
-MO  PUTO_SHARERS [0 ] 0
-MO  Unblock [0 ] 0
-MO  Exclusive_Unblock [0 ] 0
-MO  Memory_Data [0 ] 0
-MO  Memory_Ack [0 ] 0
-MO  DMA_READ [0 ] 0
-MO  DMA_WRITE [0 ] 0
-
-MM  GETX [0 ] 0
-MM  GETS [0 ] 0
-MM  PUTX [0 ] 0
-MM  PUTO [0 ] 0
-MM  PUTO_SHARERS [0 ] 0
-MM  Exclusive_Unblock [43 ] 43
-MM  Memory_Data [43 ] 43
-MM  Memory_Ack [0 ] 0
-MM  DMA_READ [0 ] 0
-MM  DMA_WRITE [0 ] 0
-
-
-MI  GETX [0 ] 0
-MI  GETS [0 ] 0
-MI  PUTX [0 ] 0
-MI  PUTO [0 ] 0
-MI  PUTO_SHARERS [0 ] 0
-MI  Unblock [0 ] 0
-MI  Clean_Writeback [331 ] 331
-MI  Dirty_Writeback [76 ] 76
-MI  Memory_Data [0 ] 0
-MI  Memory_Ack [0 ] 0
-MI  DMA_READ [0 ] 0
-MI  DMA_WRITE [0 ] 0
-
-MIS  GETX [0 ] 0
-MIS  GETS [0 ] 0
-MIS  PUTX [0 ] 0
-MIS  PUTO [0 ] 0
-MIS  PUTO_SHARERS [0 ] 0
-MIS  Unblock [0 ] 0
-MIS  Clean_Writeback [0 ] 0
-MIS  Dirty_Writeback [0 ] 0
-MIS  Memory_Data [0 ] 0
-MIS  Memory_Ack [0 ] 0
-MIS  DMA_READ [0 ] 0
-MIS  DMA_WRITE [0 ] 0
-
-OS  GETX [0 ] 0
-OS  GETS [0 ] 0
-OS  PUTX [0 ] 0
-OS  PUTO [0 ] 0
-OS  PUTO_SHARERS [0 ] 0
-OS  Unblock [0 ] 0
-OS  Clean_Writeback [0 ] 0
-OS  Dirty_Writeback [0 ] 0
-OS  Memory_Data [0 ] 0
-OS  Memory_Ack [0 ] 0
-OS  DMA_READ [0 ] 0
-OS  DMA_WRITE [0 ] 0
-
-OSS  GETX [0 ] 0
-OSS  GETS [0 ] 0
-OSS  PUTX [0 ] 0
-OSS  PUTO [0 ] 0
-OSS  PUTO_SHARERS [0 ] 0
-OSS  Unblock [0 ] 0
-OSS  Clean_Writeback [0 ] 0
-OSS  Dirty_Writeback [0 ] 0
-OSS  Memory_Data [0 ] 0
-OSS  Memory_Ack [0 ] 0
-OSS  DMA_READ [0 ] 0
-OSS  DMA_WRITE [0 ] 0
-
-XI_M  GETX [0 ] 0
-XI_M  GETS [0 ] 0
-XI_M  PUTX [0 ] 0
-XI_M  PUTO [0 ] 0
-XI_M  PUTO_SHARERS [0 ] 0
-XI_M  Memory_Data [0 ] 0
-XI_M  Memory_Ack [0 ] 0
-XI_M  DMA_READ [0 ] 0
-XI_M  DMA_WRITE [0 ] 0
-
-XI_U  GETX [0 ] 0
-XI_U  GETS [0 ] 0
-XI_U  PUTX [0 ] 0
-XI_U  PUTO [0 ] 0
-XI_U  PUTO_SHARERS [0 ] 0
-XI_U  Exclusive_Unblock [0 ] 0
-XI_U  Memory_Ack [0 ] 0
-XI_U  DMA_READ [0 ] 0
-XI_U  DMA_WRITE [0 ] 0
-
-OI_D  GETX [0 ] 0
-OI_D  GETS [0 ] 0
-OI_D  PUTX [0 ] 0
-OI_D  PUTO [0 ] 0
-OI_D  PUTO_SHARERS [0 ] 0
-OI_D  DMA_READ [0 ] 0
-OI_D  DMA_WRITE [0 ] 0
-OI_D  Data [0 ] 0
-
-OD  GETX [0 ] 0
-OD  GETS [0 ] 0
-OD  PUTX [0 ] 0
-OD  PUTO [0 ] 0
-OD  PUTO_SHARERS [0 ] 0
-OD  DMA_READ [0 ] 0
-OD  DMA_WRITE [0 ] 0
-OD  DMA_ACK [0 ] 0
-
-MD  GETX [0 ] 0
-MD  GETS [0 ] 0
-MD  PUTX [0 ] 0
-MD  PUTO [0 ] 0
-MD  PUTO_SHARERS [0 ] 0
-MD  DMA_READ [0 ] 0
-MD  DMA_WRITE [0 ] 0
-MD  DMA_ACK [0 ] 0
-
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 8f2c45ec9..fd5d57f08 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000045                       # Nu
 sim_ticks                                       44968                       # Number of ticks simulated
 final_tick                                      44968                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  13243                       # Simulator instruction rate (inst/s)
-host_op_rate                                    13241                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 231036                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 152316                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                  16391                       # Simulator instruction rate (inst/s)
+host_op_rate                                    16389                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 285944                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 146540                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.ruby.l2_cntrl0.L2cache.demand_hits           87                       # Number of cache demand hits
@@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709
 system.ruby.l1_cntrl0.L1Icache.demand_hits         2315                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses          270                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
+system.ruby.dir_cntrl0.memBuffer.memReq           499                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          423                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite           76                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh          313                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles           77                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls           77                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.154309                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy           41                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy           25                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy            2                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait            9                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          18      3.61%      3.61% |          10      2.00%      5.61% |           0      0.00%      5.61% |          34      6.81%     12.42% |          20      4.01%     16.43% |          19      3.81%     20.24% |          28      5.61%     25.85% |          21      4.21%     30.06% |           5      1.00%     31.06% |           3      0.60%     31.66% |           6      1.20%     32.87% |           4      0.80%     33.67% |          21      4.21%     37.88% |          40      8.02%     45.89% |          20      4.01%     49.90% |           3      0.60%     50.50% |           4      0.80%     51.30% |           5      1.00%     52.30% |           7      1.40%     53.71% |          13      2.61%     56.31% |          10      2.00%     58.32% |          16      3.21%     61.52% |          14      2.81%     64.33% |          41      8.22%     72.55% |          15      3.01%     75.55% |           5      1.00%     76.55% |           5      1.00%     77.56% |          12      2.40%     79.96% |          12      2.40%     82.36% |          18      3.61%     85.97% |          14      2.81%     88.78% |          56     11.22%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total          499                       # Number of accesses per bank
+
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -75,5 +89,82 @@ system.cpu.num_idle_cycles                          0                       # Nu
 system.cpu.num_busy_cycles                      44968                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.ruby.l2_cntrl0.L1_GETS                     454      0.00%      0.00%
+system.ruby.l2_cntrl0.L1_GETX                      58      0.00%      0.00%
+system.ruby.l2_cntrl0.L1_PUTX                     502      0.00%      0.00%
+system.ruby.l2_cntrl0.All_Acks                     43      0.00%      0.00%
+system.ruby.l2_cntrl0.Data                         43      0.00%      0.00%
+system.ruby.l2_cntrl0.Data_Exclusive              380      0.00%      0.00%
+system.ruby.l2_cntrl0.L1_WBCLEANDATA              396      0.00%      0.00%
+system.ruby.l2_cntrl0.L1_WBDIRTYDATA              106      0.00%      0.00%
+system.ruby.l2_cntrl0.Writeback_Ack               407      0.00%      0.00%
+system.ruby.l2_cntrl0.Exclusive_Unblock           510      0.00%      0.00%
+system.ruby.l2_cntrl0.L2_Replacement              407      0.00%      0.00%
+system.ruby.l2_cntrl0.NP.L1_GETS                  380      0.00%      0.00%
+system.ruby.l2_cntrl0.NP.L1_GETX                   43      0.00%      0.00%
+system.ruby.l2_cntrl0.ILX.L1_PUTX                 502      0.00%      0.00%
+system.ruby.l2_cntrl0.M.L1_GETS                    72      0.00%      0.00%
+system.ruby.l2_cntrl0.M.L1_GETX                    15      0.00%      0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement            407      0.00%      0.00%
+system.ruby.l2_cntrl0.ILXW.L1_WBCLEANDATA          396      0.00%      0.00%
+system.ruby.l2_cntrl0.ILXW.L1_WBDIRTYDATA          106      0.00%      0.00%
+system.ruby.l2_cntrl0.IGS.Data_Exclusive          380      0.00%      0.00%
+system.ruby.l2_cntrl0.IGS.Exclusive_Unblock          380      0.00%      0.00%
+system.ruby.l2_cntrl0.IGM.Data                     43      0.00%      0.00%
+system.ruby.l2_cntrl0.IGMO.All_Acks                43      0.00%      0.00%
+system.ruby.l2_cntrl0.IGMO.Exclusive_Unblock           43      0.00%      0.00%
+system.ruby.l2_cntrl0.MM.Exclusive_Unblock           15      0.00%      0.00%
+system.ruby.l2_cntrl0.OO.Exclusive_Unblock           72      0.00%      0.00%
+system.ruby.l2_cntrl0.MI.L1_GETS                    2      0.00%      0.00%
+system.ruby.l2_cntrl0.MI.Writeback_Ack            407      0.00%      0.00%
+system.ruby.l1_cntrl0.Load                        415      0.00%      0.00%
+system.ruby.l1_cntrl0.Ifetch                     2585      0.00%      0.00%
+system.ruby.l1_cntrl0.Store                       294      0.00%      0.00%
+system.ruby.l1_cntrl0.L1_Replacement              506      0.00%      0.00%
+system.ruby.l1_cntrl0.Exclusive_Data              510      0.00%      0.00%
+system.ruby.l1_cntrl0.Writeback_Ack_Data          502      0.00%      0.00%
+system.ruby.l1_cntrl0.All_acks                     58      0.00%      0.00%
+system.ruby.l1_cntrl0.Use_Timeout                 509      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Load                      182      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Ifetch                    270      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Store                      58      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Load                       82      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Ifetch                   1220      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Store                      33      0.00%      0.00%
+system.ruby.l1_cntrl0.M.L1_Replacement            406      0.00%      0.00%
+system.ruby.l1_cntrl0.M_W.Load                     49      0.00%      0.00%
+system.ruby.l1_cntrl0.M_W.Ifetch                 1095      0.00%      0.00%
+system.ruby.l1_cntrl0.M_W.Store                     7      0.00%      0.00%
+system.ruby.l1_cntrl0.M_W.L1_Replacement            4      0.00%      0.00%
+system.ruby.l1_cntrl0.M_W.Use_Timeout             444      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.Load                      99      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.Store                    114      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.L1_Replacement            96      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_W.Load                     3      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_W.Store                   82      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_W.Use_Timeout             65      0.00%      0.00%
+system.ruby.l1_cntrl0.IM.Exclusive_Data            58      0.00%      0.00%
+system.ruby.l1_cntrl0.OM.All_acks                  58      0.00%      0.00%
+system.ruby.l1_cntrl0.IS.Exclusive_Data           452      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Writeback_Ack_Data          502      0.00%      0.00%
+system.ruby.dir_cntrl0.GETX                        43      0.00%      0.00%
+system.ruby.dir_cntrl0.GETS                       380      0.00%      0.00%
+system.ruby.dir_cntrl0.PUTX                       407      0.00%      0.00%
+system.ruby.dir_cntrl0.Exclusive_Unblock          422      0.00%      0.00%
+system.ruby.dir_cntrl0.Clean_Writeback            331      0.00%      0.00%
+system.ruby.dir_cntrl0.Dirty_Writeback             76      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Data                423      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Ack                  76      0.00%      0.00%
+system.ruby.dir_cntrl0.I.GETX                      43      0.00%      0.00%
+system.ruby.dir_cntrl0.I.GETS                     380      0.00%      0.00%
+system.ruby.dir_cntrl0.I.Memory_Ack                74      0.00%      0.00%
+system.ruby.dir_cntrl0.M.PUTX                     407      0.00%      0.00%
+system.ruby.dir_cntrl0.IS.Exclusive_Unblock          379      0.00%      0.00%
+system.ruby.dir_cntrl0.IS.Memory_Data             380      0.00%      0.00%
+system.ruby.dir_cntrl0.IS.Memory_Ack                2      0.00%      0.00%
+system.ruby.dir_cntrl0.MM.Exclusive_Unblock           43      0.00%      0.00%
+system.ruby.dir_cntrl0.MM.Memory_Data              43      0.00%      0.00%
+system.ruby.dir_cntrl0.MI.Clean_Writeback          331      0.00%      0.00%
+system.ruby.dir_cntrl0.MI.Dirty_Writeback           76      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------