stats: Update Ruby regressions for memory controller fix

4 files changed, 75 insertions, 69 deletions

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index e62cfb199..2e8369b1e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
 boot_osflags=a
+clock=1
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -47,7 +48,6 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
-phase=0
 profile=0
 progress_interval=0
 system=system
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -118,9 +118,9 @@ bank_busy_time=11
 bank_queue_size=12
 banks_per_rank=8
 basic_bus_busy_time=2
+clock=3
 dimm_bit_0=12
 dimms_per_channel=2
-mem_bus_cycle_multiplier=10
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -129,6 +129,7 @@ rank_rank_delay=1
 ranks_per_dimm=2
 read_write_delay=2
 refresh_period=1560
+ruby_system=system.ruby
 tFaw=0
 version=0
 
@@ -180,6 +181,7 @@ tagArrayBanks=1
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
 access_phys_mem=true
+clock=1
 dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
@@ -223,6 +225,7 @@ tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
+clock=1
 conf_table_reported=false
 file=
 in_addr_map=true
@@ -347,6 +350,7 @@ ruby_system=system.ruby
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
+clock=1
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 8dafccdfe..9e474b916 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Jul/10/2012 17:37:10
+Real time: Sep/01/2012 14:11:29
 
 Profiler Stats
 --------------
@@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.48
-Virtual_time_in_minutes: 0.008
-Virtual_time_in_hours:   0.000133333
-Virtual_time_in_days:    5.55556e-06
+Virtual_time_in_seconds: 0.43
+Virtual_time_in_minutes: 0.00716667
+Virtual_time_in_hours:   0.000119444
+Virtual_time_in_days:    4.97685e-06
 
-Ruby_current_time: 85418
+Ruby_current_time: 44968
 Ruby_start_time: 0
-Ruby_cycles: 85418
+Ruby_cycles: 44968
 
-mbytes_resident: 45.4062
-mbytes_total: 228.586
-resident_ratio: 0.198657
+mbytes_resident: 46.9961
+mbytes_total: 257.863
+resident_ratio: 0.182313
 
-ruby_cycles_executed: [ 85419 ]
+ruby_cycles_executed: [ 44969 ]
 
 Busy Controller Counts:
 L2Cache-0:0  
@@ -34,11 +34,11 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average:     1 |
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 2 max: 281 count: 3294 average: 24.9314 | standard deviation: 56.0488 | 0 2784 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 91 84 78 63 5 2 2 1 3 3 0 2 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 277 count: 415 average: 60.9277 | standard deviation: 78.686 | 0 233 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 41 19 25 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 245 count: 294 average: 28.5238 | standard deviation: 59.597 | 0 236 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 3 12 7 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 281 count: 2585 average: 18.7439 | standard deviation: 48.5885 | 0 2315 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 57 40 47 31 2 2 2 1 3 2 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_NULL: [binsize: 2 max: 281 count: 3294 average: 24.9314 | standard deviation: 56.0488 | 0 2784 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 91 84 78 63 5 2 2 1 3 3 0 2 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 1 max: 115 count: 3294 average: 12.6515 | standard deviation: 24.0471 | 0 0 0 2784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126 124 112 20 18 9 5 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD: [binsize: 1 max: 115 count: 415 average: 28.8699 | standard deviation: 33.4854 | 0 0 0 233 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 44 27 6 0 2 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_ST: [binsize: 1 max: 82 count: 294 average: 14.5476 | standard deviation: 25.7644 | 0 0 0 236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 10 12 1 0 0 0 1 ]
+miss_latency_IFETCH: [binsize: 1 max: 101 count: 2585 average: 9.83211 | standard deviation: 20.7704 | 0 0 0 2315 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 80 66 4 6 6 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_NULL: [binsize: 1 max: 115 count: 3294 average: 12.6515 | standard deviation: 24.0471 | 0 0 0 2784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126 124 112 20 18 9 5 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 0
-miss_latency_LD_NULL: [binsize: 2 max: 277 count: 415 average: 60.9277 | standard deviation: 78.686 | 0 233 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 41 19 25 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_NULL: [binsize: 2 max: 245 count: 294 average: 28.5238 | standard deviation: 59.597 | 0 236 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 3 12 7 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_NULL: [binsize: 2 max: 281 count: 2585 average: 18.7439 | standard deviation: 48.5885 | 0 2315 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 57 40 47 31 2 2 2 1 3 2 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_NULL: [binsize: 1 max: 115 count: 415 average: 28.8699 | standard deviation: 33.4854 | 0 0 0 233 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 44 27 6 0 2 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_ST_NULL: [binsize: 1 max: 82 count: 294 average: 14.5476 | standard deviation: 25.7644 | 0 0 0 236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 10 12 1 0 0 0 1 ]
+miss_latency_IFETCH_NULL: [binsize: 1 max: 101 count: 2585 average: 9.83211 | standard deviation: 20.7704 | 0 0 0 2315 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 80 66 4 6 6 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -83,11 +83,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12740
+page_reclaims: 9533
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 80
 
 Network Stats
 -------------
@@ -102,9 +102,9 @@ total_msgs: 16577 total_bytes: 422728
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 5.15524
-  links_utilized_percent_switch_0_link_0: 6.00225 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 4.30823 bw: 16000 base_latency: 1
+links_utilized_percent_switch_0: 9.79252
+  links_utilized_percent_switch_0_link_0: 11.4014 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 8.1836 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_0_link_0_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_0_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1
@@ -120,9 +120,9 @@ links_utilized_percent_switch_0: 5.15524
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 3.2581
-  links_utilized_percent_switch_1_link_0: 2.98064 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 3.53555 bw: 16000 base_latency: 1
+links_utilized_percent_switch_1: 6.18885
+  links_utilized_percent_switch_1_link_0: 5.6618 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 6.71589 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_1_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 87 6264 [ 0 0 87 0 0 0 0 0 0 0 ] base_latency: 1
@@ -134,9 +134,9 @@ links_utilized_percent_switch_1: 3.2581
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 1.89685
-  links_utilized_percent_switch_2_link_0: 1.327 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 2.46669 bw: 16000 base_latency: 1
+links_utilized_percent_switch_2: 3.60312
+  links_utilized_percent_switch_2_link_0: 2.52068 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 4.68555 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_2_link_0_Request_Control: 423 3384 [ 0 423 0 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_0_Writeback_Data: 76 5472 [ 0 0 76 0 0 0 0 0 0 0 ] base_latency: 1
@@ -147,10 +147,10 @@ links_utilized_percent_switch_2: 1.89685
 
 switch_3_inlinks: 3
 switch_3_outlinks: 3
-links_utilized_percent_switch_3: 3.43682
-  links_utilized_percent_switch_3_link_0: 6.00225 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 2.98064 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_3_link_2: 1.32759 bw: 16000 base_latency: 1
+links_utilized_percent_switch_3: 6.52835
+  links_utilized_percent_switch_3_link_0: 11.4014 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 5.6618 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_2: 2.52179 bw: 16000 base_latency: 1
 
   outgoing_messages_switch_3_link_0_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1
@@ -1199,19 +1199,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 499
   memory_reads: 423
   memory_writes: 76
-  memory_refreshes: 178
-  memory_total_request_delays: 116
-  memory_delays_per_request: 0.232465
-  memory_delays_in_input_queue: 2
+  memory_refreshes: 313
+  memory_total_request_delays: 77
+  memory_delays_per_request: 0.154309
+  memory_delays_in_input_queue: 0
   memory_delays_behind_head_of_bank_queue: 0
-  memory_delays_stalled_at_head_of_bank_queue: 114
-  memory_stalls_for_bank_busy: 56
+  memory_delays_stalled_at_head_of_bank_queue: 77
+  memory_stalls_for_bank_busy: 41
   memory_stalls_for_random_busy: 0
   memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 10
+  memory_stalls_for_arbitration: 9
   memory_stalls_for_bus: 25
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 23
+  memory_stalls_for_read_write_turnaround: 2
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 18  10  0  34  20  19  28  21  5  3  6  4  21  40  20  3  4  5  7  13  10  16  14  41  15  5  5  12  12  18  14  56  
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 6a5f96ccf..0eff99821 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 28 2012 11:32:56
-gem5 started Jul 28 2012 11:35:53
-gem5 executing on zizzer
+gem5 compiled Sep  1 2012 14:10:16
+gem5 started Sep  1 2012 14:11:29
+gem5 executing on doudou.cs.wisc.edu
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 85418 because target called exit()
+Exiting @ tick 44968 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 2737629f8..b192d2700 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000085                       # Number of seconds simulated
-sim_ticks                                       85418                       # Number of ticks simulated
-final_tick                                      85418                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000045                       # Number of seconds simulated
+sim_ticks                                       44968                       # Number of ticks simulated
+final_tick                                      44968                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   1284                       # Simulator instruction rate (inst/s)
-host_op_rate                                     1284                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                  42571                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232824                       # Number of bytes of host memory used
-host_seconds                                     2.01                       # Real time elapsed on the host
+host_inst_rate                                  22673                       # Simulator instruction rate (inst/s)
+host_op_rate                                    22668                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 395469                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264056                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
@@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data                415                       # Nu
 system.physmem.num_reads::total                  3000                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               294                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  294                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            121051769                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             35308717                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               156360486                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       121051769                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          121051769                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data            24093282                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               24093282                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           121051769                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            59402000                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              180453769                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            229941292                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             67069916                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               297011208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       229941292                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          229941292                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            45765878                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45765878                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           229941292                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           112835794                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              342777086                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -84,7 +84,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            85418                       # number of cpu cycles simulated
+system.cpu.numCycles                            44968                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2577                       # Number of instructions committed
@@ -103,7 +103,7 @@ system.cpu.num_mem_refs                           717                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      85418                       # Number of busy cycles
+system.cpu.num_busy_cycles                      44968                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles