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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-14 10:20:16 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-14 10:20:16 -0600 |
| commit | 7fdcfdf08b9d654fcf311b213bd729cb957f822c (patch) | |
| tree | 3802f7a39be28c297875b4afcbe7bf9f189f8457 /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt | |
| parent | 3137557cadf0635c7593a4fb6c37d903d3048c13 (diff) | |
| download | gem5-7fdcfdf08b9d654fcf311b213bd729cb957f822c.tar.xz | |
regressions: update stats due to changes in ruby obj hierarchy
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 1cfc617f8..cef9f9d78 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000043 # Nu sim_ticks 43073 # Number of ticks simulated final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22520 # Simulator instruction rate (inst/s) -host_op_rate 22517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 376297 # Simulator tick rate (ticks/s) -host_mem_usage 231852 # Number of bytes of host memory used +host_inst_rate 22783 # Simulator instruction rate (inst/s) +host_op_rate 22779 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 380677 # Simulator tick rate (ticks/s) +host_mem_usage 279892 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -33,24 +33,24 @@ system.physmem.bw_write::total 47779351 # Wr system.physmem.bw_total::cpu.inst 240057577 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 117800014 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 357857591 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads +system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes +system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads +system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes +system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.ruby.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads +system.ruby.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes +system.ruby.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.ruby.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.ruby.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.ruby.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.ruby.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads +system.ruby.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes +system.ruby.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.ruby.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.ruby.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.ruby.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv |