stats: updates due to changes to ruby

Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.

2 files changed, 53 insertions, 144 deletions

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index 819d00fb8..4ce431f90 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Mar/06/2013 20:31:07
+Real time: Jun/08/2013 13:43:10
 
 Profiler Stats
 --------------
@@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours:   0.000141667
-Virtual_time_in_days:    5.90278e-06
+Virtual_time_in_seconds: 0.44
+Virtual_time_in_minutes: 0.00733333
+Virtual_time_in_hours:   0.000122222
+Virtual_time_in_days:    5.09259e-06
 
 Ruby_current_time: 52498
 Ruby_start_time: 0
 Ruby_cycles: 52498
 
-mbytes_resident: 53.0938
-mbytes_total: 145.422
-resident_ratio: 0.365182
-
-ruby_cycles_executed: [ 52499 ]
+mbytes_resident: 53.0039
+mbytes_total: 140.805
+resident_ratio: 0.376491
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -64,7 +62,6 @@ Request vs. RubySystem State Profile
 --------------------------------
 
 
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 
 Message Delayed Cycles
 ----------------------
@@ -85,10 +82,10 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10892
+page_reclaims: 11286
 page_faults: 0
 swaps: 0
-block_inputs: 1328
+block_inputs: 0
 block_outputs: 88
 
 Network Stats
@@ -133,129 +130,3 @@ links_utilized_percent_switch_2: 5.94308
   outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
 
- --- L1Cache ---
- - Event Counts -
-Load [415 ] 415
-Ifetch [2585 ] 2585
-Store [294 ] 294
-Data [626 ] 626
-Fwd_GETX [0 ] 0
-Inv [0 ] 0
-Replacement [622 ] 622
-Writeback_Ack [622 ] 622
-Writeback_Nack [0 ] 0
-
- - Transitions -
-I  Load [245 ] 245
-I  Ifetch [297 ] 297
-I  Store [84 ] 84
-I  Inv [0 ] 0
-I  Replacement [0 ] 0
-
-II  Writeback_Nack [0 ] 0
-
-M  Load [170 ] 170
-M  Ifetch [2288 ] 2288
-M  Store [210 ] 210
-M  Fwd_GETX [0 ] 0
-M  Inv [0 ] 0
-M  Replacement [622 ] 622
-
-MI  Fwd_GETX [0 ] 0
-MI  Inv [0 ] 0
-MI  Writeback_Ack [622 ] 622
-MI  Writeback_Nack [0 ] 0
-
-MII  Fwd_GETX [0 ] 0
-
-IS  Data [542 ] 542
-
-IM  Data [84 ] 84
-
-Memory controller: system.ruby.dir_cntrl0.memBuffer:
-  memory_total_requests: 1248
-  memory_reads: 626
-  memory_writes: 622
-  memory_refreshes: 365
-  memory_total_request_delays: 915
-  memory_delays_per_request: 0.733173
-  memory_delays_in_input_queue: 0
-  memory_delays_behind_head_of_bank_queue: 0
-  memory_delays_stalled_at_head_of_bank_queue: 915
-  memory_stalls_for_bank_busy: 352
-  memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 40
-  memory_stalls_for_bus: 497
-  memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 26
-  memory_stalls_for_read_read_turnaround: 0
-  accesses_per_bank: 55  40  0  100  42  42  88  45  14  10  14  10  46  82  38  6  22  14  14  48  20  52  26  92  34  10  12  24  28  44  38  138  
-
- --- Directory ---
- - Event Counts -
-GETX [626 ] 626
-GETS [0 ] 0
-PUTX [622 ] 622
-PUTX_NotOwner [0 ] 0
-DMA_READ [0 ] 0
-DMA_WRITE [0 ] 0
-Memory_Data [626 ] 626
-Memory_Ack [622 ] 622
-
- - Transitions -
-I  GETX [626 ] 626
-I  PUTX_NotOwner [0 ] 0
-I  DMA_READ [0 ] 0
-I  DMA_WRITE [0 ] 0
-
-M  GETX [0 ] 0
-M  PUTX [622 ] 622
-M  PUTX_NotOwner [0 ] 0
-M  DMA_READ [0 ] 0
-M  DMA_WRITE [0 ] 0
-
-M_DRD  GETX [0 ] 0
-M_DRD  PUTX [0 ] 0
-
-M_DWR  GETX [0 ] 0
-M_DWR  PUTX [0 ] 0
-
-M_DWRI  GETX [0 ] 0
-M_DWRI  Memory_Ack [0 ] 0
-
-M_DRDI  GETX [0 ] 0
-M_DRDI  Memory_Ack [0 ] 0
-
-IM  GETX [0 ] 0
-IM  GETS [0 ] 0
-IM  PUTX [0 ] 0
-IM  PUTX_NotOwner [0 ] 0
-IM  DMA_READ [0 ] 0
-IM  DMA_WRITE [0 ] 0
-IM  Memory_Data [626 ] 626
-
-MI  GETX [0 ] 0
-MI  GETS [0 ] 0
-MI  PUTX [0 ] 0
-MI  PUTX_NotOwner [0 ] 0
-MI  DMA_READ [0 ] 0
-MI  DMA_WRITE [0 ] 0
-MI  Memory_Ack [622 ] 622
-
-ID  GETX [0 ] 0
-ID  GETS [0 ] 0
-ID  PUTX [0 ] 0
-ID  PUTX_NotOwner [0 ] 0
-ID  DMA_READ [0 ] 0
-ID  DMA_WRITE [0 ] 0
-ID  Memory_Data [0 ] 0
-
-ID_W  GETX [0 ] 0
-ID_W  GETS [0 ] 0
-ID_W  PUTX [0 ] 0
-ID_W  PUTX_NotOwner [0 ] 0
-ID_W  DMA_READ [0 ] 0
-ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack [0 ] 0
-
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 98abd69d6..408d1d326 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -4,16 +4,30 @@ sim_seconds                                  0.000052                       # Nu
 sim_ticks                                       52498                       # Number of ticks simulated
 final_tick                                      52498                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   9649                       # Simulator instruction rate (inst/s)
-host_op_rate                                     9649                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 196549                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 151788                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
+host_inst_rate                                  30872                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30864                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 628609                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 144188                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         2668                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses          626                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         3294                       # Number of cache demand accesses
+system.ruby.dir_cntrl0.memBuffer.memReq          1248                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          626                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite          622                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh          365                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles          915                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls          915                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.733173                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          352                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy          497                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           26                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait           40                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          55      4.41%      4.41% |          40      3.21%      7.61% |           0      0.00%      7.61% |         100      8.01%     15.62% |          42      3.37%     18.99% |          42      3.37%     22.36% |          88      7.05%     29.41% |          45      3.61%     33.01% |          14      1.12%     34.13% |          10      0.80%     34.94% |          14      1.12%     36.06% |          10      0.80%     36.86% |          46      3.69%     40.54% |          82      6.57%     47.12% |          38      3.04%     50.16% |           6      0.48%     50.64% |          22      1.76%     52.40% |          14      1.12%     53.53% |          14      1.12%     54.65% |          48      3.85%     58.49% |          20      1.60%     60.10% |          52      4.17%     64.26% |          26      2.08%     66.35% |          92      7.37%     73.72% |          34      2.72%     76.44% |          10      0.80%     77.24% |          12      0.96%     78.21% |          24      1.92%     80.13% |          28      2.24%     82.37% |          44      3.53%     85.90% |          38      3.04%     88.94% |         138     11.06%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1248                       # Number of accesses per bank
+
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -69,5 +83,29 @@ system.cpu.num_idle_cycles                          0                       # Nu
 system.cpu.num_busy_cycles                      52498                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.ruby.l1_cntrl0.Load                        415      0.00%      0.00%
+system.ruby.l1_cntrl0.Ifetch                     2585      0.00%      0.00%
+system.ruby.l1_cntrl0.Store                       294      0.00%      0.00%
+system.ruby.l1_cntrl0.Data                        626      0.00%      0.00%
+system.ruby.l1_cntrl0.Replacement                 622      0.00%      0.00%
+system.ruby.l1_cntrl0.Writeback_Ack               622      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Load                      245      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Ifetch                    297      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Store                      84      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Load                      170      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Ifetch                   2288      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Store                     210      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Replacement               622      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Writeback_Ack            622      0.00%      0.00%
+system.ruby.l1_cntrl0.IS.Data                     542      0.00%      0.00%
+system.ruby.l1_cntrl0.IM.Data                      84      0.00%      0.00%
+system.ruby.dir_cntrl0.GETX                       626      0.00%      0.00%
+system.ruby.dir_cntrl0.PUTX                       622      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Data                626      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Ack                 622      0.00%      0.00%
+system.ruby.dir_cntrl0.I.GETX                     626      0.00%      0.00%
+system.ruby.dir_cntrl0.M.PUTX                     622      0.00%      0.00%
+system.ruby.dir_cntrl0.IM.Memory_Data             626      0.00%      0.00%
+system.ruby.dir_cntrl0.MI.Memory_Ack              622      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------