diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2016-11-17 04:54:14 -0500 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-11-17 04:54:14 -0500 |
commit | 6ed567d6002df081dd6cf2db6685d3e66c11272b (patch) | |
tree | d6df4c0abaf10391c9ca9fb9dfc833737c979e37 /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt | |
parent | 74249f80df4e6128da38dfb5dbf5f61285c673a2 (diff) | |
download | gem5-6ed567d6002df081dd6cf2db6685d3e66c11272b.tar.xz |
alpha: Remove ALPHA tru64 support and associated tests
No one appears to be using it, and it is causing build issues
and increases the development and maintenance effort.
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt')
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt | 519 |
1 files changed, 0 insertions, 519 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index 55cc07d2c..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,519 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18484500 # Number of ticks simulated -final_tick 18484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 287292 # Simulator instruction rate (inst/s) -host_op_rate 286342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2049000197 # Simulator tick rate (ticks/s) -host_mem_usage 250420 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory -system.physmem.bytes_read::total 15680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory -system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 564364738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283913549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 848278287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 564364738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 564364738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 564364738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283913549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 848278287 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 18484500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 36969 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 36969 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.258408 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.258408 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011538 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011538 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits -system.cpu.dcache.overall_hits::total 627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses -system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1701000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1701000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 5166000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 5166000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 5166000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 5166000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5084000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5084000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 79.631047 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 79.631047 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.038882 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.038882 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5335 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits -system.cpu.icache.overall_hits::total 2423 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses -system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10269500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10269500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10269500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10269500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10269500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10269500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63003.067485 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63003.067485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63003.067485 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10106500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10106500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10106500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10106500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10106500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10106500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62003.067485 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62003.067485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 127.028625 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 245 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.723638 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.304987 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001444 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003877 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 245 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007477 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 163 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses -system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1633500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1633500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9862000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 9862000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9862000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4961000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14823000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9862000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4961000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14823000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 163 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60502.040816 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60502.040816 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 163 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 163 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1363500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1363500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8232000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8232000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8232000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4141000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12373000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8232000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4141000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12373000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 218 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 218 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 245 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245 # Request fanout histogram -system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |