diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
commit | f3585c841e964c98911784a187fc4f081a02a0a6 (patch) | |
tree | 2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf /tests/quick/se/00.hello/ref/alpha/tru64/simple-timing | |
parent | cfc4a999828a5b51f4c514e3a7c47b4eebc450b9 (diff) | |
download | gem5-f3585c841e964c98911784a187fc4f081a02a0a6.tar.xz |
stats: update stats for cache occupancy and clock domain changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing')
4 files changed, 59 insertions, 12 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 81f228137..7ab4d5c2a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -147,6 +165,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +174,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +189,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +217,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -207,11 +232,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +251,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +261,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr index 31ae36f2e..32998f270 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index f5b60c70f..cd7b05e76 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:38 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:26 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 0eefef01d..3fc7cd393 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70 # Simulator instruction rate (inst/s) -host_op_rate 70 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 446596 # Simulator tick rate (ticks/s) -host_mem_usage 222964 # Number of bytes of host memory used -host_seconds 37.00 # Real time elapsed on the host +host_inst_rate 33204 # Simulator instruction rate (inst/s) +host_op_rate 33192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 212757424 # Simulator tick rate (ticks/s) +host_mem_usage 228444 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory system.physmem.bytes_read::total 15680 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 245000 # La system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 13.3 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -106,6 +109,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5335 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -186,6 +195,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses @@ -303,6 +318,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits |