Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

1 files changed, 60 insertions, 60 deletions

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index aabb78aae..83ebc2ad9 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000018                       # Number of seconds simulated
-sim_ticks                                    17541000                       # Number of ticks simulated
-final_tick                                   17541000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000017                       # Number of seconds simulated
+sim_ticks                                    16524000                       # Number of ticks simulated
+final_tick                                   16524000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 207586                       # Simulator instruction rate (inst/s)
-host_op_rate                                   207300                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1409208031                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216876                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  93431                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93371                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              598358642                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217312                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             10432                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           10432                       # Nu
 system.physmem.num_reads::cpu.inst                163                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 82                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   245                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            594720940                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            299184767                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               893905707                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       594720940                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          594720940                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           594720940                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           299184767                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              893905707                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            631324135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            317598644                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               948922779                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       631324135                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          631324135                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           631324135                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           317598644                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              948922779                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -60,7 +60,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            35082                       # number of cpu cycles simulated
+system.cpu.numCycles                            33048                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2577                       # Number of instructions committed
@@ -79,18 +79,18 @@ system.cpu.num_mem_refs                           717                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      35082                       # Number of busy cycles
+system.cpu.num_busy_cycles                      33048                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                 80.027768                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                 80.050296                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     2423                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    163                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  14.865031                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst      80.027768                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.039076                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.039076                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst      80.050296                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.039087                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.039087                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         2423                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            2423                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          2423                       # number of demand (read+write) hits
@@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst          163                       # n
 system.cpu.icache.demand_misses::total            163                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          163                       # number of overall misses
 system.cpu.icache.overall_misses::total           163                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst      9128000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total      9128000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst      9128000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total      9128000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst      9128000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total      9128000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst      8965000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total      8965000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst      8965000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total      8965000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst      8965000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total      8965000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         2586                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         2586                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         2586                       # number of demand (read+write) accesses
@@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.063032
 system.cpu.icache.demand_miss_rate::total     0.063032                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.063032                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.063032                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        55000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        55000                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total        55000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        55000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total        55000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000
 system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 47.439715                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 47.437790                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                      627                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                     82                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                   7.646341                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      47.439715                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.011582                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.011582                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      47.437790                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.011581                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.011581                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          360                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             360                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          267                       # number of WriteReq hits
@@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data           82                       # n
 system.cpu.dcache.demand_misses::total             82                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data           82                       # number of overall misses
 system.cpu.dcache.overall_misses::total            82                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      3080000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      3080000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      1512000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      1512000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      4592000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      4592000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      4592000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      4592000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3025000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3025000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      1485000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      1485000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      4510000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      4510000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      4510000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      4510000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
@@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.115656
 system.cpu.dcache.demand_miss_rate::total     0.115656                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.115656                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.115656                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               107.121835                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               107.162861                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   218                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst     80.139278                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     26.982557                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.002446                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000823                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.003269                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst     80.168669                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     26.994192                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.002447                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000824                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.003270                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_misses::cpu.inst          163                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          218                       # number of ReadReq misses