regressions: stats update due to stats from ruby prefetcher

3 files changed, 104 insertions, 18 deletions

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index 0b5dc966b..08d94aa42 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -107,7 +107,7 @@ version=0
 [system.dir_cntrl0.directory]
 type=RubyDirectoryMemory
 map_levels=4
-numa_high_bit=6
+numa_high_bit=5
 size=134217728
 use_map=false
 version=0
@@ -136,15 +136,17 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory sequencer
+children=L1DcacheMemory L1IcacheMemory prefetcher sequencer
 L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
 L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 buffer_size=0
 cntrl_id=0
+enable_prefetch=false
 l1_request_latency=2
 l1_response_latency=2
 l2_select_num_bits=0
 number_of_TBEs=256
+prefetcher=system.l1_cntrl0.prefetcher
 recycle_latency=10
 ruby_system=system.ruby
 send_evictions=false
@@ -172,7 +174,7 @@ type=RubyCache
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
-is_icache=false
+is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
 resourceStalls=false
@@ -181,6 +183,16 @@ start_index_bit=6
 tagAccessLatency=1
 tagArrayBanks=1
 
+[system.l1_cntrl0.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
 access_phys_mem=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 8f6a28b15..e49c679fb 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Sep/01/2012 14:03:04
+Real time: Dec/11/2012 09:10:20
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.41
-Virtual_time_in_minutes: 0.00683333
-Virtual_time_in_hours:   0.000113889
-Virtual_time_in_days:    4.74537e-06
+Virtual_time_in_seconds: 0.46
+Virtual_time_in_minutes: 0.00766667
+Virtual_time_in_hours:   0.000127778
+Virtual_time_in_days:    5.32407e-06
 
 Ruby_current_time: 52575
 Ruby_start_time: 0
 Ruby_cycles: 52575
 
-mbytes_resident: 46.8984
-mbytes_total: 257.648
-resident_ratio: 0.182086
+mbytes_resident: 52.6172
+mbytes_total: 267.098
+resident_ratio: 0.19704
 
 ruby_cycles_executed: [ 52576 ]
 
@@ -83,11 +83,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9494
+page_reclaims: 10056
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 80
+block_outputs: 96
 
 Network Stats
 -------------
@@ -201,6 +201,9 @@ Data_all_Acks [368 ] 368
 Ack [0 ] 0
 Ack_all [0 ] 0
 WB_Ack [124 ] 124
+PF_Load [0 ] 0
+PF_Ifetch [0 ] 0
+PF_Store [0 ] 0
 
  - Transitions -
 NP  Load [182 ] 182
@@ -208,18 +211,26 @@ NP  Ifetch [270 ] 270
 NP  Store [58 ] 58
 NP  Inv [162 ] 162
 NP  L1_Replacement [0 ] 0
+NP  PF_Load [0 ] 0
+NP  PF_Ifetch [0 ] 0
+NP  PF_Store [0 ] 0
 
 I  Load [22 ] 22
 I  Ifetch [30 ] 30
 I  Store [10 ] 10
 I  Inv [0 ] 0
 I  L1_Replacement [206 ] 206
+I  PF_Load [0 ] 0
+I  PF_Ifetch [0 ] 0
+I  PF_Store [0 ] 0
 
 S  Load [0 ] 0
 S  Ifetch [2285 ] 2285
 S  Store [0 ] 0
 S  Inv [124 ] 124
 S  L1_Replacement [172 ] 172
+S  PF_Load [0 ] 0
+S  PF_Store [0 ] 0
 
 E  Load [140 ] 140
 E  Ifetch [0 ] 0
@@ -229,6 +240,8 @@ E  L1_Replacement [79 ] 79
 E  Fwd_GETX [0 ] 0
 E  Fwd_GETS [0 ] 0
 E  Fwd_GET_INSTR [0 ] 0
+E  PF_Load [0 ] 0
+E  PF_Store [0 ] 0
 
 M  Load [71 ] 71
 M  Ifetch [0 ] 0
@@ -238,6 +251,8 @@ M  L1_Replacement [45 ] 45
 M  Fwd_GETX [0 ] 0
 M  Fwd_GETS [0 ] 0
 M  Fwd_GET_INSTR [0 ] 0
+M  PF_Load [0 ] 0
+M  PF_Store [0 ] 0
 
 IS  Load [0 ] 0
 IS  Ifetch [0 ] 0
@@ -247,6 +262,8 @@ IS  L1_Replacement [0 ] 0
 IS  Data_Exclusive [204 ] 204
 IS  DataS_fromL1 [0 ] 0
 IS  Data_all_Acks [300 ] 300
+IS  PF_Load [0 ] 0
+IS  PF_Store [0 ] 0
 
 IM  Load [0 ] 0
 IM  Ifetch [0 ] 0
@@ -256,6 +273,8 @@ IM  L1_Replacement [0 ] 0
 IM  Data [0 ] 0
 IM  Data_all_Acks [68 ] 68
 IM  Ack [0 ] 0
+IM  PF_Load [0 ] 0
+IM  PF_Store [0 ] 0
 
 SM  Load [0 ] 0
 SM  Ifetch [0 ] 0
@@ -264,6 +283,8 @@ SM  Inv [0 ] 0
 SM  L1_Replacement [0 ] 0
 SM  Ack [0 ] 0
 SM  Ack_all [0 ] 0
+SM  PF_Load [0 ] 0
+SM  PF_Store [0 ] 0
 
 IS_I  Load [0 ] 0
 IS_I  Ifetch [0 ] 0
@@ -273,6 +294,8 @@ IS_I  L1_Replacement [0 ] 0
 IS_I  Data_Exclusive [0 ] 0
 IS_I  DataS_fromL1 [0 ] 0
 IS_I  Data_all_Acks [0 ] 0
+IS_I  PF_Load [0 ] 0
+IS_I  PF_Store [0 ] 0
 
 M_I  Load [0 ] 0
 M_I  Ifetch [0 ] 0
@@ -283,6 +306,8 @@ M_I  Fwd_GETX [0 ] 0
 M_I  Fwd_GETS [0 ] 0
 M_I  Fwd_GET_INSTR [0 ] 0
 M_I  WB_Ack [124 ] 124
+M_I  PF_Load [0 ] 0
+M_I  PF_Store [0 ] 0
 
 SINK_WB_ACK  Load [0 ] 0
 SINK_WB_ACK  Ifetch [0 ] 0
@@ -290,6 +315,46 @@ SINK_WB_ACK  Store [0 ] 0
 SINK_WB_ACK  Inv [0 ] 0
 SINK_WB_ACK  L1_Replacement [0 ] 0
 SINK_WB_ACK  WB_Ack [0 ] 0
+SINK_WB_ACK  PF_Load [0 ] 0
+SINK_WB_ACK  PF_Store [0 ] 0
+
+PF_IS  Load [0 ] 0
+PF_IS  Ifetch [0 ] 0
+PF_IS  Store [0 ] 0
+PF_IS  Inv [0 ] 0
+PF_IS  L1_Replacement [0 ] 0
+PF_IS  Data_Exclusive [0 ] 0
+PF_IS  DataS_fromL1 [0 ] 0
+PF_IS  Data_all_Acks [0 ] 0
+PF_IS  PF_Load [0 ] 0
+PF_IS  PF_Store [0 ] 0
+
+PF_IM  Load [0 ] 0
+PF_IM  Ifetch [0 ] 0
+PF_IM  Store [0 ] 0
+PF_IM  Inv [0 ] 0
+PF_IM  L1_Replacement [0 ] 0
+PF_IM  Data [0 ] 0
+PF_IM  Data_all_Acks [0 ] 0
+PF_IM  Ack [0 ] 0
+PF_IM  PF_Load [0 ] 0
+PF_IM  PF_Store [0 ] 0
+
+PF_SM  Load [0 ] 0
+PF_SM  Ifetch [0 ] 0
+PF_SM  Store [0 ] 0
+PF_SM  Inv [0 ] 0
+PF_SM  L1_Replacement [0 ] 0
+PF_SM  Ack [0 ] 0
+PF_SM  Ack_all [0 ] 0
+
+PF_IS_I  Load [0 ] 0
+PF_IS_I  Store [0 ] 0
+PF_IS_I  Inv [0 ] 0
+PF_IS_I  L1_Replacement [0 ] 0
+PF_IS_I  Data_Exclusive [0 ] 0
+PF_IS_I  DataS_fromL1 [0 ] 0
+PF_IS_I  Data_all_Acks [0 ] 0
 
 Cache Stats: system.l2_cntrl0.L2cacheMemory
   system.l2_cntrl0.L2cacheMemory_total_misses: 547
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 84321c81e..381866200 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000053                       # Nu
 sim_ticks                                       52575                       # Number of ticks simulated
 final_tick                                      52575                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27172                       # Simulator instruction rate (inst/s)
-host_op_rate                                    27165                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 554084                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 263836                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  11415                       # Simulator instruction rate (inst/s)
+host_op_rate                                    11414                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 232838                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273512                       # Number of bytes of host memory used
+host_seconds                                     0.23                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
@@ -45,6 +45,15 @@ system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0
 system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
 system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
 system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+system.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
+system.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
+system.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
+system.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
+system.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
+system.l1_cntrl0.prefetcher.hits                    0                       # number of prefetched blocks accessed
+system.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
+system.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
+system.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
 system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads