diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
tree | 5d32efd82f884376573604727d971a80458ed04a /tests/quick/se/00.hello/ref/alpha/tru64 | |
parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64')
25 files changed, 382 insertions, 212 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index e812354d2..3b6b2b818 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 992260cf4..157d28a7a 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:16 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:45:03 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 28a756060..119328db2 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000007 # Nu sim_ticks 7015000 # Number of ticks simulated final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31687 # Simulator instruction rate (inst/s) -host_op_rate 31676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93063477 # Simulator tick rate (ticks/s) -host_mem_usage 214220 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 16156 # Simulator instruction rate (inst/s) +host_op_rate 16154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47467285 # Simulator tick rate (ticks/s) +host_mem_usage 214556 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 17600 # Number of bytes read from this memory -system.physmem.bytes_inst_read 12096 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 275 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2508909480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1724305061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2508909480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 12096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5504 # Number of bytes read from this memory +system.physmem.bytes_read::total 17600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 12096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 12096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 189 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 86 # Number of read requests responded to by this memory +system.physmem.num_reads::total 275 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1724305061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 784604419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2508909480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1724305061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 784604419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2508909480 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -355,11 +362,17 @@ system.cpu.icache.demand_accesses::total 1067 # nu system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.234302 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.234302 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.234302 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35830 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35830 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35830 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,11 +400,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 6695500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177132 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.177132 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.177132 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35425.925926 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use @@ -435,13 +454,21 @@ system.cpu.dcache.demand_accesses::total 972 # nu system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.157817 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184156 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184156 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34359.813084 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39111.111111 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36270.949721 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36270.949721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,13 +502,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3078500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.091445 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.088477 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.088477 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35564.516129 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36395.833333 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use @@ -529,18 +564,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 86 system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34340.637450 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34666.666667 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34369.090909 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34369.090909 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,18 +616,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.410359 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31562.500000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 4f5452325..198cad098 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr index 31ae36f2e..bcbfa5445 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout index d7b73cec1..4dbe62d94 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:01 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:15:42 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 2f22610c9..cc1232526 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 381497 # Simulator instruction rate (inst/s) -host_op_rate 379897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 190598632 # Simulator tick rate (ticks/s) -host_mem_usage 204064 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 760610 # Simulator instruction rate (inst/s) +host_op_rate 756680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379104629 # Simulator tick rate (ticks/s) +host_mem_usage 204432 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10293641618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7969171484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1586127168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11879768786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7969171484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2324470135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10293641618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7969171484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7969171484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1586127168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1586127168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index bda71aafd..5ef992e40 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:34 +Real time: Jun/04/2012 13:42:36 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.24 -Virtual_time_in_minutes: 0.004 -Virtual_time_in_hours: 6.66667e-05 -Virtual_time_in_days: 2.77778e-06 +Virtual_time_in_seconds: 0.31 +Virtual_time_in_minutes: 0.00516667 +Virtual_time_in_hours: 8.61111e-05 +Virtual_time_in_days: 3.58796e-06 Ruby_current_time: 104867 Ruby_start_time: 0 Ruby_cycles: 104867 -mbytes_resident: 45.8906 -mbytes_total: 218.43 -resident_ratio: 0.210093 +mbytes_resident: 46.8984 +mbytes_total: 218.785 +resident_ratio: 0.214358 ruby_cycles_executed: [ 104868 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12254 -page_faults: 0 +page_reclaims: 12410 +page_faults: 4 swaps: 0 -block_inputs: 0 -block_outputs: 88 +block_inputs: 480 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index 59ad2cc4d..d8d70a93e 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 13:42:35 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index bd57039cb..748d8a973 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000105 # Nu sim_ticks 104867 # Number of ticks simulated final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 38145 # Simulator instruction rate (inst/s) -host_op_rate 38137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1551633 # Simulator tick rate (ticks/s) -host_mem_usage 223676 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 4864 # Simulator instruction rate (inst/s) +host_op_rate 4864 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197908 # Simulator tick rate (ticks/s) +host_mem_usage 224040 # Number of bytes of host memory used +host_seconds 0.53 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 127361324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 98601085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 19624858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 146986182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 98601085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28760239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 127361324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 98601085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 98601085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 19624858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 19624858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 98601085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48385097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 146986182 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 232722c59..0769bb48a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:38 +Real time: Jun/04/2012 14:41:15 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 +Virtual_time_in_seconds: 0.3 +Virtual_time_in_minutes: 0.005 +Virtual_time_in_hours: 8.33333e-05 +Virtual_time_in_days: 3.47222e-06 Ruby_current_time: 85418 Ruby_start_time: 0 Ruby_cycles: 85418 -mbytes_resident: 46.1016 -mbytes_total: 218.602 -resident_ratio: 0.210893 +mbytes_resident: 46.9141 +mbytes_total: 218.969 +resident_ratio: 0.21425 ruby_cycles_executed: [ 85419 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12263 +page_reclaims: 12428 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 80 +block_outputs: 88 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index fe8db74fc..dc8b54148 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:15 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 5143cdcae..07e9173f4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000085 # Nu sim_ticks 85418 # Number of ticks simulated final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 33831 # Simulator instruction rate (inst/s) -host_op_rate 33824 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1120953 # Simulator tick rate (ticks/s) -host_mem_usage 223852 # Number of bytes of host memory used +host_inst_rate 30509 # Simulator instruction rate (inst/s) +host_op_rate 30502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010829 # Simulator tick rate (ticks/s) +host_mem_usage 224228 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 156360486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 121051769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 24093282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 180453769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 121051769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35308717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 156360486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 121051769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 121051769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 24093282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24093282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats index a538bb5ac..1584bb895 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:42 +Real time: Jun/04/2012 14:42:22 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.23 -Virtual_time_in_minutes: 0.00383333 -Virtual_time_in_hours: 6.38889e-05 -Virtual_time_in_days: 2.66204e-06 +Virtual_time_in_seconds: 0.27 +Virtual_time_in_minutes: 0.0045 +Virtual_time_in_hours: 7.5e-05 +Virtual_time_in_days: 3.125e-06 Ruby_current_time: 87899 Ruby_start_time: 0 Ruby_cycles: 87899 -mbytes_resident: 45.1094 -mbytes_total: 217.598 -resident_ratio: 0.207306 +mbytes_resident: 46.1055 +mbytes_total: 217.996 +resident_ratio: 0.211497 ruby_cycles_executed: [ 87900 ] @@ -127,11 +127,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12024 +page_reclaims: 12179 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 88 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index f849b0d8f..3e1c7a0df 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:41 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:22 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 253fc28f1..0b4d202c9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000088 # Nu sim_ticks 87899 # Number of ticks simulated final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 46491 # Simulator instruction rate (inst/s) -host_op_rate 46479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1584970 # Simulator tick rate (ticks/s) -host_mem_usage 222824 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 49141 # Simulator instruction rate (inst/s) +host_op_rate 49125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1675041 # Simulator tick rate (ticks/s) +host_mem_usage 223232 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 151947121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 117635013 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 23413236 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 175360357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 117635013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34312108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 151947121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 117635013 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 117635013 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 23413236 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 23413236 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 117635013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57725344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 175360357 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 6835e2100..f062dbc78 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:31 +Real time: Jun/04/2012 13:42:34 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.24 -Virtual_time_in_minutes: 0.004 -Virtual_time_in_hours: 6.66667e-05 -Virtual_time_in_days: 2.77778e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 78448 Ruby_start_time: 0 Ruby_cycles: 78448 -mbytes_resident: 44.707 -mbytes_total: 217.324 -resident_ratio: 0.205716 +mbytes_resident: 45.7539 +mbytes_total: 217.664 +resident_ratio: 0.210204 ruby_cycles_executed: [ 78449 ] @@ -126,11 +126,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11920 -page_faults: 3 +page_reclaims: 12072 +page_faults: 20 swaps: 0 -block_inputs: 824 -block_outputs: 88 +block_inputs: 2944 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 7b52a0c21..423daf7c7 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index f21155c2f..002b923d5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000078 # Nu sim_ticks 78448 # Number of ticks simulated final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 48255 # Simulator instruction rate (inst/s) -host_op_rate 48240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1468118 # Simulator tick rate (ticks/s) -host_mem_usage 222544 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 9618 # Simulator instruction rate (inst/s) +host_op_rate 9618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292754 # Simulator tick rate (ticks/s) +host_mem_usage 222892 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 170252906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 131807057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 26233938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 196486845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 131807057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38445849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 170252906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 131807057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 131807057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 26233938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26233938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 131807057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64679788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 196486845 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats index cc4333b9c..0115257b7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:37:51 +Real time: Jun/04/2012 14:06:25 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.4 -Virtual_time_in_minutes: 0.00666667 -Virtual_time_in_hours: 0.000111111 -Virtual_time_in_days: 4.62963e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 Ruby_current_time: 123378 Ruby_start_time: 0 Ruby_cycles: 123378 -mbytes_resident: 45.0547 -mbytes_total: 217.531 -resident_ratio: 0.207118 +mbytes_resident: 46.1406 +mbytes_total: 217.871 +resident_ratio: 0.211779 ruby_cycles_executed: [ 123379 ] @@ -122,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12045 +page_reclaims: 12216 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 6ae96cee0..ef2e2d974 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:51 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:06:24 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 6c31e7bc8..d4f9035ad 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000123 # Nu sim_ticks 123378 # Number of ticks simulated final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23789 # Simulator instruction rate (inst/s) -host_op_rate 23782 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1138300 # Simulator tick rate (ticks/s) -host_mem_usage 222756 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 56001 # Simulator instruction rate (inst/s) +host_op_rate 55979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2679090 # Simulator tick rate (ticks/s) +host_mem_usage 223104 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 108252687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 83807486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 16680445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 124933132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 83807486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24445201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 108252687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 83807486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 83807486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 16680445 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16680445 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 83807486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 41125646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 124933132 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 1cfaa4239..3d54d7382 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index 194a972c4..803a08b4e 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:39:41 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 2a4818376..fab613981 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000017 # Nu sim_ticks 16769000 # Number of ticks simulated final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149101 # Simulator instruction rate (inst/s) -host_op_rate 148981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 968734693 # Simulator tick rate (ticks/s) -host_mem_usage 212944 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 308591 # Simulator instruction rate (inst/s) +host_op_rate 307918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1999557615 # Simulator tick rate (ticks/s) +host_mem_usage 213304 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15680 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10432 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 245 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 935058739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 935058739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory +system.physmem.bytes_read::total 15680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory +system.physmem.num_reads::total 245 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 622100304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 312958435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 935058739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 622100304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 622100304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 622100304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 312958435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 935058739 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total 2586 # nu system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 8639000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use @@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total 709 # nu system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,13 +242,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4346000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use @@ -269,18 +304,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 82 system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -313,18 +356,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |