diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-24 20:50:06 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-24 20:50:06 -0600 |
| commit | 53f697a6166a6fe2787882f3448e73a8ebb849aa (patch) | |
| tree | 34375d648a60551f8a1ccb0a4486a35665b5115a /tests/quick/se/00.hello/ref/alpha/tru64 | |
| parent | 8504b079b8e1c5bc4c14fa42ba224fe182ca43df (diff) | |
| download | gem5-53f697a6166a6fe2787882f3448e73a8ebb849aa.tar.xz | |
stats: updates due to c0db268f811b
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64')
10 files changed, 120 insertions, 40 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini index 8168c285c..96554f51d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000 [system] type=System -children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain +children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:268435455 memories=system.physmem @@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -108,7 +110,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -131,6 +133,16 @@ latency_var=0 null=true range=0:134217727 +[system.piobus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.ruby.l1_cntrl0.sequencer.pio_slave_port +slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port + [system.ruby] type=RubySystem children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network @@ -282,6 +294,9 @@ system=system using_network_tester=false using_ruby_tester=false version=0 +mem_master_port=system.piobus.slave[1] +pio_master_port=system.piobus.slave[0] +pio_slave_port=system.piobus.master[0] slave=system.cpu.icache_port system.cpu.dcache_port [system.ruby.l2_cntrl0] @@ -436,7 +451,6 @@ ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.system_port diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 32cd33943..24dc22b08 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,15 +4,17 @@ sim_seconds 0.000053 # Nu sim_ticks 52548 # Number of ticks simulated final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18733 # Simulator instruction rate (inst/s) -host_op_rate 18730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 381878 # Simulator tick rate (ticks/s) -host_mem_usage 173280 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 15623 # Simulator instruction rate (inst/s) +host_op_rate 15622 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 318507 # Simulator tick rate (ticks/s) +host_mem_usage 173288 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.piobus.throughput 0 # Throughput (bytes/s) +system.piobus.data_through_bus 0 # Total data (bytes) system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 647bb1e23..5bf00383f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000 [system] type=System -children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain +children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:268435455 memories=system.physmem @@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -108,7 +110,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -131,6 +133,16 @@ latency_var=0 null=true range=0:134217727 +[system.piobus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.ruby.l1_cntrl0.sequencer.pio_slave_port +slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port + [system.ruby] type=RubySystem children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network @@ -267,6 +279,9 @@ system=system using_network_tester=false using_ruby_tester=false version=0 +mem_master_port=system.piobus.slave[1] +pio_master_port=system.piobus.slave[0] +pio_slave_port=system.piobus.master[0] slave=system.cpu.icache_port system.cpu.dcache_port [system.ruby.l2_cntrl0] @@ -420,7 +435,6 @@ ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.system_port diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 0ccaf1668..9dd7d5514 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,15 +4,17 @@ sim_seconds 0.000045 # Nu sim_ticks 44968 # Number of ticks simulated final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 20165 # Simulator instruction rate (inst/s) -host_op_rate 20162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 351768 # Simulator tick rate (ticks/s) -host_mem_usage 175636 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 18935 # Simulator instruction rate (inst/s) +host_op_rate 18932 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 330302 # Simulator tick rate (ticks/s) +host_mem_usage 175652 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.piobus.throughput 0 # Throughput (bytes/s) +system.piobus.data_through_bus 0 # Total data (bytes) system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 2bf0001da..215d8c7dd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000 [system] type=System -children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain +children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:268435455 memories=system.physmem @@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -108,7 +110,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -131,6 +133,16 @@ latency_var=0 null=true range=0:134217727 +[system.piobus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.ruby.l1_cntrl0.sequencer.pio_slave_port +slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port + [system.ruby] type=RubySystem children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network @@ -278,6 +290,9 @@ system=system using_network_tester=false using_ruby_tester=false version=0 +mem_master_port=system.piobus.slave[1] +pio_master_port=system.piobus.slave[0] +pio_slave_port=system.piobus.master[0] slave=system.cpu.icache_port system.cpu.dcache_port [system.ruby.l2_cntrl0] @@ -433,7 +448,6 @@ ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.system_port diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 40fe08734..5c6f736b0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,15 +4,17 @@ sim_seconds 0.000043 # Nu sim_ticks 43073 # Number of ticks simulated final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 26989 # Simulator instruction rate (inst/s) -host_op_rate 26984 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 450937 # Simulator tick rate (ticks/s) -host_mem_usage 173396 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 22164 # Simulator instruction rate (inst/s) +host_op_rate 22160 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 370326 # Simulator tick rate (ticks/s) +host_mem_usage 173416 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.piobus.throughput 0 # Throughput (bytes/s) +system.piobus.data_through_bus 0 # Total data (bytes) system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 1829ec00a..80f383f10 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000 [system] type=System -children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain +children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:268435455 memories=system.physmem @@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -108,7 +110,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -131,6 +133,16 @@ latency_var=0 null=true range=0:134217727 +[system.piobus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.ruby.l1_cntrl0.sequencer.pio_slave_port +slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port + [system.ruby] type=RubySystem children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network @@ -302,6 +314,9 @@ system=system using_network_tester=false using_ruby_tester=false version=0 +mem_master_port=system.piobus.slave[1] +pio_master_port=system.piobus.slave[0] +pio_slave_port=system.piobus.master[0] slave=system.cpu.icache_port system.cpu.dcache_port [system.ruby.memctrl_clk_domain] @@ -396,7 +411,6 @@ ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.system_port diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 7c0342029..f07876b7c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,15 +4,17 @@ sim_seconds 0.000035 # Nu sim_ticks 35432 # Number of ticks simulated final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 26797 # Simulator instruction rate (inst/s) -host_op_rate 26791 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 368294 # Simulator tick rate (ticks/s) -host_mem_usage 174352 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 22204 # Simulator instruction rate (inst/s) +host_op_rate 22201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 305145 # Simulator tick rate (ticks/s) +host_mem_usage 174496 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.piobus.throughput 0 # Throughput (bytes/s) +system.piobus.data_through_bus 0 # Total data (bytes) system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 360da34a5..06b17a491 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000 [system] type=System -children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain +children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:268435455 memories=system.physmem @@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -108,7 +110,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -131,6 +133,16 @@ latency_var=0 null=true range=0:134217727 +[system.piobus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.ruby.l1_cntrl0.sequencer.pio_slave_port +slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port + [system.ruby] type=RubySystem children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network @@ -250,6 +262,9 @@ system=system using_network_tester=false using_ruby_tester=false version=0 +mem_master_port=system.piobus.slave[1] +pio_master_port=system.piobus.slave[0] +pio_slave_port=system.piobus.master[0] slave=system.cpu.icache_port system.cpu.dcache_port [system.ruby.memctrl_clk_domain] @@ -344,7 +359,6 @@ ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.system_port diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 97736bd69..5c88cf46f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,15 +4,17 @@ sim_seconds 0.000052 # Nu sim_ticks 52498 # Number of ticks simulated final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23247 # Simulator instruction rate (inst/s) -host_op_rate 23243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 473432 # Simulator tick rate (ticks/s) -host_mem_usage 172892 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 10658 # Simulator instruction rate (inst/s) +host_op_rate 10657 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 217095 # Simulator tick rate (ticks/s) +host_mem_usage 172908 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.piobus.throughput 0 # Throughput (bytes/s) +system.piobus.data_through_bus 0 # Total data (bytes) system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message |