diff options
| author | Joel Hestness <hestness@cs.wisc.edu> | 2012-09-05 20:53:34 -0500 |
|---|---|---|
| committer | Joel Hestness <hestness@cs.wisc.edu> | 2012-09-05 20:53:34 -0500 |
| commit | 4124ea09f8e2f6934fe746ff7c244dba7230cac9 (patch) | |
| tree | b2bfebc3b4e62ff6a06deec45852f58fa2aded23 /tests/quick/se/00.hello/ref/alpha/tru64 | |
| parent | 6924e10978c5847fa33cf33c50f5b3511bf89ee4 (diff) | |
| download | gem5-4124ea09f8e2f6934fe746ff7c244dba7230cac9.tar.xz | |
stats: Update Ruby regressions for memory controller fix
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64')
12 files changed, 237 insertions, 219 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index cc1d6c0b9..ae9a50a52 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000 type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -119,9 +119,9 @@ bank_busy_time=11 bank_queue_size=12 banks_per_rank=8 basic_bus_busy_time=2 +clock=3 dimm_bit_0=12 dimms_per_channel=2 -mem_bus_cycle_multiplier=10 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -130,6 +130,7 @@ rank_rank_delay=1 ranks_per_dimm=2 read_write_delay=2 refresh_period=1560 +ruby_system=system.ruby tFaw=0 version=0 @@ -183,6 +184,7 @@ tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer access_phys_mem=true +clock=1 dcache=system.l1_cntrl0.L1DcacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory @@ -227,6 +229,7 @@ tagArrayBanks=1 [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true @@ -351,6 +354,7 @@ ruby_system=system.ruby [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true +clock=1 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 48e6b0fca..8f6a28b15 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,4 +1,4 @@ -Real time: Jul/10/2012 17:31:25 +Real time: Sep/01/2012 14:03:04 Profiler Stats -------------- @@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.47 -Virtual_time_in_minutes: 0.00783333 -Virtual_time_in_hours: 0.000130556 -Virtual_time_in_days: 5.43981e-06 +Virtual_time_in_seconds: 0.41 +Virtual_time_in_minutes: 0.00683333 +Virtual_time_in_hours: 0.000113889 +Virtual_time_in_days: 4.74537e-06 -Ruby_current_time: 104867 +Ruby_current_time: 52575 Ruby_start_time: 0 -Ruby_cycles: 104867 +Ruby_cycles: 52575 -mbytes_resident: 45.3203 -mbytes_total: 228.348 -resident_ratio: 0.198488 +mbytes_resident: 46.8984 +mbytes_total: 257.648 +resident_ratio: 0.182086 -ruby_cycles_executed: [ 104868 ] +ruby_cycles_executed: [ 52576 ] Busy Controller Counts: L1Cache-0:0 @@ -34,11 +34,11 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 275 count: 3294 average: 30.8358 | standard deviation: 62.2139 | 0 2722 0 0 0 0 0 0 0 23 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62 131 87 117 74 6 17 4 2 2 1 11 10 5 4 3 5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 235 count: 415 average: 80.7349 | standard deviation: 83.1868 | 0 211 0 0 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 46 24 49 14 4 7 4 1 1 0 5 0 4 0 3 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 275 count: 294 average: 39.8435 | standard deviation: 69.7713 | 0 226 0 0 0 0 0 0 0 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 19 3 12 8 0 8 0 0 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 267 count: 2585 average: 21.8004 | standard deviation: 52.7361 | 0 2285 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 66 60 56 52 2 2 0 1 1 1 5 9 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_NULL: [binsize: 2 max: 275 count: 3294 average: 30.8358 | standard deviation: 62.2139 | 0 2722 0 0 0 0 0 0 0 23 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62 131 87 117 74 6 17 4 2 2 1 11 10 5 4 3 5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 1 max: 116 count: 3294 average: 14.9608 | standard deviation: 26.5582 | 0 0 0 2722 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 107 178 170 5 17 15 15 11 9 0 5 5 3 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 1 max: 116 count: 415 average: 36.7566 | standard deviation: 35.7458 | 0 0 0 211 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 70 54 1 10 7 8 4 0 0 4 4 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 1 max: 106 count: 294 average: 18.915 | standard deviation: 29.8083 | 0 0 0 226 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 17 15 0 6 5 3 2 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH: [binsize: 1 max: 89 count: 2585 average: 11.012 | standard deviation: 22.3546 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71 91 101 4 1 3 4 5 9 0 0 0 0 0 0 0 1 1 ] +miss_latency_NULL: [binsize: 1 max: 116 count: 3294 average: 14.9608 | standard deviation: 26.5582 | 0 0 0 2722 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 107 178 170 5 17 15 15 11 9 0 5 5 3 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 2 max: 235 count: 415 average: 80.7349 | standard deviation: 83.1868 | 0 211 0 0 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 46 24 49 14 4 7 4 1 1 0 5 0 4 0 3 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 2 max: 275 count: 294 average: 39.8435 | standard deviation: 69.7713 | 0 226 0 0 0 0 0 0 0 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 19 3 12 8 0 8 0 0 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_NULL: [binsize: 2 max: 267 count: 2585 average: 21.8004 | standard deviation: 52.7361 | 0 2285 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 66 60 56 52 2 2 0 1 1 1 5 9 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 1 max: 116 count: 415 average: 36.7566 | standard deviation: 35.7458 | 0 0 0 211 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 70 54 1 10 7 8 4 0 0 4 4 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_NULL: [binsize: 1 max: 106 count: 294 average: 18.915 | standard deviation: 29.8083 | 0 0 0 226 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 17 15 0 6 5 3 2 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_NULL: [binsize: 1 max: 89 count: 2585 average: 11.012 | standard deviation: 22.3546 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71 91 101 4 1 3 4 5 9 0 0 0 0 0 0 0 1 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -65,10 +65,10 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 18 count: 3612 average: 0.0625692 | standard deviation: 0.620431 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 2644 average: 0.00075643 | standard deviation: 0.0389028 | 2643 0 1 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 968 average: 0.231405 | standard deviation: 1.18112 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 2 count: 2213 average: 0.000903751 | standard deviation: 0.0425243 | 2212 0 1 ] +Total_delay_cycles: [binsize: 1 max: 4 count: 3612 average: 0.0520487 | standard deviation: 0.453608 | 3565 0 0 0 47 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2644 average: 0 | standard deviation: 0 | 2644 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 4 count: 968 average: 0.194215 | standard deviation: 0.860485 | 921 0 0 0 47 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 2213 average: 0 | standard deviation: 0 | 2213 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -83,11 +83,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12765 +page_reclaims: 9494 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 80 Network Stats ------------- @@ -102,9 +102,9 @@ total_msgs: 14094 total_bytes: 368304 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 1.90098 - links_utilized_percent_switch_0_link_0: 2.71916 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 1.0828 bw: 16000 base_latency: 1 +links_utilized_percent_switch_0: 3.79173 + links_utilized_percent_switch_0_link_0: 5.42368 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.15977 bw: 16000 base_latency: 1 outgoing_messages_switch_0_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1 @@ -116,9 +116,9 @@ links_utilized_percent_switch_0: 1.90098 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 3.65844 - links_utilized_percent_switch_1_link_0: 3.68705 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 3.62984 bw: 16000 base_latency: 1 +links_utilized_percent_switch_1: 7.29719 + links_utilized_percent_switch_1_link_0: 7.35426 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 7.24013 bw: 16000 base_latency: 1 outgoing_messages_switch_1_link_0_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1 @@ -132,9 +132,9 @@ links_utilized_percent_switch_1: 3.65844 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 1.75746 - links_utilized_percent_switch_2_link_0: 0.910677 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.60425 bw: 16000 base_latency: 1 +links_utilized_percent_switch_2: 3.50547 + links_utilized_percent_switch_2_link_0: 1.81645 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 5.19448 bw: 16000 base_latency: 1 outgoing_messages_switch_2_link_0_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1 @@ -144,10 +144,10 @@ links_utilized_percent_switch_2: 1.75746 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 2.43896 - links_utilized_percent_switch_3_link_0: 2.71916 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 3.68705 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.910677 bw: 16000 base_latency: 1 +links_utilized_percent_switch_3: 4.8648 + links_utilized_percent_switch_3_link_0: 5.42368 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 7.35426 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 1.81645 bw: 16000 base_latency: 1 outgoing_messages_switch_3_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1 @@ -307,8 +307,8 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory --- L2Cache --- - Event Counts - L1_GET_INSTR [300 ] 300 -L1_GETS [205 ] 205 -L1_GETX [69 ] 69 +L1_GETS [204 ] 204 +L1_GETX [68 ] 68 L1_UPGRADE [0 ] 0 L1_PUTX [124 ] 124 L1_PUTX_old [0 ] 0 @@ -364,8 +364,8 @@ MT L2_Replacement_clean [141 ] 141 MT MEM_Inv [0 ] 0 M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [1 ] 1 -M_I L1_GETX [1 ] 1 +M_I L1_GETS [0 ] 0 +M_I L1_GETX [0 ] 0 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 M_I L1_PUTX_old [0 ] 0 @@ -518,19 +518,19 @@ Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 650 memory_reads: 547 memory_writes: 103 - memory_refreshes: 219 - memory_total_request_delays: 306 - memory_delays_per_request: 0.470769 - memory_delays_in_input_queue: 27 + memory_refreshes: 365 + memory_total_request_delays: 117 + memory_delays_per_request: 0.18 + memory_delays_in_input_queue: 0 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 279 - memory_stalls_for_bank_busy: 56 + memory_delays_stalled_at_head_of_bank_queue: 117 + memory_stalls_for_bank_busy: 63 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 9 - memory_stalls_for_bus: 94 + memory_stalls_for_arbitration: 8 + memory_stalls_for_bus: 46 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 120 + memory_stalls_for_read_write_turnaround: 0 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index 9a67c2963..b08e9f127 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 28 2012 11:30:15 -gem5 started Jul 28 2012 11:35:39 -gem5 executing on zizzer +gem5 compiled Sep 1 2012 14:01:54 +gem5 started Sep 1 2012 14:03:04 +gem5 executing on doudou.cs.wisc.edu command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 104867 because target called exit() +Exiting @ tick 52575 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index 198022e25..84321c81e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 104867 # Number of ticks simulated -final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000053 # Number of seconds simulated +sim_ticks 52575 # Number of ticks simulated +final_tick 52575 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22041 # Simulator instruction rate (inst/s) -host_op_rate 22037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 896641 # Simulator tick rate (ticks/s) -host_mem_usage 231628 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 27172 # Simulator instruction rate (inst/s) +host_op_rate 27165 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 554084 # Simulator tick rate (ticks/s) +host_mem_usage 263836 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 415 # Nu system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory system.physmem.num_writes::total 294 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 98601085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28760239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 127361324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 98601085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 98601085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 19624858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 19624858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 98601085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48385097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 146986182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 196671422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57365668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 254037090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 196671422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 196671422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 39144080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 39144080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 196671422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 96509748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 293181170 # Total bandwidth to/from this memory (bytes/s) system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -84,7 +84,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 104867 # number of cpu cycles simulated +system.cpu.numCycles 52575 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -103,7 +103,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 104867 # Number of busy cycles +system.cpu.num_busy_cycles 52575 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index e62cfb199..2e8369b1e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000 type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -118,9 +118,9 @@ bank_busy_time=11 bank_queue_size=12 banks_per_rank=8 basic_bus_busy_time=2 +clock=3 dimm_bit_0=12 dimms_per_channel=2 -mem_bus_cycle_multiplier=10 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -129,6 +129,7 @@ rank_rank_delay=1 ranks_per_dimm=2 read_write_delay=2 refresh_period=1560 +ruby_system=system.ruby tFaw=0 version=0 @@ -180,6 +181,7 @@ tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer access_phys_mem=true +clock=1 dcache=system.l1_cntrl0.L1DcacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory @@ -223,6 +225,7 @@ tagArrayBanks=1 [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true @@ -347,6 +350,7 @@ ruby_system=system.ruby [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true +clock=1 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 8dafccdfe..9e474b916 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -1,4 +1,4 @@ -Real time: Jul/10/2012 17:37:10 +Real time: Sep/01/2012 14:11:29 Profiler Stats -------------- @@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.48 -Virtual_time_in_minutes: 0.008 -Virtual_time_in_hours: 0.000133333 -Virtual_time_in_days: 5.55556e-06 +Virtual_time_in_seconds: 0.43 +Virtual_time_in_minutes: 0.00716667 +Virtual_time_in_hours: 0.000119444 +Virtual_time_in_days: 4.97685e-06 -Ruby_current_time: 85418 +Ruby_current_time: 44968 Ruby_start_time: 0 -Ruby_cycles: 85418 +Ruby_cycles: 44968 -mbytes_resident: 45.4062 -mbytes_total: 228.586 -resident_ratio: 0.198657 +mbytes_resident: 46.9961 +mbytes_total: 257.863 +resident_ratio: 0.182313 -ruby_cycles_executed: [ 85419 ] +ruby_cycles_executed: [ 44969 ] Busy Controller Counts: L2Cache-0:0 @@ -34,11 +34,11 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 281 count: 3294 average: 24.9314 | standard deviation: 56.0488 | 0 2784 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 91 84 78 63 5 2 2 1 3 3 0 2 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 277 count: 415 average: 60.9277 | standard deviation: 78.686 | 0 233 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 41 19 25 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 245 count: 294 average: 28.5238 | standard deviation: 59.597 | 0 236 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 3 12 7 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 281 count: 2585 average: 18.7439 | standard deviation: 48.5885 | 0 2315 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 57 40 47 31 2 2 2 1 3 2 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_NULL: [binsize: 2 max: 281 count: 3294 average: 24.9314 | standard deviation: 56.0488 | 0 2784 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 91 84 78 63 5 2 2 1 3 3 0 2 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 1 max: 115 count: 3294 average: 12.6515 | standard deviation: 24.0471 | 0 0 0 2784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126 124 112 20 18 9 5 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 1 max: 115 count: 415 average: 28.8699 | standard deviation: 33.4854 | 0 0 0 233 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 44 27 6 0 2 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 1 max: 82 count: 294 average: 14.5476 | standard deviation: 25.7644 | 0 0 0 236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 10 12 1 0 0 0 1 ] +miss_latency_IFETCH: [binsize: 1 max: 101 count: 2585 average: 9.83211 | standard deviation: 20.7704 | 0 0 0 2315 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 80 66 4 6 6 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_NULL: [binsize: 1 max: 115 count: 3294 average: 12.6515 | standard deviation: 24.0471 | 0 0 0 2784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126 124 112 20 18 9 5 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 2 max: 277 count: 415 average: 60.9277 | standard deviation: 78.686 | 0 233 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 41 19 25 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 2 max: 245 count: 294 average: 28.5238 | standard deviation: 59.597 | 0 236 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 3 12 7 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_NULL: [binsize: 2 max: 281 count: 2585 average: 18.7439 | standard deviation: 48.5885 | 0 2315 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 57 40 47 31 2 2 2 1 3 2 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 1 max: 115 count: 415 average: 28.8699 | standard deviation: 33.4854 | 0 0 0 233 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 44 27 6 0 2 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_NULL: [binsize: 1 max: 82 count: 294 average: 14.5476 | standard deviation: 25.7644 | 0 0 0 236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 10 12 1 0 0 0 1 ] +miss_latency_IFETCH_NULL: [binsize: 1 max: 101 count: 2585 average: 9.83211 | standard deviation: 20.7704 | 0 0 0 2315 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 80 66 4 6 6 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -83,11 +83,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12740 +page_reclaims: 9533 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 80 Network Stats ------------- @@ -102,9 +102,9 @@ total_msgs: 16577 total_bytes: 422728 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 5.15524 - links_utilized_percent_switch_0_link_0: 6.00225 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 4.30823 bw: 16000 base_latency: 1 +links_utilized_percent_switch_0: 9.79252 + links_utilized_percent_switch_0_link_0: 11.4014 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 8.1836 bw: 16000 base_latency: 1 outgoing_messages_switch_0_link_0_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 @@ -120,9 +120,9 @@ links_utilized_percent_switch_0: 5.15524 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 3.2581 - links_utilized_percent_switch_1_link_0: 2.98064 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 3.53555 bw: 16000 base_latency: 1 +links_utilized_percent_switch_1: 6.18885 + links_utilized_percent_switch_1_link_0: 5.6618 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 6.71589 bw: 16000 base_latency: 1 outgoing_messages_switch_1_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 87 6264 [ 0 0 87 0 0 0 0 0 0 0 ] base_latency: 1 @@ -134,9 +134,9 @@ links_utilized_percent_switch_1: 3.2581 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 1.89685 - links_utilized_percent_switch_2_link_0: 1.327 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.46669 bw: 16000 base_latency: 1 +links_utilized_percent_switch_2: 3.60312 + links_utilized_percent_switch_2_link_0: 2.52068 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 4.68555 bw: 16000 base_latency: 1 outgoing_messages_switch_2_link_0_Request_Control: 423 3384 [ 0 423 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Data: 76 5472 [ 0 0 76 0 0 0 0 0 0 0 ] base_latency: 1 @@ -147,10 +147,10 @@ links_utilized_percent_switch_2: 1.89685 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 3.43682 - links_utilized_percent_switch_3_link_0: 6.00225 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 2.98064 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 1.32759 bw: 16000 base_latency: 1 +links_utilized_percent_switch_3: 6.52835 + links_utilized_percent_switch_3_link_0: 11.4014 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 5.6618 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 2.52179 bw: 16000 base_latency: 1 outgoing_messages_switch_3_link_0_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 @@ -1199,19 +1199,19 @@ Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 499 memory_reads: 423 memory_writes: 76 - memory_refreshes: 178 - memory_total_request_delays: 116 - memory_delays_per_request: 0.232465 - memory_delays_in_input_queue: 2 + memory_refreshes: 313 + memory_total_request_delays: 77 + memory_delays_per_request: 0.154309 + memory_delays_in_input_queue: 0 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 114 - memory_stalls_for_bank_busy: 56 + memory_delays_stalled_at_head_of_bank_queue: 77 + memory_stalls_for_bank_busy: 41 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 10 + memory_stalls_for_arbitration: 9 memory_stalls_for_bus: 25 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 23 + memory_stalls_for_read_write_turnaround: 2 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 18 10 0 34 20 19 28 21 5 3 6 4 21 40 20 3 4 5 7 13 10 16 14 41 15 5 5 12 12 18 14 56 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index 6a5f96ccf..0eff99821 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 28 2012 11:32:56 -gem5 started Jul 28 2012 11:35:53 -gem5 executing on zizzer +gem5 compiled Sep 1 2012 14:10:16 +gem5 started Sep 1 2012 14:11:29 +gem5 executing on doudou.cs.wisc.edu command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 85418 because target called exit() +Exiting @ tick 44968 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 2737629f8..b192d2700 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000085 # Number of seconds simulated -sim_ticks 85418 # Number of ticks simulated -final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000045 # Number of seconds simulated +sim_ticks 44968 # Number of ticks simulated +final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 1284 # Simulator instruction rate (inst/s) -host_op_rate 1284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42571 # Simulator tick rate (ticks/s) -host_mem_usage 232824 # Number of bytes of host memory used -host_seconds 2.01 # Real time elapsed on the host +host_inst_rate 22673 # Simulator instruction rate (inst/s) +host_op_rate 22668 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 395469 # Simulator tick rate (ticks/s) +host_mem_usage 264056 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 415 # Nu system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory system.physmem.num_writes::total 294 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 121051769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35308717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 156360486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 121051769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 121051769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 24093282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24093282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 229941292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 67069916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 297011208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 229941292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 229941292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 45765878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45765878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 229941292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 112835794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 342777086 # Total bandwidth to/from this memory (bytes/s) system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -84,7 +84,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 85418 # number of cpu cycles simulated +system.cpu.numCycles 44968 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -103,7 +103,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 85418 # Number of busy cycles +system.cpu.num_busy_cycles 44968 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 1640431a2..4e9dec81e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000 type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -121,9 +121,9 @@ bank_busy_time=11 bank_queue_size=12 banks_per_rank=8 basic_bus_busy_time=2 +clock=3 dimm_bit_0=12 dimms_per_channel=2 -mem_bus_cycle_multiplier=10 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -132,6 +132,7 @@ rank_rank_delay=1 ranks_per_dimm=2 read_write_delay=2 refresh_period=1560 +ruby_system=system.ruby tFaw=0 version=0 @@ -214,6 +215,7 @@ tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer access_phys_mem=true +clock=1 dcache=system.l1_cntrl0.L1DcacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory @@ -229,6 +231,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true @@ -330,6 +333,7 @@ ruby_system=system.ruby [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true +clock=1 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 9dff590a4..9e9602eaf 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -1,26 +1,26 @@ -Real time: Jul/10/2012 17:50:59 +Real time: Sep/01/2012 13:54:35 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.42 -Virtual_time_in_minutes: 0.007 -Virtual_time_in_hours: 0.000116667 -Virtual_time_in_days: 4.86111e-06 +Virtual_time_in_seconds: 0.39 +Virtual_time_in_minutes: 0.0065 +Virtual_time_in_hours: 0.000108333 +Virtual_time_in_days: 4.51389e-06 -Ruby_current_time: 78448 +Ruby_current_time: 35432 Ruby_start_time: 0 -Ruby_cycles: 78448 +Ruby_cycles: 35432 -mbytes_resident: 44.0312 -mbytes_total: 227.02 -resident_ratio: 0.193988 +mbytes_resident: 47.6953 +mbytes_total: 256.324 +resident_ratio: 0.186135 -ruby_cycles_executed: [ 78449 ] +ruby_cycles_executed: [ 35433 ] Busy Controller Counts: L1Cache-0:0 @@ -33,13 +33,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] +miss_latency: [binsize: 1 max: 122 count: 3294 average: 9.75653 | standard deviation: 19.3896 | 0 0 2784 0 0 0 0 0 0 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 327 37 9 38 4 1 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 2 1 8 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 ] +miss_latency_LD: [binsize: 1 max: 122 count: 415 average: 22.8313 | standard deviation: 27.0523 | 0 0 233 0 0 0 0 0 0 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 110 14 1 9 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] +miss_latency_ST: [binsize: 1 max: 122 count: 294 average: 12.0102 | standard deviation: 23.154 | 0 0 236 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 0 2 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ] +miss_latency_IFETCH: [binsize: 1 max: 83 count: 2585 average: 7.40116 | standard deviation: 16.3551 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 181 23 6 25 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 5 ] miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ] miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ] -miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 1 max: 122 count: 441 average: 58.2154 | standard deviation: 8.81927 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 327 37 9 38 4 1 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 2 1 8 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -47,18 +47,18 @@ miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 avera imcomplete_wCC_Times: 0 miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] imcomplete_dir_Times: 440 miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ] -miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_Directory: [binsize: 1 max: 122 count: 146 average: 58.5 | standard deviation: 9.33625 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 110 14 1 9 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ] miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ] -miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 1 max: 122 count: 47 average: 62.0426 | standard deviation: 18.5144 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 0 2 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ] miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ] -miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] +miss_latency_IFETCH_Directory: [binsize: 1 max: 83 count: 248 average: 57.3226 | standard deviation: 4.46262 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 181 23 6 25 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 5 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -90,11 +90,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12375 +page_reclaims: 9203 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 80 Network Stats ------------- @@ -108,9 +108,9 @@ total_msgs: 7791 total_bytes: 162552 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 2.15844 - links_utilized_percent_switch_0_link_0: 2.80058 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 1.51629 bw: 16000 base_latency: 1 +links_utilized_percent_switch_0: 4.77887 + links_utilized_percent_switch_0_link_0: 6.20061 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 3.35713 bw: 16000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 @@ -121,9 +121,9 @@ links_utilized_percent_switch_0: 2.15844 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 2.15844 - links_utilized_percent_switch_1_link_0: 1.51629 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 2.80058 bw: 16000 base_latency: 1 +links_utilized_percent_switch_1: 4.77887 + links_utilized_percent_switch_1_link_0: 3.35713 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 6.20061 bw: 16000 base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 @@ -134,9 +134,9 @@ links_utilized_percent_switch_1: 2.15844 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 2.15844 - links_utilized_percent_switch_2_link_0: 2.80058 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 1.51629 bw: 16000 base_latency: 1 +links_utilized_percent_switch_2: 4.77887 + links_utilized_percent_switch_2_link_0: 6.20061 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 3.35713 bw: 16000 base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 @@ -590,25 +590,25 @@ Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 522 memory_reads: 441 memory_writes: 81 - memory_refreshes: 164 - memory_total_request_delays: 151 - memory_delays_per_request: 0.289272 - memory_delays_in_input_queue: 2 + memory_refreshes: 246 + memory_total_request_delays: 39 + memory_delays_per_request: 0.0747126 + memory_delays_in_input_queue: 0 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 149 - memory_stalls_for_bank_busy: 22 + memory_delays_stalled_at_head_of_bank_queue: 39 + memory_stalls_for_bank_busy: 15 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 7 - memory_stalls_for_bus: 26 + memory_stalls_for_arbitration: 5 + memory_stalls_for_bus: 15 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 94 + memory_stalls_for_read_write_turnaround: 4 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62 --- Directory --- - Event Counts - -GETX [53 ] 53 +GETX [51 ] 51 GETS [410 ] 410 PUT [425 ] 425 Unblock [0 ] 0 @@ -909,7 +909,7 @@ WB_O_W DMA_WRITE [0 ] 0 WB_O_W Memory_Ack [0 ] 0 WB_O_W GETF [0 ] 0 -WB_E_W GETX [2 ] 2 +WB_E_W GETX [0 ] 0 WB_E_W GETS [2 ] 2 WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 55a2f065e..8fae8fc4c 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 28 2012 11:27:37 -gem5 started Jul 28 2012 11:35:39 -gem5 executing on zizzer +gem5 compiled Sep 1 2012 13:53:26 +gem5 started Sep 1 2012 13:54:34 +gem5 executing on doudou.cs.wisc.edu command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 78448 because target called exit() +Exiting @ tick 35432 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index a36f99678..c2b9c6eb8 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000078 # Number of seconds simulated -sim_ticks 78448 # Number of ticks simulated -final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000035 # Number of seconds simulated +sim_ticks 35432 # Number of ticks simulated +final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 31170 # Simulator instruction rate (inst/s) -host_op_rate 31163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 948464 # Simulator tick rate (ticks/s) -host_mem_usage 230616 # Number of bytes of host memory used +host_inst_rate 32925 # Simulator instruction rate (inst/s) +host_op_rate 32915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 452422 # Simulator tick rate (ticks/s) +host_mem_usage 262480 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 415 # Nu system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory system.physmem.num_writes::total 294 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 131807057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38445849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 170252906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 131807057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 131807057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 26233938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26233938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 131807057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 64679788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 196486845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 291826597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 85120795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 376947392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 291826597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 291826597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 58083089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58083089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 291826597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 143203883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 435030481 # Total bandwidth to/from this memory (bytes/s) system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -90,7 +90,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 78448 # number of cpu cycles simulated +system.cpu.numCycles 35432 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -109,7 +109,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 78448 # Number of busy cycles +system.cpu.num_busy_cycles 35432 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles |