diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/quick/se/00.hello/ref/alpha | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha')
6 files changed, 1048 insertions, 1047 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index ff8d4bf12..89a25c4c1 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:12 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21216000 because target called exit() +Exiting @ tick 21234500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index fc30a21c8..fdd02b36e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21216000 # Number of ticks simulated -final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21234500 # Number of ticks simulated +final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38129 # Simulator instruction rate (inst/s) -host_op_rate 38124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126288909 # Simulator tick rate (ticks/s) -host_mem_usage 209388 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 95244 # Simulator instruction rate (inst/s) +host_op_rate 95219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 315647941 # Simulator tick rate (ticks/s) +host_mem_usage 209384 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30016 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 469 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1414781297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 907993967 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1414781297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1413548706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 907202901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1413548706 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 2084 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2094 # DTB accesses -system.cpu.itb.fetch_hits 929 # ITB hits +system.cpu.itb.fetch_hits 908 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 946 # ITB accesses +system.cpu.itb.fetch_accesses 925 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42433 # number of cpu cycles simulated +system.cpu.numCycles 42470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7383 # Number of cycles cpu stages are processed. -system.cpu.activity 17.399194 # Percentage of cycles cpu is active +system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7391 # Number of cycles cpu stages are processed. +system.cpu.activity 17.402873 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -74,92 +74,92 @@ system.cpu.committedInsts 6404 # Nu system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total) -system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1670 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted +system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1608 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2138 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2183 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4447 # Number of Instructions Executed. +system.cpu.execution_unit.executions 4474 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use -system.cpu.icache.total_refs 581 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use +system.cpu.icache.total_refs 558 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.882502 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067814 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067814 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 581 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 581 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 581 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 581 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 581 # number of overall hits -system.cpu.icache.overall_hits::total 581 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses -system.cpu.icache.overall_misses::total 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19241000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19241000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19241000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19241000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 929 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 929 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 929 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 929 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.374596 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.374596 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.374596 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55290.229885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits +system.cpu.icache.overall_hits::total 558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,40 +168,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 46 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 46 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 46 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16049000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16049000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.384106 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.671807 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025066 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025066 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits @@ -218,14 +218,14 @@ system.cpu.dcache.demand_misses::cpu.data 347 # n system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses system.cpu.dcache.overall_misses::total 347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5508500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13555500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19064000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19064000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -238,10 +238,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56788.659794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54222 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -266,34 +266,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53831.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53561.643836 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.958412 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.251157 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005957 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -311,17 +311,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15707000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4995000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15707000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24524000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15707000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8817000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24524000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -340,13 +340,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52182.724252 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52578.947368 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52356.164384 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,16 +367,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15877000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18819500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses @@ -385,12 +385,12 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40405.263158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 684d7e9b2..16153e12a 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:12 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12004500 because target called exit() +Exiting @ tick 12450500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 49671266a..bfc4cc915 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12004500 # Number of ticks simulated -final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12450500 # Number of ticks simulated +final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42281 # Simulator instruction rate (inst/s) -host_op_rate 42276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79460110 # Simulator tick rate (ticks/s) -host_mem_usage 210060 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 87465 # Simulator instruction rate (inst/s) +host_op_rate 87444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170447462 # Simulator tick rate (ticks/s) +host_mem_usage 210080 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 31040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory +system.physmem.bytes_read 31360 # Number of bytes read from this memory +system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 485 # Number of read requests responded to by this memory +system.physmem.num_reads 490 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2585697030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1658044900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2585697030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1860 # DTB read hits -system.cpu.dtb.read_misses 44 # DTB read misses +system.cpu.dtb.read_hits 1943 # DTB read hits +system.cpu.dtb.read_misses 53 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1904 # DTB read accesses -system.cpu.dtb.write_hits 1041 # DTB write hits -system.cpu.dtb.write_misses 28 # DTB write misses +system.cpu.dtb.read_accesses 1996 # DTB read accesses +system.cpu.dtb.write_hits 1071 # DTB write hits +system.cpu.dtb.write_misses 32 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1069 # DTB write accesses -system.cpu.dtb.data_hits 2901 # DTB hits -system.cpu.dtb.data_misses 72 # DTB misses +system.cpu.dtb.write_accesses 1103 # DTB write accesses +system.cpu.dtb.data_hits 3014 # DTB hits +system.cpu.dtb.data_misses 85 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2973 # DTB accesses -system.cpu.itb.fetch_hits 2039 # ITB hits -system.cpu.itb.fetch_misses 29 # ITB misses +system.cpu.dtb.data_accesses 3099 # DTB accesses +system.cpu.itb.fetch_hits 2367 # ITB hits +system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2068 # ITB accesses +system.cpu.itb.fetch_accesses 2393 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,246 +53,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24010 # number of cpu cycles simulated +system.cpu.numCycles 24902 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2507 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1457 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 459 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 718 # Number of BTB hits +system.cpu.BPredUnit.lookups 2873 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14456 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2507 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1091 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1556 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.148030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.530696 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9973 79.20% 79.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.18% 81.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 224 1.78% 83.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.76% 84.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 234 1.86% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 178 1.41% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.04% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 140 1.11% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1090 8.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.104415 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.602082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7970 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2449 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 978 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13378 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 978 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2318 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12829 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9573 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16037 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 16020 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2784 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2587 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4990 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11558 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9757 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4883 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2853 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.774857 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.395692 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8510 67.58% 67.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1462 11.61% 79.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1072 8.51% 87.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 440 3.49% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 254 2.02% 98.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 128 1.02% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.24% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13 12.26% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 54 50.94% 63.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 36.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6575 67.39% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2074 21.26% 88.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1103 11.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9757 # Type of FU issued -system.cpu.iq.rate 0.406372 # Inst issue rate -system.cpu.iq.fu_busy_cnt 106 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010864 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16474 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10522 # Type of FU issued +system.cpu.iq.rate 0.422536 # Inst issue rate +system.cpu.iq.fu_busy_cnt 112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9850 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1206 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 406 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 978 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11665 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 447 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9313 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1914 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80 # number of nop insts executed -system.cpu.iew.exec_refs 2985 # number of memory reference insts executed -system.cpu.iew.exec_branches 1504 # Number of branches executed -system.cpu.iew.exec_stores 1071 # Number of stores executed -system.cpu.iew.exec_rate 0.387880 # Inst execution rate -system.cpu.iew.wb_sent 9119 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8992 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4719 # num instructions producing a value -system.cpu.iew.wb_consumers 6404 # num instructions consuming a value +system.cpu.iew.exec_nop 79 # number of nop insts executed +system.cpu.iew.exec_refs 3117 # number of memory reference insts executed +system.cpu.iew.exec_branches 1605 # Number of branches executed +system.cpu.iew.exec_stores 1108 # Number of stores executed +system.cpu.iew.exec_rate 0.396675 # Inst execution rate +system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9487 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4957 # num instructions producing a value +system.cpu.iew.wb_consumers 6732 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374511 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back +system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.413084 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 240 2.07% 95.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 159 1.37% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 46 0.40% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 162 1.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle system.cpu.commit.committedInsts 6403 # Number of instructions committed system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -303,64 +303,64 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 162 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22763 # The number of ROB reads -system.cpu.rob.rob_writes 24313 # The number of ROB writes -system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24667 # The number of ROB reads +system.cpu.rob.rob_writes 26868 # The number of ROB writes +system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads -system.cpu.ipc 0.265973 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265973 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11830 # number of integer regfile reads -system.cpu.int_regfile_writes 6732 # number of integer regfile writes +system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads +system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12526 # number of integer regfile reads +system.cpu.int_regfile_writes 7116 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.112304 # Cycle average of tags in use -system.cpu.icache.total_refs 1606 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use +system.cpu.icache.total_refs 1909 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.112304 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078180 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1606 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1606 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1606 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1606 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1606 # number of overall hits -system.cpu.icache.overall_hits::total 1606 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses -system.cpu.icache.overall_misses::total 433 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15431000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15431000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15431000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35637.413395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits +system.cpu.icache.overall_hits::total 1909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses +system.cpu.icache.overall_misses::total 458 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -369,80 +369,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 121 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 121 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 121 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 121 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 121 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11021000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35323.717949 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.290272 # Cycle average of tags in use -system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use +system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 109.290272 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1645 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2154 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2154 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2154 # number of overall hits -system.cpu.dcache.overall_hits::total 2154 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 154 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 154 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits +system.cpu.dcache.overall_hits::total 2244 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses -system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12467500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12467500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17965000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17965000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2664 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2664 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2664 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085603 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191441 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191441 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35698.051948 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35021.067416 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,103 +451,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056142 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36183.168317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35773.972603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.643066 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 412 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 160.084939 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 61.558127 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004885 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001879 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006764 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 311 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 412 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 311 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 311 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses -system.cpu.l2cache.overall_misses::total 485 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10665000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3498000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14163000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10665000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6011500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16676500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10665000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6011500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16676500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 312 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 413 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses +system.cpu.l2cache.overall_misses::total 490 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34292.604502 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34633.663366 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34431.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -556,42 +556,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 412 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9672000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3178000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12850000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9672000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5464000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15136000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9672000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5464000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15136000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31099.678457 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31465.346535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 6aed6d3ac..eb202613d 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:23 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:03 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 6833000 because target called exit() +Exiting @ tick 7015000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d93b581f0..686010297 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6833000 # Number of ticks simulated -final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7015000 # Number of ticks simulated +final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16400 # Simulator instruction rate (inst/s) -host_op_rate 16398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46934615 # Simulator tick rate (ticks/s) -host_mem_usage 209144 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 73930 # Simulator instruction rate (inst/s) +host_op_rate 73884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 217009042 # Simulator tick rate (ticks/s) +host_mem_usage 209140 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 17280 # Number of bytes read from this memory -system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory +system.physmem.bytes_read 17600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 12096 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 270 # Number of read requests responded to by this memory +system.physmem.num_reads 275 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2528903849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1732767452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2528903849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2508909480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2508909480 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 679 # DTB read hits -system.cpu.dtb.read_misses 26 # DTB read misses +system.cpu.dtb.read_hits 711 # DTB read hits +system.cpu.dtb.read_misses 43 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 705 # DTB read accesses -system.cpu.dtb.write_hits 356 # DTB write hits -system.cpu.dtb.write_misses 18 # DTB write misses +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 380 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 374 # DTB write accesses -system.cpu.dtb.data_hits 1035 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 403 # DTB write accesses +system.cpu.dtb.data_hits 1091 # DTB hits +system.cpu.dtb.data_misses 66 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1079 # DTB accesses -system.cpu.itb.fetch_hits 941 # ITB hits -system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.dtb.data_accesses 1157 # DTB accesses +system.cpu.itb.fetch_hits 1067 # ITB hits +system.cpu.itb.fetch_misses 33 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 971 # ITB accesses +system.cpu.itb.fetch_accesses 1100 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,245 +53,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13667 # number of cpu cycles simulated +system.cpu.numCycles 14031 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1038 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits +system.cpu.BPredUnit.lookups 1201 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 941 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1081 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1197 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 995 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups +system.cpu.rename.RunCycles 1115 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle +system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3881 # Type of FU issued -system.cpu.iq.rate 0.283969 # Inst issue rate -system.cpu.iq.fu_busy_cnt 41 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4206 # Type of FU issued +system.cpu.iq.rate 0.299765 # Inst issue rate +system.cpu.iq.fu_busy_cnt 43 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1080 # number of memory reference insts executed -system.cpu.iew.exec_branches 629 # Number of branches executed -system.cpu.iew.exec_stores 374 # Number of stores executed -system.cpu.iew.exec_rate 0.274310 # Inst execution rate -system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3579 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1702 # num instructions producing a value -system.cpu.iew.wb_consumers 2165 # num instructions consuming a value +system.cpu.iew.exec_nop 368 # number of nop insts executed +system.cpu.iew.exec_refs 1160 # number of memory reference insts executed +system.cpu.iew.exec_branches 681 # Number of branches executed +system.cpu.iew.exec_stores 403 # Number of stores executed +system.cpu.iew.exec_rate 0.285439 # Inst execution rate +system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3813 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1793 # num instructions producing a value +system.cpu.iew.wb_consumers 2339 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back +system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -302,63 +303,63 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 10645 # The number of ROB reads -system.cpu.rob.rob_writes 10410 # The number of ROB writes -system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11567 # The number of ROB reads +system.cpu.rob.rob_writes 11753 # The number of ROB writes +system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads -system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4520 # number of integer regfile reads -system.cpu.int_regfile_writes 2768 # number of integer regfile writes +system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads +system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4832 # number of integer regfile reads +system.cpu.int_regfile_writes 2958 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use -system.cpu.icache.total_refs 700 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use +system.cpu.icache.total_refs 817 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 91.574139 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.044714 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.044714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 700 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 700 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 700 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 700 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 700 # number of overall hits -system.cpu.icache.overall_hits::total 700 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses -system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8777500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8777500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8777500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 941 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 941 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.256111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.256111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.256111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36421.161826 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits +system.cpu.icache.overall_hits::total 817 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,80 +368,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 185 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 185 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6554500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6554500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35429.729730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use -system.cpu.dcache.total_refs 765 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use +system.cpu.dcache.total_refs 793 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 86 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.220930 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.439198 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 543 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 46.152964 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011268 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011268 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 571 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 765 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 765 # number of overall hits -system.cpu.dcache.overall_hits::total 765 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 793 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 793 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 793 # number of overall hits +system.cpu.dcache.overall_hits::total 793 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 107 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 107 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 173 # number of overall misses -system.cpu.dcache.overall_misses::total 173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3605000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3605000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6421500 # 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number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2816000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 678 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 938 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 938 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 938 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 938 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.156832 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184435 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184435 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35693.069307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,83 +450,83 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 88 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 88 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35557.377049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 91.660485 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.543397 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002797 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000871 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_misses::cpu.inst 185 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 246 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 93.626172 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 251 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 270 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 270 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 189 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 86 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 275 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 189 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 86 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses @@ -533,13 +534,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.702703 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34450.819672 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34500 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,28 +549,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 246 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5756000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1905500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7661500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5756000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2661500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8417500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5756000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2661500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8417500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses @@ -577,13 +578,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.513514 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31237.704918 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |