diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/quick/se/00.hello/ref/alpha | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha')
17 files changed, 1323 insertions, 752 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 0bab63428..a216e15cb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu sim_ticks 25552000 # Number of ticks simulated final_tick 25552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78801 # Simulator instruction rate (inst/s) -host_op_rate 78787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 314994021 # Simulator tick rate (ticks/s) -host_mem_usage 262608 # Number of bytes of host memory used +host_inst_rate 78387 # Simulator instruction rate (inst/s) +host_op_rate 78372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 313333088 # Simulator tick rate (ticks/s) +host_mem_usage 263656 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,27 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.629630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 196.201768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.982069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16 29.63% 29.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 29.63% 59.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 12.96% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 7.41% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.85% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.85% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.70% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7 12.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54 # Bytes accessed per row activation -system.physmem.totQLat 2560250 # Total ticks spent queuing -system.physmem.totMemAccLat 12605250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 86 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.418605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 204.922237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.300576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27 31.40% 31.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21 24.42% 55.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 11.63% 67.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 9.30% 76.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 1.16% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.49% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 8.14% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.33% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7 8.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86 # Bytes accessed per row activation +system.physmem.totQLat 3845750 # Total ticks spent queuing +system.physmem.totMemAccLat 12639500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.totBankLat 7700000 # Total ticks spent accessing banks -system.physmem.avgQLat 5458.96 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16417.91 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8199.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26876.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26949.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1174.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1174.70 # Average system read bandwidth in MiByte/s @@ -223,7 +222,11 @@ system.physmem.readRowHitRate 80.60 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 54450.96 # Average gap between requests system.physmem.pageHitRate 80.60 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.memoryStateTime::IDLE 13500 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22839000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 1172197871 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution @@ -237,7 +240,7 @@ system.membus.data_through_bus 29952 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4371250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4371000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1632 # Number of BP lookups @@ -304,9 +307,9 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11596 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11594 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 469 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 43730 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7375 # Number of cycles cpu stages are processed. system.cpu.activity 14.431073 # Percentage of cycles cpu is active @@ -343,14 +346,14 @@ system.cpu.stage4.idleCycles 46641 # Nu system.cpu.stage4.runCycles 4464 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 8.734957 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.169993 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.073249 # Cycle average of tags in use system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.169993 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069419 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069419 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.073249 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069372 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id @@ -369,12 +372,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25349750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25349750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25349750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25349750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25349750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25349750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24875750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24875750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24875750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24875750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24875750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24875750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -387,12 +390,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71407.746479 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71407.746479 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71407.746479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71407.746479 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70072.535211 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70072.535211 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70072.535211 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70072.535211 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -413,24 +416,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21532500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21532500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21532500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21532500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21532500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21532500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21058500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21058500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21058500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21058500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21058500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21058500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71299.668874 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71299.668874 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69730.132450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69730.132450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 1174702567 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution @@ -449,19 +452,19 @@ system.cpu.toL2Bus.reqLayer0.occupancy 235000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 508000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 274750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 198.925679 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 198.803908 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.205920 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.719759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004340 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001731 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006071 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.109548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.694360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001730 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006067 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id @@ -485,17 +488,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6927250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28141250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4931500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4931500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21214000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11858750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33072750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21214000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11858750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33072750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20740000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7180750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27920750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5181250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5181250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12362000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33102000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20740000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12362000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33102000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -518,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70478.405316 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72918.421053 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71063.762626 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67554.794521 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67554.794521 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70517.590618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70517.590618 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68903.654485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75586.842105 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70506.944444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70976.027397 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70976.027397 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70579.957356 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70579.957356 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17443000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5745750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23188750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4029500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4029500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17443000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9775250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27218250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17443000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9775250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27218250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5998750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22968250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16969500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10277000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27246500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16969500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10277000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27246500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -570,27 +573,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57950.166113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.578947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58557.449495 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55198.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55198.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56377.076412 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63144.736842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58000.631313 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58606.164384 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58606.164384 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.450623 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.396801 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.450623 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025256 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025256 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.396801 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025243 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025243 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id @@ -613,14 +616,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7371250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7371250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21672250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21672250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29043500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29043500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29043500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29043500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7625750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7625750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22645250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22645250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30271000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30271000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30271000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30271000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -637,19 +640,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75992.268041 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75992.268041 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61920.714286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61920.714286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64974.272931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64974.272931 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78615.979381 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78615.979381 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64700.714286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64700.714286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67720.357942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67720.357942 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.730769 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.307692 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -669,14 +672,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7028750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7028750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12037750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12037750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12037750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12037750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7282250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7282250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5258750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5258750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12541000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12541000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12541000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12541000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -685,14 +688,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73986.842105 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73986.842105 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68616.438356 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68616.438356 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76655.263158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76655.263158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72037.671233 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72037.671233 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 8bfd28333..33f9c5fe9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21078000 # Number of ticks simulated -final_tick 21078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21025000 # Number of ticks simulated +final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72140 # Simulator instruction rate (inst/s) -host_op_rate 72127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238549554 # Simulator tick rate (ticks/s) -host_mem_usage 265696 # Number of bytes of host memory used +host_inst_rate 72274 # Simulator instruction rate (inst/s) +host_op_rate 72262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238397605 # Simulator tick rate (ticks/s) +host_mem_usage 265716 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 950374798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 528323370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1478698169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 950374798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 950374798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 950374798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 528323370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1478698169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 488 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21045000 # Total gap between requests +system.physmem.totGap 20992000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.393443 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.167058 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.898610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21 34.43% 34.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 26.23% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 9.84% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.56% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.92% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.64% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 16.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation -system.physmem.totQLat 3243750 # Total ticks spent queuing -system.physmem.totMemAccLat 13328750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.218426 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.360278 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 24.05% 50.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation +system.physmem.totQLat 4394750 # Total ticks spent queuing +system.physmem.totMemAccLat 13544750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers -system.physmem.totBankLat 7645000 # Total ticks spent accessing banks -system.physmem.avgQLat 6647.03 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15665.98 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9005.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27313.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1481.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27755.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1481.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.58 # Data bus utilization in percentage -system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.61 # Data bus utilization in percentage +system.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 394 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43125.00 # Average gap between requests +system.physmem.avgGap 43016.39 # Average gap between requests system.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1478698169 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15304250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1482425684 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -234,10 +238,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 618500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 4556750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2894 # Number of BP lookups system.cpu.branchPred.condPredicted 1702 # Number of conditional branches predicted @@ -252,22 +256,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2078 # DTB read hits +system.cpu.dtb.read_hits 2077 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2125 # DTB read accesses +system.cpu.dtb.read_accesses 2124 # DTB read accesses system.cpu.dtb.write_hits 1062 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1093 # DTB write accesses -system.cpu.dtb.data_hits 3140 # DTB hits +system.cpu.dtb.data_hits 3139 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3218 # DTB accesses -system.cpu.itb.fetch_hits 2388 # ITB hits +system.cpu.dtb.data_accesses 3217 # DTB accesses +system.cpu.itb.fetch_hits 2387 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2427 # ITB accesses +system.cpu.itb.fetch_accesses 2426 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -281,95 +285,95 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42157 # number of cpu cycles simulated +system.cpu.numCycles 42051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8510 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16605 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 8515 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16590 # Number of instructions fetch has processed system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2968 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1911 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1405 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 1438 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2388 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.109663 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.506678 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.106000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.503194 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11994 80.15% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.13% 82.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.56% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 214 1.43% 85.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.70% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.61% 88.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.76% 90.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 184 1.23% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1260 8.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12032 80.21% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.12% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.56% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 214 1.43% 85.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.70% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 241 1.61% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.76% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.22% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1259 8.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068648 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393885 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9327 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1567 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2770 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.068821 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.394521 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9332 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2769 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1226 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 243 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15343 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15335 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1226 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9537 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2628 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 341 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14637 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 9542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 708 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2627 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 344 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14630 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10979 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18262 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18253 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 301 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10973 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18255 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18246 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6409 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6403 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 843 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 874 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2768 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12974 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12973 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10780 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10779 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6201 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3613 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.720396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363744 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.718600 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361398 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10463 69.92% 69.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1623 10.85% 80.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1158 7.74% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 756 5.05% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 501 3.35% 96.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 1.80% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 146 0.98% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10485 69.90% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1646 10.97% 80.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1153 7.69% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 753 5.02% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 501 3.34% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 1.79% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15000 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available @@ -405,7 +409,7 @@ system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7243 67.19% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7243 67.20% 67.21% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued @@ -434,39 +438,39 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2399 22.25% 89.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2398 22.25% 89.49% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1133 10.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10780 # Type of FU issued -system.cpu.iq.rate 0.255711 # Inst issue rate +system.cpu.iq.FU_type_0::total 10779 # Type of FU issued +system.cpu.iq.rate 0.256332 # Inst issue rate system.cpu.iq.fu_busy_cnt 112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010390 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36671 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19208 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.010391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36705 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19206 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 9602 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10879 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10878 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1585 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 127 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 132 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1226 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 247 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13092 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 13091 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2768 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall @@ -475,43 +479,43 @@ system.cpu.iew.memOrderViolationEvents 16 # Nu system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 504 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10072 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 10071 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3231 # number of memory reference insts executed +system.cpu.iew.exec_refs 3230 # number of memory reference insts executed system.cpu.iew.exec_branches 1589 # Number of branches executed system.cpu.iew.exec_stores 1095 # Number of stores executed -system.cpu.iew.exec_rate 0.238916 # Inst execution rate +system.cpu.iew.exec_rate 0.239495 # Inst execution rate system.cpu.iew.wb_sent 9755 # cumulative count of insts sent to commit system.cpu.iew.wb_count 9612 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5080 # num instructions producing a value -system.cpu.iew.wb_consumers 6838 # num instructions consuming a value +system.cpu.iew.wb_producers 5069 # num instructions producing a value +system.cpu.iew.wb_consumers 6811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.228005 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.228580 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.744237 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6701 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6700 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13738 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465060 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.277866 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.463845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273398 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10960 79.78% 79.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1479 10.77% 90.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 519 3.78% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 236 1.72% 96.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 157 1.14% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 106 0.77% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 104 0.76% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 34 0.25% 98.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10981 79.72% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1489 10.81% 90.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 532 3.86% 94.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 235 1.71% 96.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 155 1.13% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 100 0.73% 97.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.77% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.24% 98.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 143 1.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13738 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13774 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -522,26 +526,61 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 6389 # Class of committed instruction system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26334 # The number of ROB reads -system.cpu.rob.rob_writes 27415 # The number of ROB writes +system.cpu.rob.rob_reads 26369 # The number of ROB reads +system.cpu.rob.rob_writes 27413 # The number of ROB writes system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27193 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 27051 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 6.615976 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.615976 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151149 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151149 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12785 # number of integer regfile reads +system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12784 # number of integer regfile reads system.cpu.int_regfile_writes 7268 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1481734510 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -556,61 +595,61 @@ system.cpu.toL2Bus.data_through_bus 31232 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 278250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.411930 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1899 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.423717 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.047771 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.411930 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077838 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 159.423717 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077844 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5090 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5090 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1899 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1899 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1899 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1899 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1899 # number of overall hits -system.cpu.icache.overall_hits::total 1899 # number of overall hits +system.cpu.icache.tags.tag_accesses 5088 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5088 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits +system.cpu.icache.overall_hits::total 1898 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses system.cpu.icache.overall_misses::total 489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31431750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31431750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31431750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31431750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31431750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31431750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2388 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2388 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2388 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2388 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204774 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204774 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204774 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204774 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204774 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204774 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64277.607362 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64277.607362 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64277.607362 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64277.607362 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31330250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31330250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31330250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31330250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31330250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31330250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64070.040900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64070.040900 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,34 +670,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22098000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22098000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22098000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22098000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22098000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22098000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131910 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131910 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131910 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70152.380952 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70152.380952 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22016000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22016000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22016000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22016000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22016000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22016000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 219.244506 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.258059 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.494883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.749622 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004867 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.507047 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.751013 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006691 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id @@ -684,17 +723,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7725500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29497500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5467500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5467500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13193000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34965000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21772000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13193000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34965000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21690000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29408000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21690000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13435750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35125750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21690000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13435750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35125750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) @@ -717,17 +756,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69337.579618 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76490.099010 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.313253 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74897.260274 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74897.260274 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71649.590164 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71649.590164 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,17 +786,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488 system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17823000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6485500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4573000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4573000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17823000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11058500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28881500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17823000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11058500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28881500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17737500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6477000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24214500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4818250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4818250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11295250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29032750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17737500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11295250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29032750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses @@ -769,41 +808,41 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56761.146497 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64212.871287 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58574.698795 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58348.192771 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66003.424658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66003.424658 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.267771 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.231811 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2229 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.810345 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.267771 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026188 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026188 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 107.231811 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026180 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026180 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5694 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5694 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits -system.cpu.dcache.overall_hits::total 2230 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2229 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2229 # number of overall hits +system.cpu.dcache.overall_hits::total 2229 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -812,43 +851,43 @@ system.cpu.dcache.demand_misses::cpu.data 530 # n system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses system.cpu.dcache.overall_misses::total 530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11467500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11467500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23223733 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23223733 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34691233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34691233 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34691233 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34691233 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11460500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11460500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25449978 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25449978 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36910478 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36910478 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36910478 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36910478 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090237 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.090237 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090285 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.090285 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.192029 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.192029 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.192029 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.192029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65455.156604 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65455.156604 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1533 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.192099 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.192099 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.192099 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.192099 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69642.411321 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69642.411321 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1529 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.862069 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.970588 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -868,30 +907,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5462500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5462500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13377500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13377500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13377500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13377500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7907500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7907500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5712750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5712750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13620250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13620250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13620250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13620250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053854 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053854 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 53f3ae2a8..60119bd53 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3208000 # Number of ticks simulated final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105446 # Simulator instruction rate (inst/s) -host_op_rate 105415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52907298 # Simulator tick rate (ticks/s) -host_mem_usage 268408 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 172950 # Simulator instruction rate (inst/s) +host_op_rate 172880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 86758979 # Simulator tick rate (ticks/s) +host_mem_usage 253924 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 6417 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 913b33750..351b1338b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138616 # Number of ticks simulated final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14698 # Simulator instruction rate (inst/s) -host_op_rate 14697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 318804 # Simulator tick rate (ticks/s) -host_mem_usage 174728 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host +host_inst_rate 36011 # Simulator instruction rate (inst/s) +host_op_rate 36008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 781041 # Simulator tick rate (ticks/s) +host_mem_usage 161164 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -210,6 +210,41 @@ system.cpu.num_busy_cycles 138616 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.369871 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index f70111f0d..a76851914 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000118 # Nu sim_ticks 117611 # Number of ticks simulated final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 21881 # Simulator instruction rate (inst/s) -host_op_rate 21879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 402676 # Simulator tick rate (ticks/s) -host_mem_usage 177980 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 31716 # Simulator instruction rate (inst/s) +host_op_rate 31714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 583663 # Simulator tick rate (ticks/s) +host_mem_usage 164416 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,6 +200,41 @@ system.cpu.num_busy_cycles 117611 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.786874 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1109 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 253 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index e6916bab3..706264b43 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000114 # Nu sim_ticks 113627 # Number of ticks simulated final_tick 113627 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28822 # Simulator instruction rate (inst/s) -host_op_rate 28819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 512426 # Simulator tick rate (ticks/s) -host_mem_usage 175880 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 50343 # Simulator instruction rate (inst/s) +host_op_rate 50337 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 894983 # Simulator tick rate (ticks/s) +host_mem_usage 161272 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,6 +186,41 @@ system.cpu.num_busy_cycles 113627 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.473611 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1178 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 66f09eeb4..29b31fb1d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000093 # Nu sim_ticks 93341 # Number of ticks simulated final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 31508 # Simulator instruction rate (inst/s) -host_op_rate 31505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 460155 # Simulator tick rate (ticks/s) -host_mem_usage 175808 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 52665 # Simulator instruction rate (inst/s) +host_op_rate 52659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 769125 # Simulator tick rate (ticks/s) +host_mem_usage 161200 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -185,6 +185,41 @@ system.cpu.num_busy_cycles 93341 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.199848 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index d0515d3c9..17ffa2150 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000144 # Nu sim_ticks 143853 # Number of ticks simulated final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14935 # Simulator instruction rate (inst/s) -host_op_rate 14935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 336198 # Simulator tick rate (ticks/s) -host_mem_usage 174340 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host +host_inst_rate 53676 # Simulator instruction rate (inst/s) +host_op_rate 53669 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1208067 # Simulator tick rate (ticks/s) +host_mem_usage 160752 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -160,6 +160,41 @@ system.cpu.num_busy_cycles 143853 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.011692 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 72bd7571c..e6ec389d1 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163681 # Simulator instruction rate (inst/s) -host_op_rate 163603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 832819326 # Simulator tick rate (ticks/s) -host_mem_usage 277116 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 550056 # Simulator instruction rate (inst/s) +host_op_rate 549394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2794675827 # Simulator tick rate (ticks/s) +host_mem_usage 262632 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 65088 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 88231a1ee..5be5fa9ed 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12006500 # Number of ticks simulated -final_tick 12006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11975500 # Number of ticks simulated +final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60243 # Simulator instruction rate (inst/s) -host_op_rate 60220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 302796832 # Simulator tick rate (ticks/s) -host_mem_usage 264400 # Number of bytes of host memory used +host_inst_rate 56599 # Simulator instruction rate (inst/s) +host_op_rate 56579 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 283759448 # Simulator tick rate (ticks/s) +host_mem_usage 265424 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1002123850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 453087911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1455211760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1002123850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1002123850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1002123850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 453087911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1455211760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1004717966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 454260782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1458978748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1004717966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1004717966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1004717966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 454260782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1458978748 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 273 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11917000 # Total gap between requests +system.physmem.totGap 11886000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,33 +186,33 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 24 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 464 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 290.487911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.347726 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4 16.67% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 12.50% 54.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 4.17% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 8.33% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 8.33% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 25.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 24 # Bytes accessed per row activation -system.physmem.totQLat 1638000 # Total ticks spent queuing -system.physmem.totMemAccLat 7265500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 38 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.368421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.223359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 366.580725 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14 36.84% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 13.16% 50.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 10.53% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 5.26% 65.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 5.26% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 5.26% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 5.26% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 2.63% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 15.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38 # Bytes accessed per row activation +system.physmem.totQLat 2067500 # Total ticks spent queuing +system.physmem.totMemAccLat 7186250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers -system.physmem.totBankLat 4262500 # Total ticks spent accessing banks -system.physmem.avgQLat 6000.00 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15613.55 # Average bank access latency per DRAM burst +system.physmem.avgQLat 7573.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26613.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1455.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26323.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1458.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1455.21 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1458.98 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.37 # Data bus utilization in percentage -system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.40 # Data bus utilization in percentage +system.physmem.busUtilRead 11.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,10 +220,14 @@ system.physmem.readRowHits 225 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43652.01 # Average gap between requests +system.physmem.avgGap 43538.46 # Average gap between requests system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1455211760 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem.memoryStateTime::REF 260000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 7796750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1458978748 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 249 # Transaction distribution system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution @@ -234,9 +238,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 344500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2552500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2556250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1176 # Number of BP lookups @@ -281,42 +285,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 24014 # number of cpu cycles simulated +system.cpu.numCycles 23952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 4342 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 531 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.907925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.314691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.909929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.316850 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6513 84.34% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 176 2.28% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 76 0.98% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.83% 91.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.84% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6496 84.31% 84.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.69% 85.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.49% 86.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.23% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 2.28% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 76 0.99% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.83% 91.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.84% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.048971 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.291955 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5487 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 7705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.292710 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5480 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 569 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1153 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing @@ -325,9 +329,9 @@ system.cpu.decode.BranchMispred 81 # Nu system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5585 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 5578 # Number of cycles rename is idle system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1063 # Number of cycles rename is running system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 5900 # Number of instructions processed by rename @@ -354,23 +358,23 @@ system.cpu.iq.iqSquashedInstsIssued 54 # Nu system.cpu.iq.iqSquashedInstsExamined 2341 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 1389 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7722 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.523828 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.238657 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.524984 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.239779 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6098 78.97% 78.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 565 7.32% 86.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 401 5.19% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.41% 94.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 200 2.59% 97.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 120 1.55% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6081 78.92% 78.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 565 7.33% 86.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 401 5.20% 91.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 263 3.41% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 200 2.60% 97.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 120 1.56% 99.03% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7705 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available @@ -440,10 +444,10 @@ system.cpu.iq.FU_type_0::MemWrite 395 9.77% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 4045 # Type of FU issued -system.cpu.iq.rate 0.168443 # Inst issue rate +system.cpu.iq.rate 0.168879 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010878 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15897 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 15880 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 7311 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3652 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads @@ -484,26 +488,26 @@ system.cpu.iew.exec_nop 336 # nu system.cpu.iew.exec_refs 1130 # number of memory reference insts executed system.cpu.iew.exec_branches 644 # Number of branches executed system.cpu.iew.exec_stores 388 # Number of stores executed -system.cpu.iew.exec_rate 0.160531 # Inst execution rate +system.cpu.iew.exec_rate 0.160947 # Inst execution rate system.cpu.iew.wb_sent 3738 # cumulative count of insts sent to commit system.cpu.iew.wb_count 3658 # cumulative count of insts written-back system.cpu.iew.wb_producers 1710 # num instructions producing a value system.cpu.iew.wb_consumers 2211 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152328 # insts written-back per cycle +system.cpu.iew.wb_rate 0.152722 # insts written-back per cycle system.cpu.iew.wb_fanout 0.773406 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 2726 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7228 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.356392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.198445 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 7211 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.357232 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199732 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6359 87.98% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6342 87.95% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.83% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.27% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.58% 96.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle @@ -512,7 +516,7 @@ system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7228 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7211 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -523,25 +527,60 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 2576 # Class of committed instruction system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12220 # The number of ROB reads +system.cpu.rob.rob_reads 12203 # The number of ROB reads system.cpu.rob.rob_writes 11111 # The number of ROB writes -system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16292 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16247 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 10.060327 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.060327 # CPI: Total CPI of All Threads -system.cpu.ipc 0.099400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.099400 # IPC: Total IPC of All Threads +system.cpu.cpi 10.034353 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 4672 # number of integer regfile reads system.cpu.int_regfile_writes 2825 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1455211760 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1458978748 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -556,19 +595,19 @@ system.cpu.toL2Bus.data_through_bus 17472 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 315500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 316750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 133500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 93.163170 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 93.052511 # Cycle average of tags in use system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 93.163170 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.045490 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.045490 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 93.052511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.045436 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.045436 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id @@ -587,12 +626,12 @@ system.cpu.icache.demand_misses::cpu.inst 250 # n system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17591499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17591499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17591499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17591499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17591499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17591499 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17506249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17506249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17506249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17506249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17506249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17506249 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses @@ -605,12 +644,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70365.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70365.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70365.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70365.996000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70024.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70024.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70024.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70024.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -631,36 +670,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 188 system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13162249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13162249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13162249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13110499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13110499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13110499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13110499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13110499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13110499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70011.962766 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70011.962766 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69736.696809 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69736.696809 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 122.028433 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 121.888429 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.360563 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.667870 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002849 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003720 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 249 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -678,17 +717,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12973500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4680750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17654250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1693750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1693750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12973500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6374500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19348000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12973500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6374500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19348000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12921750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17574250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1688000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1688000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12921750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6340500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19262250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12921750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6340500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19262250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -711,17 +750,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69007.978723 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76733.606557 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70900.602410 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70572.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70572.916667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70871.794872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70871.794872 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68732.712766 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76270.491803 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70579.317269 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70557.692308 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70557.692308 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,17 +780,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10603500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3934250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14537750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1399750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1399750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10603500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5334000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15937500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10603500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5334000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15937500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14452750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1393500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1393500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5298500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5298500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15846250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -763,30 +802,30 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56401.595745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64495.901639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58384.538153 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58322.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58322.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56105.053191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64016.393443 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58043.172691 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58062.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58062.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.630537 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.583444 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 759 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.929412 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.630537 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011140 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011140 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.583444 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011129 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011129 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1995 # Number of data accesses @@ -806,14 +845,14 @@ system.cpu.dcache.demand_misses::cpu.data 196 # n system.cpu.dcache.demand_misses::total 196 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 196 # number of overall misses system.cpu.dcache.overall_misses::total 196 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7964000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5323250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5323250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13287250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13287250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13287250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13287250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7876750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7876750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5302250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5302250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13179000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13179000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13179000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13179000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -830,14 +869,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.205236 system.cpu.dcache.demand_miss_rate::total 0.205236 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.205236 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.205236 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69252.173913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69252.173913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65719.135802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65719.135802 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67792.091837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67792.091837 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65459.876543 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67239.795918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67239.795918 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -862,14 +901,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6461000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6461000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6427000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6427000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6427000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6427000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -878,14 +917,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089005 system.cpu.dcache.demand_mshr_miss_rate::total 0.089005 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.089005 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77733.606557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77733.606557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71635.416667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71635.416667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77270.491803 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77270.491803 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 2cd66ec8a..6080ce665 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59390 # Simulator instruction rate (inst/s) -host_op_rate 59366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29878318 # Simulator tick rate (ticks/s) -host_mem_usage 267100 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 741583 # Simulator instruction rate (inst/s) +host_op_rate 738395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 370291096 # Simulator tick rate (ticks/s) +host_mem_usage 253628 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 2596 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 944c5b9f4..d01144a54 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu sim_ticks 52548 # Number of ticks simulated final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 15623 # Simulator instruction rate (inst/s) -host_op_rate 15622 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 318507 # Simulator tick rate (ticks/s) -host_mem_usage 173288 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 36298 # Simulator instruction rate (inst/s) +host_op_rate 36291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 739863 # Simulator tick rate (ticks/s) +host_mem_usage 159844 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -209,6 +209,41 @@ system.cpu.num_busy_cycles 52548 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.426467 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 215db9928..99c36fa52 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000045 # Nu sim_ticks 44968 # Number of ticks simulated final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18935 # Simulator instruction rate (inst/s) -host_op_rate 18932 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 330302 # Simulator tick rate (ticks/s) -host_mem_usage 175652 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 32543 # Simulator instruction rate (inst/s) +host_op_rate 32537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 567670 # Simulator tick rate (ticks/s) +host_mem_usage 162088 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,6 +200,41 @@ system.cpu.num_busy_cycles 44968 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.661804 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 423 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 87 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index eecde778c..c5b73657d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000043 # Nu sim_ticks 43073 # Number of ticks simulated final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22164 # Simulator instruction rate (inst/s) -host_op_rate 22160 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 370326 # Simulator tick rate (ticks/s) -host_mem_usage 173416 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 51660 # Simulator instruction rate (inst/s) +host_op_rate 51645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 862979 # Simulator tick rate (ticks/s) +host_mem_usage 159984 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,6 +186,41 @@ system.cpu.num_busy_cycles 43073 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.412904 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 293fb7685..3c031887e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu sim_ticks 35432 # Number of ticks simulated final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22204 # Simulator instruction rate (inst/s) -host_op_rate 22201 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 305145 # Simulator tick rate (ticks/s) -host_mem_usage 174496 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 51262 # Simulator instruction rate (inst/s) +host_op_rate 51245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 704386 # Simulator tick rate (ticks/s) +host_mem_usage 159904 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -184,6 +184,41 @@ system.cpu.num_busy_cycles 35432 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.200610 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 8be4f5dad..c9a4a26c5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu sim_ticks 52498 # Number of ticks simulated final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 10658 # Simulator instruction rate (inst/s) -host_op_rate 10657 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 217095 # Simulator tick rate (ticks/s) -host_mem_usage 172908 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 55191 # Simulator instruction rate (inst/s) +host_op_rate 55175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1123673 # Simulator tick rate (ticks/s) +host_mem_usage 158428 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -159,6 +159,41 @@ system.cpu.num_busy_cycles 52498 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.958322 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 4ab5ef724..3ccccfd43 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56666 # Simulator instruction rate (inst/s) -host_op_rate 56644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 363064230 # Simulator tick rate (ticks/s) -host_mem_usage 275808 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 366311 # Simulator instruction rate (inst/s) +host_op_rate 365532 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2339184598 # Simulator tick rate (ticks/s) +host_mem_usage 262348 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 33048 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. |