diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
| commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
| tree | 81108e7ff1951b652258f53bd5615a617b734ce2 /tests/quick/se/00.hello/ref/alpha | |
| parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
| download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz | |
update stats for preceeding changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha')
9 files changed, 1347 insertions, 1295 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index f7aca5bc7..ab195624f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -62,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -92,22 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,22 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -148,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -155,24 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -182,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -200,7 +204,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -222,15 +226,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index da760535c..05dfd62f0 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 16:51:51 -gem5 started Aug 13 2012 17:17:12 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:20:12 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21979500 because target called exit() +Exiting @ tick 18737000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 823f9b4c3..6769b3cad 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18769500 # Number of ticks simulated -final_tick 18769500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18737000 # Number of ticks simulated +final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10228 # Simulator instruction rate (inst/s) -host_op_rate 10227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30039955 # Simulator tick rate (ticks/s) -host_mem_usage 216300 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host +host_inst_rate 37767 # Simulator instruction rate (inst/s) +host_op_rate 37763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110721753 # Simulator tick rate (ticks/s) +host_mem_usage 213516 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1022936146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 572844242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1595780388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1022936146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1022936146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1022936146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 572844242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1595780388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1024710466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 573837861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1598548327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1024710466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1024710466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1024710466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 573837861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1598548327 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18755000 # Total gap between requests +system.physmem.totGap 18722500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -165,26 +165,26 @@ system.physmem.wrQLenPdf::30 0 # Wh system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 1862969 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11662969 # Sum of mem lat for all requests +system.physmem.totMemAccLat 11648969 # Sum of mem lat for all requests system.physmem.totBusLat 1876000 # Total cycles spent in databus access -system.physmem.totBankLat 7924000 # Total cycles spent in bank access +system.physmem.totBankLat 7910000 # Total cycles spent in bank access system.physmem.avgQLat 3972.22 # Average queueing delay per request -system.physmem.avgBankLat 16895.52 # Average bank access latency per request +system.physmem.avgBankLat 16865.67 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24867.74 # Average memory access latency -system.physmem.avgRdBW 1595.78 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24837.89 # Average memory access latency +system.physmem.avgRdBW 1598.55 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1595.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1598.55 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.97 # Data bus utilization in percentage +system.physmem.busUtil 9.99 # Data bus utilization in percentage system.physmem.avgRdQLen 0.62 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 401 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 39989.34 # Average gap between requests +system.physmem.avgGap 39920.04 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -201,10 +201,10 @@ system.cpu.dtb.data_hits 2048 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 909 # ITB hits +system.cpu.itb.fetch_hits 915 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 926 # ITB accesses +system.cpu.itb.fetch_accesses 932 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 37540 # number of cpu cycles simulated +system.cpu.numCycles 37475 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1605 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1125 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 713 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1185 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits +system.cpu.branch_predictor.lookups 1632 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1160 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 706 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1266 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 352 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 26.497890 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1141 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5235 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 27.804107 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9802 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9769 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2929 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2181 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 368 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 652 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 399 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.036156 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4462 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 2948 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2152 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 645 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 406 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.370124 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 4448 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11564 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11520 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 496 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30143 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7397 # Number of cycles cpu stages are processed. -system.cpu.activity 19.704315 # Percentage of cycles cpu is active +system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30101 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7374 # Number of cycles cpu stages are processed. +system.cpu.activity 19.677118 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -265,72 +265,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 5.874804 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 5.864632 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 5.874804 # CPI: Total CPI of All Threads -system.cpu.ipc 0.170218 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 5.864632 # CPI: Total CPI of All Threads +system.cpu.ipc 0.170514 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.170218 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32631 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4909 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.076718 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33667 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3873 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 10.316995 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33372 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4168 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 11.102824 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36235 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.170514 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32551 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 13.139426 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33582 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 10.388259 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33313 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4162 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 11.106071 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 36170 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.476292 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33023 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4517 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 12.032499 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.482322 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 32961 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4514 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 12.045364 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.255742 # Cycle average of tags in use -system.cpu.icache.total_refs 556 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 143.133594 # Cycle average of tags in use +system.cpu.icache.total_refs 561 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.847176 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.863787 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.255742 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069949 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069949 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 556 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 556 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 556 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 556 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 556 # number of overall hits -system.cpu.icache.overall_hits::total 556 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 353 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 353 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 353 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 353 # number of overall misses -system.cpu.icache.overall_misses::total 353 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17380500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17380500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17380500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17380500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17380500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17380500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 909 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.388339 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.388339 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.388339 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.388339 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.388339 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.388339 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49236.543909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49236.543909 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49236.543909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49236.543909 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 143.133594 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069889 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069889 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 561 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 561 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 561 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 561 # number of overall hits +system.cpu.icache.overall_hits::total 561 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 354 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 354 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 354 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 354 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 354 # number of overall misses +system.cpu.icache.overall_misses::total 354 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17402500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17402500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17402500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17402500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17402500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17402500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 915 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49159.604520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49159.604520 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -339,154 +339,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51 # 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mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332233 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.332233 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.332233 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48890.728477 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48890.728477 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14751500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14751500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48846.026490 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48846.026490 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 104.285094 # Cycle average of tags in use -system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 104.285094 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025460 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025460 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 515 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5354500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14914000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14914000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20268500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20268500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20268500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20268500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55201.030928 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55201.030928 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42611.428571 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42611.428571 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45343.400447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45343.400447 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # 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number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8753000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8753000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53463.157895 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53463.157895 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50328.767123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50328.767123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52101.190476 # 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Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006113 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 143.234891 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.932349 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006109 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -504,17 +398,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14446500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19424000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3596500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14446500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8574000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23020500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14446500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8574000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23020500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14433000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4976500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19409500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3596000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14433000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8572500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23005500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14433000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8572500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23005500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -537,17 +431,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47995.016611 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52394.736842 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49050.505051 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49267.123288 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49084.221748 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49084.221748 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47950.166113 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52384.210526 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49013.888889 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49260.273973 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49260.273973 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49052.238806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49052.238806 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -567,17 +461,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10662000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10648000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14454120 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14440120 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10662000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10648000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17128216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10662000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17114216 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10648000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17128216 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17114216 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -589,17 +483,123 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35421.926910 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35375.415282 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36500.303030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36464.949495 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 104.225653 # Cycle average of tags in use +system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 104.225653 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025446 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025446 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 515 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1601 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1601 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1601 # number of overall hits +system.cpu.dcache.overall_hits::total 1601 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 350 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 350 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 447 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses +system.cpu.dcache.overall_misses::total 447 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5353500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5353500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14913500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20267000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20267000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20267000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20267000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55190.721649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55190.721649 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42610 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42610 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45340.044743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45340.044743 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3673500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3673500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8751500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8751500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53452.631579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53452.631579 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50321.917808 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50321.917808 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 6c764cc38..8465ac1d0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -448,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -455,24 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +504,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -522,15 +526,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index a77141c3d..9cdc62046 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 16:51:51 -gem5 started Aug 13 2012 17:17:12 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:20:12 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12735500 because target called exit() +Exiting @ tick 15802500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index fb45a6f1f..56f807ea0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 15653000 # Number of ticks simulated -final_tick 15653000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15802500 # Number of ticks simulated +final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 11804 # Simulator instruction rate (inst/s) -host_op_rate 11803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28994780 # Simulator tick rate (ticks/s) -host_mem_usage 217308 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host +host_inst_rate 38730 # Simulator instruction rate (inst/s) +host_op_rate 38726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96032767 # Simulator tick rate (ticks/s) +host_mem_usage 214332 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1279754680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 711429119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1991183799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1279754680 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1279754680 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1279754680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 711429119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1991183799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1267647524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 704698624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1972346148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1267647524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1267647524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1267647524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 704698624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1972346148 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 487 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady @@ -41,12 +41,12 @@ system.physmem.perBankRdReqs::1 18 # Tr system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 73 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15508000 # Total gap between requests +system.physmem.totGap 15655000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -99,9 +99,9 @@ system.physmem.neitherpktsize::6 0 # ca system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2668987 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12414987 # Sum of mem lat for all requests +system.physmem.totQLat 3073487 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12819487 # Sum of mem lat for all requests system.physmem.totBusLat 1948000 # Total cycles spent in databus access system.physmem.totBankLat 7798000 # Total cycles spent in bank access -system.physmem.avgQLat 5480.47 # Average queueing delay per request +system.physmem.avgQLat 6311.06 # Average queueing delay per request system.physmem.avgBankLat 16012.32 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25492.79 # Average memory access latency -system.physmem.avgRdBW 1991.18 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26323.38 # Average memory access latency +system.physmem.avgRdBW 1972.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1991.18 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1972.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.44 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.busUtil 12.33 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.81 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 417 # Number of row buffer hits during reads +system.physmem.readRowHits 416 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 31843.94 # Average gap between requests +system.physmem.avgGap 32145.79 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2048 # DTB read hits -system.cpu.dtb.read_misses 58 # DTB read misses +system.cpu.dtb.read_hits 2068 # DTB read hits +system.cpu.dtb.read_misses 50 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2106 # DTB read accesses -system.cpu.dtb.write_hits 1074 # DTB write hits -system.cpu.dtb.write_misses 32 # DTB write misses +system.cpu.dtb.read_accesses 2118 # DTB read accesses +system.cpu.dtb.write_hits 1071 # DTB write hits +system.cpu.dtb.write_misses 29 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1106 # DTB write accesses -system.cpu.dtb.data_hits 3122 # DTB hits -system.cpu.dtb.data_misses 90 # DTB misses +system.cpu.dtb.write_accesses 1100 # DTB write accesses +system.cpu.dtb.data_hits 3139 # DTB hits +system.cpu.dtb.data_misses 79 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3212 # DTB accesses -system.cpu.itb.fetch_hits 2395 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 3218 # DTB accesses +system.cpu.itb.fetch_hits 2370 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2433 # ITB accesses +system.cpu.itb.fetch_accesses 2409 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,243 +218,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 31307 # number of cpu cycles simulated +system.cpu.numCycles 31606 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2894 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1701 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 520 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2227 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits +system.cpu.BPredUnit.lookups 2927 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1718 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 517 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2238 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 757 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 422 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8391 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16487 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1236 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2984 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1891 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 950 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 757 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2395 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 373 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.145010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.528367 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 420 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1177 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2985 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1897 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1074 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 762 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2370 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.161487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.555904 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11415 79.28% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 325 2.26% 81.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 232 1.61% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 251 1.74% 84.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 272 1.89% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 212 1.47% 88.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 276 1.92% 90.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 187 1.30% 91.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1229 8.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11431 79.29% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 317 2.20% 81.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 233 1.62% 83.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 212 1.47% 84.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 264 1.83% 86.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 229 1.59% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 265 1.84% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 186 1.29% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1279 8.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.092439 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.526623 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9352 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 969 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 14416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.092609 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.529773 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9179 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1146 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2779 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1211 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch +system.cpu.decode.UnblockCycles 90 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1222 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 249 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15295 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1211 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 276 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 373 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2656 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 325 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14562 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 299 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18155 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18138 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 15526 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1222 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9389 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 326 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2653 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 349 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14793 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 317 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 11113 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18446 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18429 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 714 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2751 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1359 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 6543 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 811 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2756 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12925 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10660 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6224 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3683 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.740329 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373860 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10819 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6341 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.391653 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9938 69.02% 69.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1614 11.21% 80.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1141 7.92% 88.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 759 5.27% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 488 3.39% 96.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 274 1.90% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 143 0.99% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.20% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9926 68.85% 68.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1619 11.23% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1135 7.87% 87.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 768 5.33% 93.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 481 3.34% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 285 1.98% 98.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 151 1.05% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 37 0.26% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14399 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14416 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 7.89% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 66 57.89% 65.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 34.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 14 11.97% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 64 54.70% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7159 67.16% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2350 22.05% 89.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1146 10.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7317 67.63% 67.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2355 21.77% 89.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1142 10.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10660 # Type of FU issued -system.cpu.iq.rate 0.340499 # Inst issue rate -system.cpu.iq.fu_busy_cnt 114 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010694 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35869 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19185 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9545 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10819 # Type of FU issued +system.cpu.iq.rate 0.342308 # Inst issue rate +system.cpu.iq.fu_busy_cnt 117 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010814 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19446 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9723 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10761 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10923 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1568 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1573 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 494 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 92 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 90 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1211 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13042 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2751 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1359 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1222 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 52 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13186 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 157 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2756 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1363 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 376 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 520 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10013 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2117 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 647 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 522 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10167 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88 # number of nop insts executed -system.cpu.iew.exec_refs 3225 # number of memory reference insts executed -system.cpu.iew.exec_branches 1609 # Number of branches executed -system.cpu.iew.exec_stores 1108 # Number of stores executed -system.cpu.iew.exec_rate 0.319833 # Inst execution rate -system.cpu.iew.wb_sent 9713 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9555 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5016 # num instructions producing a value -system.cpu.iew.wb_consumers 6802 # num instructions consuming a value +system.cpu.iew.exec_nop 87 # number of nop insts executed +system.cpu.iew.exec_refs 3231 # number of memory reference insts executed +system.cpu.iew.exec_branches 1614 # Number of branches executed +system.cpu.iew.exec_stores 1102 # Number of stores executed +system.cpu.iew.exec_rate 0.321679 # Inst execution rate +system.cpu.iew.wb_sent 9882 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9733 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5145 # num instructions producing a value +system.cpu.iew.wb_consumers 6933 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.305203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737430 # average fanout of values written-back +system.cpu.iew.wb_rate 0.307948 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742103 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6652 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6795 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 438 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13188 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.484456 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.302208 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 435 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.484235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.303292 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10412 78.95% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1478 11.21% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 518 3.93% 94.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 238 1.80% 95.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 160 1.21% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.71% 97.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 109 0.83% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.27% 98.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 144 1.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10420 78.98% 78.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1475 11.18% 90.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 517 3.92% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 247 1.87% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 154 1.17% 97.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 92 0.70% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.80% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 146 1.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13194 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -465,70 +466,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 144 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 146 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25734 # The number of ROB reads -system.cpu.rob.rob_writes 27303 # The number of ROB writes -system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25881 # The number of ROB reads +system.cpu.rob.rob_writes 27599 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17190 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 4.913214 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.913214 # CPI: Total CPI of All Threads -system.cpu.ipc 0.203533 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.203533 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12695 # number of integer regfile reads -system.cpu.int_regfile_writes 7186 # number of integer regfile writes +system.cpu.cpi 4.960138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.960138 # CPI: Total CPI of All Threads +system.cpu.ipc 0.201607 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.201607 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12907 # number of integer regfile reads +system.cpu.int_regfile_writes 7365 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.377030 # Cycle average of tags in use -system.cpu.icache.total_refs 1916 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 160.479269 # Cycle average of tags in use +system.cpu.icache.total_refs 1894 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.101911 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 6.031847 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.377030 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078309 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078309 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1916 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1916 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1916 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1916 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1916 # number of overall hits -system.cpu.icache.overall_hits::total 1916 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses -system.cpu.icache.overall_misses::total 479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21334000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21334000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21334000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21334000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21334000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21334000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2395 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2395 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2395 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2395 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2395 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2395 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.200000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.200000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.200000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.200000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44538.622129 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44538.622129 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44538.622129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44538.622129 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 160.479269 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078359 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078359 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1894 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1894 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1894 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1894 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1894 # number of overall hits +system.cpu.icache.overall_hits::total 1894 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 476 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 476 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 476 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 476 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 476 # number of overall misses +system.cpu.icache.overall_misses::total 476 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21386500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21386500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21386500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21386500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21386500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21386500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2370 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2370 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2370 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2370 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2370 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2370 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200844 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.200844 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.200844 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.200844 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.200844 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.200844 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44929.621849 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44929.621849 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44929.621849 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44929.621849 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,154 +538,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 162 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 162 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 162 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 162 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15306500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15306500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15306500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15306500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15306500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15306500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131106 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131106 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131106 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48746.815287 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48746.815287 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15404000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15404000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15404000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15404000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15404000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15404000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132489 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.132489 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.132489 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49057.324841 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49057.324841 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.831538 # Cycle average of tags in use -system.cpu.dcache.total_refs 2240 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.831538 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026326 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026326 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2240 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits 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of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15746484 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24054984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24054984 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24054984 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24054984 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2759 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ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51928.125000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43862.072423 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43862.072423 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46348.716763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46348.716763 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 810 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of 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misses +system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses +system.cpu.dcache.overall_misses::total 528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9065500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9065500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15837484 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15837484 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24902984 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24902984 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24902984 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24902984 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2792 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2792 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2792 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2792 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087701 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087701 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.189112 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.189112 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.189112 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.189112 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53642.011834 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53642.011834 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44115.554318 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44115.554318 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47164.742424 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47164.742424 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 801 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807692 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3813500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3813500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10132500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10132500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10132500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10132500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052413 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052413 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062321 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062321 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62564.356436 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62564.356436 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52239.726027 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52239.726027 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 35d1c924c..4d782f4dd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -448,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -455,24 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +504,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -522,15 +526,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 07442c5d8..8f40149c5 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:08:29 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:20:24 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7252000 because target called exit() +Exiting @ tick 9059000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 9eea9fb92..f9cbb8511 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9061000 # Number of ticks simulated -final_tick 9061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 9059000 # Number of ticks simulated +final_tick 9059000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62320 # Simulator instruction rate (inst/s) -host_op_rate 62299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 236406021 # Simulator tick rate (ticks/s) -host_mem_usage 216020 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 28083 # Simulator instruction rate (inst/s) +host_op_rate 28078 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106544733 # Simulator tick rate (ticks/s) +host_mem_usage 213348 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1320825516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 600375235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1921200750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1320825516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1320825516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1320825516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 600375235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1921200750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1321117121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 600507782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1921624903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1321117121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1321117121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1321117121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 600507782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1921624903 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady @@ -36,7 +36,7 @@ system.physmem.bytesConsumedRd 17408 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis @@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 27 # Tr system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 8992500 # Total gap between requests +system.physmem.totGap 8990500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -100,8 +100,8 @@ system.physmem.neitherpktsize::7 0 # ca system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1105772 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6813772 # Sum of mem lat for all requests +system.physmem.totQLat 1180771 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6930771 # Sum of mem lat for all requests system.physmem.totBusLat 1088000 # Total cycles spent in databus access -system.physmem.totBankLat 4620000 # Total cycles spent in bank access -system.physmem.avgQLat 4065.34 # Average queueing delay per request -system.physmem.avgBankLat 16985.29 # Average bank access latency per request +system.physmem.totBankLat 4662000 # Total cycles spent in bank access +system.physmem.avgQLat 4341.07 # Average queueing delay per request +system.physmem.avgBankLat 17139.71 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25050.63 # Average memory access latency -system.physmem.avgRdBW 1921.20 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25480.78 # Average memory access latency +system.physmem.avgRdBW 1921.62 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1921.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1921.62 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 12.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.75 # Average read queue length over time +system.physmem.avgRdQLen 0.77 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 228 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33060.66 # Average gap between requests +system.physmem.avgGap 33053.31 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 743 # DTB read hits -system.cpu.dtb.read_misses 38 # DTB read misses +system.cpu.dtb.read_hits 717 # DTB read hits +system.cpu.dtb.read_misses 25 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 781 # DTB read accesses -system.cpu.dtb.write_hits 387 # DTB write hits -system.cpu.dtb.write_misses 24 # DTB write misses +system.cpu.dtb.read_accesses 742 # DTB read accesses +system.cpu.dtb.write_hits 359 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 411 # DTB write accesses -system.cpu.dtb.data_hits 1130 # DTB hits -system.cpu.dtb.data_misses 62 # DTB misses +system.cpu.dtb.write_accesses 378 # DTB write accesses +system.cpu.dtb.data_hits 1076 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1192 # DTB accesses -system.cpu.itb.fetch_hits 1097 # ITB hits +system.cpu.dtb.data_accesses 1120 # DTB accesses +system.cpu.itb.fetch_hits 1063 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1127 # ITB accesses +system.cpu.itb.fetch_accesses 1093 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,245 +218,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 18123 # number of cpu cycles simulated +system.cpu.numCycles 18119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1200 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 612 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 260 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 849 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 266 # Number of BTB hits +system.cpu.BPredUnit.lookups 1180 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 594 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 261 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 806 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 235 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 229 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 227 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4258 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7288 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 495 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1268 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 917 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 438 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4211 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7069 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1180 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 462 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1219 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 881 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 344 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 961 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 959 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1097 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.961604 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.365122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1063 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 190 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.961769 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.375037 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6311 83.27% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.70% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 134 1.77% 85.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 102 1.35% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 181 2.39% 89.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 82 1.08% 90.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 68 0.90% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.86% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 583 7.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6131 83.41% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57 0.78% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 120 1.63% 85.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.29% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 168 2.29% 89.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 73 0.99% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 67 0.91% 91.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.87% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 575 7.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.066214 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.402141 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5340 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 471 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1207 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 547 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 173 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6471 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 7350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065125 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.390143 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5296 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 369 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1168 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 510 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 170 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6269 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 547 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5441 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 165 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 510 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5398 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 91 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1119 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 57 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 6174 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4474 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6979 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6967 # Number of integer rename lookups +system.cpu.rename.RunCycles 1075 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 26 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5981 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4351 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6729 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6717 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2706 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2583 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1006 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 508 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5283 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 979 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 463 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5055 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4254 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2663 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1563 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4086 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2501 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1445 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7579 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.561288 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.273203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.555918 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.264810 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5858 77.29% 77.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 621 8.19% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 415 5.48% 90.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.44% 94.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 216 2.85% 97.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 132 1.74% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 51 0.67% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.13% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5719 77.81% 77.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 555 7.55% 85.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 404 5.50% 90.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 261 3.55% 94.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 214 2.91% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 126 1.71% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 50 0.68% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14 0.19% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7579 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7350 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.13% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 46.81% 48.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 51.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2999 70.50% 70.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 829 19.49% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 425 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2910 71.22% 71.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 789 19.31% 90.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 386 9.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4254 # Type of FU issued -system.cpu.iq.rate 0.234729 # Inst issue rate -system.cpu.iq.fu_busy_cnt 47 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011048 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 16186 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7949 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3830 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4086 # Type of FU issued +system.cpu.iq.rate 0.225509 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010768 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15607 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7560 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3685 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4294 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4123 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 591 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 564 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 214 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 169 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 547 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5652 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1006 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 508 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 510 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 82 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5405 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 979 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 463 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 155 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 217 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 4043 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 782 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 211 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 218 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3887 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 743 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 199 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363 # number of nop insts executed -system.cpu.iew.exec_refs 1193 # number of memory reference insts executed -system.cpu.iew.exec_branches 672 # Number of branches executed -system.cpu.iew.exec_stores 411 # Number of stores executed -system.cpu.iew.exec_rate 0.223087 # Inst execution rate -system.cpu.iew.wb_sent 3934 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3836 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1789 # num instructions producing a value -system.cpu.iew.wb_consumers 2358 # num instructions consuming a value +system.cpu.iew.exec_nop 344 # number of nop insts executed +system.cpu.iew.exec_refs 1121 # number of memory reference insts executed +system.cpu.iew.exec_branches 656 # Number of branches executed +system.cpu.iew.exec_stores 378 # Number of stores executed +system.cpu.iew.exec_rate 0.214526 # Inst execution rate +system.cpu.iew.wb_sent 3770 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3691 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1735 # num instructions producing a value +system.cpu.iew.wb_consumers 2218 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.211665 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.758694 # average fanout of values written-back +system.cpu.iew.wb_rate 0.203709 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.782236 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3067 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2808 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 182 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7032 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.366325 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.202351 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 183 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.234221 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6145 87.39% 87.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 219 3.11% 90.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 312 4.44% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 120 1.71% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 65 0.92% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 56 0.80% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.47% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 21 0.30% 99.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 61 0.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5975 87.35% 87.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 201 2.94% 90.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 309 4.52% 94.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 115 1.68% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 68 0.99% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 49 0.72% 98.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.48% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23 0.34% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7032 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -467,69 +467,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12367 # The number of ROB reads -system.cpu.rob.rob_writes 11843 # The number of ROB writes +system.cpu.rob.rob_reads 11910 # The number of ROB reads +system.cpu.rob.rob_writes 11291 # The number of ROB writes system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 10769 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 7.592375 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.592375 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131711 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131711 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4904 # number of integer regfile reads -system.cpu.int_regfile_writes 2974 # number of integer regfile writes +system.cpu.cpi 7.590700 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.590700 # CPI: Total CPI of All Threads +system.cpu.ipc 0.131740 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.131740 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4685 # number of integer regfile reads +system.cpu.int_regfile_writes 2864 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.415859 # Cycle average of tags in use -system.cpu.icache.total_refs 849 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 92.986102 # Cycle average of tags in use +system.cpu.icache.total_refs 813 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.540107 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.347594 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 92.415859 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045125 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045125 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 849 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 849 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 849 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 849 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 849 # number of overall hits -system.cpu.icache.overall_hits::total 849 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses -system.cpu.icache.overall_misses::total 248 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11771499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11771499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11771499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11771499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11771499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11771499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1097 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1097 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1097 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1097 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.226071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.226071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.226071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.226071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.226071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.226071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47465.721774 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47465.721774 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47465.721774 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47465.721774 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 92.986102 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045403 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045403 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 813 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 813 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 813 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 813 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 813 # number of overall hits +system.cpu.icache.overall_hits::total 813 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11955999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11955999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11955999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11955999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11955999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11955999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1063 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1063 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1063 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47823.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -538,154 +538,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 34 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 61 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9236999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9236999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175917 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.175917 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.175917 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49395.716578 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49395.716578 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.370052 # Cycle average of tags in use -system.cpu.dcache.total_refs 789 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.282353 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.370052 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011077 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011077 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 789 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 789 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 789 # number of overall hits -system.cpu.dcache.overall_hits::total 789 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 123 # 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number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9561500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9561500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 699 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 699 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 993 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 993 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 993 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 993 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175966 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.175966 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.205438 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.205438 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.205438 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.205438 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44280.487805 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44280.487805 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50802.469136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 50802.469136 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46870.098039 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46870.098039 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 119 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 119 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 119 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # 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number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.087268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.087268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.085599 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.085599 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.085599 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.085599 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54909.836066 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54909.836066 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56208.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56208.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55276.470588 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55276.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55276.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55276.470588 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 121.264296 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 121.901566 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 92.675015 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.589281 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002828 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000872 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003701 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 93.245260 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.656305 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003720 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 187 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses @@ -697,17 +591,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8931000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3288500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12219500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1323500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1323500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8931000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4612000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13543000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8931000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4612000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13543000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9049000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3265500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12314500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1324000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1324000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9049000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4589500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13638500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9049000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4589500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13638500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -730,17 +624,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47759.358289 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53909.836066 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49272.177419 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55145.833333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55145.833333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47759.358289 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54258.823529 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49790.441176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47759.358289 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54258.823529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49790.441176 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48390.374332 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53532.786885 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49655.241935 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55166.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55166.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50141.544118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50141.544118 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -760,17 +654,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6582780 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2536058 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9118838 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6701279 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2512062 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9213341 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1027024 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1027024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6582780 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3563082 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10145862 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6582780 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3563082 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10145862 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6701279 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3539086 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10240365 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6701279 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3539086 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10240365 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -782,17 +676,123 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35202.032086 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41574.721311 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36769.508065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35835.716578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41181.344262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37150.568548 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42792.666667 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42792.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 45.425217 # Cycle average of tags in use +system.cpu.dcache.total_refs 774 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 45.425217 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011090 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011090 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits +system.cpu.dcache.overall_hits::total 774 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 192 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 192 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 192 # number of overall misses +system.cpu.dcache.overall_misses::total 192 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5152500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5152500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4115500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9268000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9268000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9268000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9268000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 966 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 966 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 966 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 966 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165179 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.165179 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.198758 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.198758 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.198758 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.198758 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46418.918919 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46418.918919 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50808.641975 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 50808.641975 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48270.833333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48270.833333 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 107 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 107 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 107 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3326500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3326500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4676000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4676000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4676000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4676000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090774 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090774 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087992 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087992 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54532.786885 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54532.786885 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56229.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56229.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |