diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/quick/se/00.hello/ref/alpha | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha')
13 files changed, 1443 insertions, 1450 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index b5554ceae..1a6e00d22 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37623000 # Number of ticks simulated -final_tick 37623000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37552000 # Number of ticks simulated +final_tick 37552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152308 # Simulator instruction rate (inst/s) -host_op_rate 152258 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 894784408 # Simulator tick rate (ticks/s) -host_mem_usage 293572 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 72134 # Simulator instruction rate (inst/s) +host_op_rate 72118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 423067865 # Simulator tick rate (ticks/s) +host_mem_usage 288748 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 619195705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 287483720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 906679425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 619195705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 619195705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 619195705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 287483720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 906679425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 620366425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 288027269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 908393694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 620366425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 620366425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 620366425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 288027269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 908393694 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37518500 # Total gap between requests +system.physmem.totGap 37447500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -188,8 +188,8 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 247.494057 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.812732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.290862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.108272 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 20 23.81% 23.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 19 22.62% 46.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation @@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 3 3.57% 83.33% # By system.physmem.bytesPerActivate::896-1023 6 7.14% 90.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8 9.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation -system.physmem.totQLat 3336750 # Total ticks spent queuing -system.physmem.totMemAccLat 13330500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3307750 # Total ticks spent queuing +system.physmem.totMemAccLat 13301500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6260.32 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25010.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 906.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 908.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 906.68 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 908.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.08 # Data bus utilization in percentage -system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.10 # Data bus utilization in percentage +system.physmem.busUtilRead 7.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70391.18 # Average gap between requests +system.physmem.avgGap 70257.97 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ) @@ -231,32 +231,32 @@ system.physmem_0.actBackEnergy 21178350 # En system.physmem_0.preBackEnergy 265500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 25872240 # Total energy per rank (pJ) system.physmem_0.averagePower 823.825505 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 435750 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 346000 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 30032750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20558475 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 809250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25483875 # Total energy per rank (pJ) -system.physmem_1.averagePower 811.459163 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1209750 # Time in different power states +system.physmem_1.actBackEnergy 20535390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 831750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25491090 # Total energy per rank (pJ) +system.physmem_1.averagePower 811.591993 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1333500 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29169000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29134000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1965 # Number of BP lookups -system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1556 # Number of BTB lookups -system.cpu.branchPred.BTBHits 382 # Number of BTB hits +system.cpu.branchPred.lookups 1929 # Number of BP lookups +system.cpu.branchPred.condPredicted 1187 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 360 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1557 # Number of BTB lookups +system.cpu.branchPred.BTBHits 398 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.550129 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 25.561978 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1371 # DTB read hits +system.cpu.dtb.read_hits 1369 # DTB read hits system.cpu.dtb.read_misses 11 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1382 # DTB read accesses +system.cpu.dtb.read_accesses 1380 # DTB read accesses system.cpu.dtb.write_hits 884 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 887 # DTB write accesses -system.cpu.dtb.data_hits 2255 # DTB hits +system.cpu.dtb.data_hits 2253 # DTB hits system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2269 # DTB accesses -system.cpu.itb.fetch_hits 2639 # ITB hits +system.cpu.dtb.data_accesses 2267 # DTB accesses +system.cpu.itb.fetch_hits 2651 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2656 # ITB accesses +system.cpu.itb.fetch_accesses 2668 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,40 +293,40 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75246 # number of cpu cycles simulated +system.cpu.numCycles 75104 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1115 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.757188 # CPI: cycles per instruction -system.cpu.ipc 0.085054 # IPC: instructions per cycle -system.cpu.tickCycles 12577 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62669 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.735000 # CPI: cycles per instruction +system.cpu.ipc 0.085215 # IPC: instructions per cycle +system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62587 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.998872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.919220 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.998872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025390 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025390 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.919220 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4567 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4567 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1232 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1232 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits -system.cpu.dcache.overall_hits::total 1975 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1972 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1972 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1972 # number of overall hits +system.cpu.dcache.overall_hits::total 1972 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses @@ -335,38 +335,38 @@ system.cpu.dcache.demand_misses::cpu.data 227 # n system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8109500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8109500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9137500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9137500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17247000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17247000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17247000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17247000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8311500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8311500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9136500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9136500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17448000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17448000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17448000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17448000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1334 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2199 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2199 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076462 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076462 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.103088 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.103088 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.103088 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.103088 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79504.901961 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79504.901961 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73100 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75977.973568 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75977.973568 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.103229 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.103229 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.103229 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.103229 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81485.294118 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81485.294118 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76863.436123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76863.436123 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7616500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7616500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5372000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5372000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12988500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12988500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12988500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12988500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7818500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7818500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5371500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5371500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13190000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13190000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13190000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13190000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071964 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071964 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79338.541667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79338.541667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73589.041096 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73589.041096 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76855.029586 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76855.029586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76855.029586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76855.029586 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076853 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076853 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81442.708333 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81442.708333 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73582.191781 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73582.191781 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.991805 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.811080 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.991805 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085933 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085933 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.811080 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085845 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5643 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits -system.cpu.icache.overall_hits::total 2274 # number of overall hits +system.cpu.icache.tags.tag_accesses 5667 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5667 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2286 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2286 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2286 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2286 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2286 # number of overall hits +system.cpu.icache.overall_hits::total 2286 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28165000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28165000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28165000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28165000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28165000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28165000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77164.383562 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77164.383562 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77164.383562 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77164.383562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77164.383562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77164.383562 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27931500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27931500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27931500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27931500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27931500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27931500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2651 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2651 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2651 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.137684 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.137684 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.137684 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76524.657534 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76524.657534 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76524.657534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76524.657534 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27800000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27800000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27800000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27800000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27800000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27800000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76164.383562 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76164.383562 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76164.383562 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76164.383562 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76164.383562 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76164.383562 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27566500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27566500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27566500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27566500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27566500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27566500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75524.657534 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75524.657534 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.662872 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.447652 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 176.005347 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.657524 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005371 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007131 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.824515 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -535,18 +535,18 @@ system.cpu.l2cache.demand_misses::total 533 # nu system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5261500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5261500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27241500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27241500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27241500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12732500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 39974000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27241500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12732500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 39974000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5261000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5261000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27008000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27008000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7673000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7673000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27008000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12934000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 39942000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27008000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12934000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 39942000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) @@ -571,18 +571,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72075.342466 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72075.342466 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74839.285714 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74839.285714 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.916667 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.916667 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74839.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75340.236686 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74998.123827 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74839.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75340.236686 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74998.123827 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72068.493151 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72068.493151 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74197.802198 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74197.802198 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79927.083333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79927.083333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74938.086304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74938.086304 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,18 +603,18 @@ system.cpu.l2cache.demand_mshr_misses::total 533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23601500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23601500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23601500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11042500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 34644000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23601500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11042500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 34644000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11244000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 34612000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11244000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 34612000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadCleanReq accesses @@ -627,18 +627,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62075.342466 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62075.342466 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64839.285714 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64839.285714 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67822.916667 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67822.916667 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62068.493151 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62068.493151 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64197.802198 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64197.802198 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69927.083333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69927.083333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -688,7 +688,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2833000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 5a166e70e..7f87c40d6 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:11:59 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 21:14:59 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 22074000 because target called exit() +Exiting @ tick 21900500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 96f652b92..85a8b430a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21947000 # Number of ticks simulated -final_tick 21947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21900500 # Number of ticks simulated +final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95577 # Simulator instruction rate (inst/s) -host_op_rate 95558 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329070081 # Simulator tick rate (ticks/s) -host_mem_usage 294868 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 43231 # Simulator instruction rate (inst/s) +host_op_rate 43225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148545474 # Simulator tick rate (ticks/s) +host_mem_usage 289772 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory -system.physmem.bytes_read::total 31104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory -system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 912744339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 504488085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1417232424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 912744339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 912744339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 912744339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 504488085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1417232424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 486 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory +system.physmem.bytes_read::total 30784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 171 # Number of read requests responded to by this memory +system.physmem.num_reads::total 481 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 905915390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 499714618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1405630008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 905915390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 905915390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 905915390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 499714618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1405630008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 481 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 481 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30784 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31104 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30784 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 69 # Per bank write bursts -system.physmem.perBankRdBursts::1 33 # Per bank write bursts +system.physmem.perBankRdBursts::0 68 # Per bank write bursts +system.physmem.perBankRdBursts::1 32 # Per bank write bursts system.physmem.perBankRdBursts::2 32 # Per bank write bursts system.physmem.perBankRdBursts::3 47 # Per bank write bursts -system.physmem.perBankRdBursts::4 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 41 # Per bank write bursts system.physmem.perBankRdBursts::5 20 # Per bank write bursts system.physmem.perBankRdBursts::6 1 # Per bank write bursts system.physmem.perBankRdBursts::7 3 # Per bank write bursts @@ -54,7 +54,7 @@ system.physmem.perBankRdBursts::9 1 # Pe system.physmem.perBankRdBursts::10 22 # Per bank write bursts system.physmem.perBankRdBursts::11 25 # Per bank write bursts system.physmem.perBankRdBursts::12 14 # Per bank write bursts -system.physmem.perBankRdBursts::13 120 # Per bank write bursts +system.physmem.perBankRdBursts::13 118 # Per bank write bursts system.physmem.perBankRdBursts::14 45 # Per bank write bursts system.physmem.perBankRdBursts::15 12 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21815000 # Total gap between requests +system.physmem.totGap 21763000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 486 # Read request sizes (log2) +system.physmem.readPktSize::6 481 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,99 +186,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.725130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.981029 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation -system.physmem.totQLat 4379250 # Total ticks spent queuing -system.physmem.totMemAccLat 13491750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9010.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.822785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.071445 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.417518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22 27.85% 54.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.39% 65.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 11.39% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.06% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.27% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.80% 87.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation +system.physmem.totQLat 3965000 # Total ticks spent queuing +system.physmem.totMemAccLat 12983750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8243.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27760.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1417.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26993.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1405.63 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1417.23 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1405.63 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.07 # Data bus utilization in percentage -system.physmem.busUtilRead 11.07 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.98 # Data bus utilization in percentage +system.physmem.busUtilRead 10.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 390 # Number of row buffer hits during reads +system.physmem.readRowHits 387 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44886.83 # Average gap between requests -system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 45245.32 # Average gap between requests +system.physmem.pageHitRate 80.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1630200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) -system.physmem_0.averagePower 873.750829 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states +system.physmem_0.totalEnergy 13775205 # Total energy per rank (pJ) +system.physmem_0.averagePower 870.058740 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 209750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10129185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 614250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13534410 # Total energy per rank (pJ) -system.physmem_1.averagePower 854.849834 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 953500 # Time in different power states +system.physmem_1.actBackEnergy 10183905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 566250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13545045 # Total energy per rank (pJ) +system.physmem_1.averagePower 855.521554 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 873500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14372750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14452750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2810 # Number of BP lookups -system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 478 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2116 # Number of BTB lookups -system.cpu.branchPred.BTBHits 679 # Number of BTB hits +system.cpu.branchPred.lookups 2551 # Number of BP lookups +system.cpu.branchPred.condPredicted 1518 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1991 # Number of BTB lookups +system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.088847 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 396 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 36.464088 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 383 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2105 # DTB read hits -system.cpu.dtb.read_misses 55 # DTB read misses +system.cpu.dtb.read_hits 2033 # DTB read hits +system.cpu.dtb.read_misses 43 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2160 # DTB read accesses -system.cpu.dtb.write_hits 1074 # DTB write hits -system.cpu.dtb.write_misses 30 # DTB write misses +system.cpu.dtb.read_accesses 2076 # DTB read accesses +system.cpu.dtb.write_hits 1052 # DTB write hits +system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1104 # DTB write accesses -system.cpu.dtb.data_hits 3179 # DTB hits -system.cpu.dtb.data_misses 85 # DTB misses +system.cpu.dtb.write_accesses 1080 # DTB write accesses +system.cpu.dtb.data_hits 3085 # DTB hits +system.cpu.dtb.data_misses 71 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3264 # DTB accesses -system.cpu.itb.fetch_hits 2194 # ITB hits -system.cpu.itb.fetch_misses 34 # ITB misses +system.cpu.dtb.data_accesses 3156 # DTB accesses +system.cpu.itb.fetch_hits 2086 # ITB hits +system.cpu.itb.fetch_misses 32 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2228 # ITB accesses +system.cpu.itb.fetch_accesses 2118 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,237 +292,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 43895 # number of cpu cycles simulated +system.cpu.numCycles 43802 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8597 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16278 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2810 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1075 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4298 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1038 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 740 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2194 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14179 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.148036 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.557344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8360 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14953 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2551 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1109 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4527 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 940 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 730 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2086 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 308 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.059670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.447373 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11320 79.84% 79.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 289 2.04% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 216 1.52% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 243 1.71% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 208 1.47% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 242 1.71% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.23% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1282 9.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11381 80.65% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 309 2.19% 82.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 232 1.64% 84.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 210 1.49% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 257 1.82% 87.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 204 1.45% 89.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 249 1.76% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 144 1.02% 92.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1125 7.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14179 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064016 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.370840 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8623 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2500 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2414 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 442 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14886 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 442 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8796 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1074 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 427 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2425 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14276 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 33 # Number of times rename has blocked due to LQ full +system.cpu.fetch.rateDist::total 14111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.058239 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.341377 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8350 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2903 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2283 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 178 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 199 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13658 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8499 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1362 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 551 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2297 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1005 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13185 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10794 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17927 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17918 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9916 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16517 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16508 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6224 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 5346 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 538 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 571 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2513 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1264 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12940 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12094 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10735 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6595 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 10150 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3122 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14179 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.757106 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.490778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.719297 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.444291 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10173 71.75% 71.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1278 9.01% 80.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 898 6.33% 87.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 679 4.79% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 528 3.72% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 333 2.35% 97.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 209 1.47% 99.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.39% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10252 72.65% 72.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1258 8.92% 81.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 873 6.19% 87.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 669 4.74% 92.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 489 3.47% 95.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 327 2.32% 98.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 176 1.25% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14179 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14111 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 29 20.14% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 73 50.69% 70.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 42 29.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 18 13.64% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 55.30% 68.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41 31.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7243 67.47% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2356 21.95% 89.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1131 10.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6822 67.21% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2214 21.81% 89.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1109 10.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10735 # Type of FU issued -system.cpu.iq.rate 0.244561 # Inst issue rate -system.cpu.iq.fu_busy_cnt 144 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013414 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35792 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19571 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9784 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10150 # Type of FU issued +system.cpu.iq.rate 0.231725 # Inst issue rate +system.cpu.iq.fu_busy_cnt 132 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013005 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34530 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17879 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9316 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10866 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10269 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 71 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1330 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 399 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 71 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 442 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1033 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13054 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12206 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2513 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1264 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 395 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 476 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10242 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 493 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 85 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2076 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 3269 # number of memory reference insts executed -system.cpu.iew.exec_branches 1598 # Number of branches executed -system.cpu.iew.exec_stores 1106 # Number of stores executed -system.cpu.iew.exec_rate 0.233330 # Inst execution rate -system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9794 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5300 # num instructions producing a value -system.cpu.iew.wb_consumers 7297 # num instructions consuming a value +system.cpu.iew.exec_nop 84 # number of nop insts executed +system.cpu.iew.exec_refs 3158 # number of memory reference insts executed +system.cpu.iew.exec_branches 1540 # Number of branches executed +system.cpu.iew.exec_stores 1082 # Number of stores executed +system.cpu.iew.exec_rate 0.222638 # Inst execution rate +system.cpu.iew.wb_sent 9474 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9326 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4992 # num instructions producing a value +system.cpu.iew.wb_consumers 6833 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.223123 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.726326 # average fanout of values written-back +system.cpu.iew.wb_rate 0.212913 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.730572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6664 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5821 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.405132 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 356 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13063 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.489091 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.409393 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10520 81.06% 81.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1167 8.99% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 504 3.88% 93.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 136 1.05% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 76 0.59% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10626 81.34% 81.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1163 8.90% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 487 3.73% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 202 1.55% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 127 0.97% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 82 0.63% 97.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 98 0.75% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 84 0.64% 98.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 194 1.49% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13063 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,186 +568,186 @@ system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction -system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 25490 # The number of ROB reads -system.cpu.rob.rob_writes 27321 # The number of ROB writes -system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 24728 # The number of ROB reads +system.cpu.rob.rob_writes 25475 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.888732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.888732 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145165 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145165 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13013 # number of integer regfile reads -system.cpu.int_regfile_writes 7460 # number of integer regfile writes +system.cpu.cpi 6.874137 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.874137 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145473 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145473 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12362 # number of integer regfile reads +system.cpu.int_regfile_writes 7056 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.548347 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2343 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.543353 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.516544 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.309942 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.548347 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026257 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026257 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 107.516544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026249 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026249 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5891 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5891 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1835 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1835 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2343 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2343 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2343 # number of overall hits -system.cpu.dcache.overall_hits::total 2343 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 159 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 159 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 516 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 516 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 516 # number of overall misses -system.cpu.dcache.overall_misses::total 516 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11993500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11993500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24175975 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24175975 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36169475 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36169475 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36169475 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36169475 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1994 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041748 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5747 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5747 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1770 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1770 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits +system.cpu.dcache.overall_hits::total 2276 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 153 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 153 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses +system.cpu.dcache.overall_misses::total 512 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11315000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11315000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23651475 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23651475 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34966475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34966475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34966475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34966475 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1923 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2859 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2859 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2859 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2859 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079739 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079739 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.180483 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.180483 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.180483 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.180483 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75430.817610 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75430.817610 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67719.817927 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67719.817927 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70095.881783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70095.881783 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2284 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2788 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2788 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2788 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2788 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079563 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079563 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.183644 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.183644 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.183644 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.183644 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73954.248366 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73954.248366 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65881.545961 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65881.545961 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68293.896484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68293.896484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2328 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 41 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.707317 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.428571 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 343 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 343 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 343 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 341 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 341 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8588000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8588000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5911000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5911000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14499000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14499000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14499000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14499000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050652 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050652 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 171 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8341000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8341000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5669500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5669500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14010500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14010500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051482 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.060511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.060511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85029.702970 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85029.702970 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82097.222222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82097.222222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061334 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061334 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84252.525253 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84252.525253 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.228991 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1714 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.458599 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.228991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077260 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077260 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4702 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4702 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1714 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1714 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1714 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1714 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1714 # number of overall hits -system.cpu.icache.overall_hits::total 1714 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses -system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33574500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33574500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33574500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33574500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33574500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33574500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2194 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2194 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75575.079872 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75575.079872 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83450.495050 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83450.495050 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75575.079872 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82245.664740 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77949.588477 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75575.079872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82245.664740 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77949.588477 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997925 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77201.388889 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77201.388889 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75419.354839 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75419.354839 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82676.767677 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82676.767677 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77179.833680 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77179.833680 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -880,104 +880,104 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 313 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 313 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20525000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20525000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7418500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7418500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20525000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12498500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33023500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20525000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12498500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33023500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 310 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 310 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 99 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 99 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 310 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 310 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4838500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4838500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20280000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20280000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7195000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7195000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12033500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32313500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12033500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32313500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996815 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996785 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997925 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70555.555556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70555.555556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65575.079872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65575.079872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73450.495050 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73450.495050 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997925 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65419.354839 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65419.354839 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72676.767677 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 314 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 414 # Transaction distribution +system.membus.trans_dist::ReadResp 409 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 414 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 962 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 962 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30784 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 486 # Request fanout histogram +system.membus.snoop_fanout::samples 481 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 481 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 486 # Request fanout histogram -system.membus.reqLayer0.occupancy 594500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 481 # Request fanout histogram +system.membus.reqLayer0.occupancy 586000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2585500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2558250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index e07ba072a..5b279bd35 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 011f7e597..bf628f608 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 3ff859531..7d246ed9e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 7c57b2554..2f7c0906a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20091000 # Number of ticks simulated -final_tick 20091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20075000 # Number of ticks simulated +final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125803 # Simulator instruction rate (inst/s) -host_op_rate 125723 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 976523768 # Simulator tick rate (ticks/s) -host_mem_usage 293292 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 42420 # Simulator instruction rate (inst/s) +host_op_rate 42407 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 329231154 # Simulator tick rate (ticks/s) +host_mem_usage 287436 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 710367826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 270768006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 981135832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 710367826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 710367826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 710367826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 270768006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 981135832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 710933998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 270983811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 981917808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 710933998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 710933998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 710933998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 270983811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 981917808 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20003000 # Total gap between requests +system.physmem.totGap 19987000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 7.32% 85.37% # By system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1567250 # Total ticks spent queuing -system.physmem.totMemAccLat 7342250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1568250 # Total ticks spent queuing +system.physmem.totMemAccLat 7343250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5088.47 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5091.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23838.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 981.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23841.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 981.92 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 981.14 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 981.92 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.67 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 258 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 64944.81 # Average gap between requests +system.physmem.avgGap 64892.86 # Average gap between requests system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) @@ -231,7 +231,7 @@ system.physmem_0.actBackEnergy 10605420 # En system.physmem_0.preBackEnergy 196500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 12727575 # Total energy per rank (pJ) system.physmem_0.averagePower 803.889152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 536250 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 534250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15041250 # Time in different power states @@ -241,22 +241,22 @@ system.physmem_1.preEnergy 103125 # En system.physmem_1.readEnergy 1201200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10489995 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 10488285 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13299690 # Total energy per rank (pJ) -system.physmem_1.averagePower 839.892011 # Core power per rank (mW) +system.physmem_1.totalEnergy 13297980 # Total energy per rank (pJ) +system.physmem_1.averagePower 839.916627 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14871250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14869250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 793 # Number of BP lookups -system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups -system.cpu.branchPred.BTBHits 58 # Number of BTB hits +system.cpu.branchPred.lookups 787 # Number of BP lookups +system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 164 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 560 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 10.714286 # BTB Hit Percentage system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 509 # DTB read hits +system.cpu.dtb.read_hits 506 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 516 # DTB read accesses +system.cpu.dtb.read_accesses 513 # DTB read accesses system.cpu.dtb.write_hits 307 # DTB write hits system.cpu.dtb.write_misses 6 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 313 # DTB write accesses -system.cpu.dtb.data_hits 816 # DTB hits +system.cpu.dtb.data_hits 813 # DTB hits system.cpu.dtb.data_misses 13 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 829 # DTB accesses -system.cpu.itb.fetch_hits 971 # ITB hits +system.cpu.dtb.data_accesses 826 # DTB accesses +system.cpu.itb.fetch_hits 965 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 984 # ITB accesses +system.cpu.itb.fetch_accesses 978 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,40 +293,40 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 40182 # number of cpu cycles simulated +system.cpu.numCycles 40150 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 594 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 581 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.544294 # CPI: cycles per instruction -system.cpu.ipc 0.064332 # IPC: instructions per cycle -system.cpu.tickCycles 5392 # Number of cycles that the object actually ticked -system.cpu.idleCycles 34790 # Total number of cycles that the object has spent stopped +system.cpu.cpi 15.531915 # CPI: cycles per instruction +system.cpu.ipc 0.064384 # IPC: instructions per cycle +system.cpu.tickCycles 5369 # Number of cycles that the object actually ticked +system.cpu.idleCycles 34781 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.329975 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 48.313800 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 689 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.105882 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.329975 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011799 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.313800 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011795 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011795 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1671 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1671 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 438 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 438 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 692 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 692 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 692 # number of overall hits -system.cpu.dcache.overall_hits::total 692 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 689 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 689 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 689 # number of overall hits +system.cpu.dcache.overall_hits::total 689 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses @@ -343,22 +343,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7981500 system.cpu.dcache.demand_miss_latency::total 7981500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7981500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7981500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 499 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 796 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 796 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 796 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 796 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.121514 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 793 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 793 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 793 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 793 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.122244 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.122244 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.146259 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.130653 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.131148 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.131148 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.131148 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.131148 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767 # average WriteReq miss latency @@ -399,14 +399,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6459500 system.cpu.dcache.demand_mshr_miss_latency::total 6459500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6459500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6459500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.107188 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.107188 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency @@ -417,56 +417,56 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.935175 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 748 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 117.873256 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 742 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.354260 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.327354 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.935175 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057586 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057586 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.873256 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057555 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057555 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2165 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2165 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 748 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 748 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 748 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 748 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 748 # number of overall hits -system.cpu.icache.overall_hits::total 748 # number of overall hits +system.cpu.icache.tags.tag_accesses 2153 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2153 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 742 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 742 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 742 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 742 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 742 # number of overall hits +system.cpu.icache.overall_hits::total 742 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16978500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16978500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16978500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16978500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16978500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16978500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 971 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 971 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 971 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 971 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229660 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229660 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229660 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229660 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229660 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229660 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76136.771300 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76136.771300 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76136.771300 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76136.771300 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76136.771300 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76136.771300 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16979500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16979500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16979500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16979500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16979500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16979500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 965 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 965 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.231088 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.231088 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.231088 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.231088 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.231088 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.231088 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76141.255605 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76141.255605 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76141.255605 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76141.255605 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,36 +481,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16755500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16755500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16755500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16755500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16755500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16755500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229660 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.229660 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.229660 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75136.771300 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75136.771300 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75136.771300 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75136.771300 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75136.771300 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75136.771300 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16756500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16756500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16756500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16756500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16756500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16756500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231088 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.231088 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.231088 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75141.255605 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75141.255605 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 145.853573 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 145.780629 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.051720 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.801853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003603 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 117.989893 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.790736 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003601 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004451 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004449 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id @@ -531,16 +531,16 @@ system.cpu.l2cache.overall_misses::cpu.data 85 # system.cpu.l2cache.overall_misses::total 308 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16421000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16421000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16422000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16422000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16421000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16422000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 6331000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16421000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16422000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 6331000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 223 # number of ReadCleanReq accesses(hits+misses) @@ -567,16 +567,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73636.771300 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73636.771300 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73641.255605 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73641.255605 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73870.129870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73873.376623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73870.129870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73873.376623 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,16 +599,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 85 system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14191000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14191000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14192000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14192000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14191000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14192000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19672000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14191000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19673000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14192000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19672000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19673000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -623,16 +623,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63636.771300 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63636.771300 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63641.255605 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63641.255605 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index ee80959b5..6ee889334 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12591500 # Number of ticks simulated -final_tick 12591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12363500 # Number of ticks simulated +final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74456 # Simulator instruction rate (inst/s) -host_op_rate 74426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 392441951 # Simulator tick rate (ticks/s) -host_mem_usage 293552 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 20992 # Simulator instruction rate (inst/s) +host_op_rate 20989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108692792 # Simulator tick rate (ticks/s) +host_mem_usage 288464 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 950482468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 432037486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1382519954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 950482468 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 950482468 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 950482468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 432037486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1382519954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 968010677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 440004853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1408015530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 968010677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 968010677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 968010677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 440004853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1408015530 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12495000 # Total gap between requests +system.physmem.totGap 12267000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -200,27 +200,27 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1676750 # Total ticks spent queuing -system.physmem.totMemAccLat 6776750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1685750 # Total ticks spent queuing +system.physmem.totMemAccLat 6785750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6164.52 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6197.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24914.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1382.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24947.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1408.02 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1382.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1408.02 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.80 # Data bus utilization in percentage -system.physmem.busUtilRead 10.80 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.00 # Data bus utilization in percentage +system.physmem.busUtilRead 11.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45937.50 # Average gap between requests +system.physmem.avgGap 45099.26 # Average gap between requests system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) @@ -250,36 +250,36 @@ system.physmem_1.memoryStateTime::REF 260000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1086 # Number of BP lookups -system.cpu.branchPred.condPredicted 546 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 723 # Number of BTB lookups -system.cpu.branchPred.BTBHits 206 # Number of BTB hits +system.cpu.branchPred.lookups 890 # Number of BP lookups +system.cpu.branchPred.condPredicted 443 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 195 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 616 # Number of BTB lookups +system.cpu.branchPred.BTBHits 164 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 28.492393 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 197 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 26.623377 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 186 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 688 # DTB read hits -system.cpu.dtb.read_misses 18 # DTB read misses +system.cpu.dtb.read_hits 719 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 706 # DTB read accesses -system.cpu.dtb.write_hits 353 # DTB write hits -system.cpu.dtb.write_misses 17 # DTB write misses +system.cpu.dtb.read_accesses 729 # DTB read accesses +system.cpu.dtb.write_hits 347 # DTB write hits +system.cpu.dtb.write_misses 16 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 370 # DTB write accesses -system.cpu.dtb.data_hits 1041 # DTB hits -system.cpu.dtb.data_misses 35 # DTB misses +system.cpu.dtb.write_accesses 363 # DTB write accesses +system.cpu.dtb.data_hits 1066 # DTB hits +system.cpu.dtb.data_misses 26 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1076 # DTB accesses -system.cpu.itb.fetch_hits 931 # ITB hits -system.cpu.itb.fetch_misses 26 # ITB misses +system.cpu.dtb.data_accesses 1092 # DTB accesses +system.cpu.itb.fetch_hits 802 # ITB hits +system.cpu.itb.fetch_misses 35 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 957 # ITB accesses +system.cpu.itb.fetch_accesses 837 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +293,235 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 25184 # number of cpu cycles simulated +system.cpu.numCycles 24728 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4404 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6508 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1086 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 403 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1405 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4265 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 5512 # Number of instructions fetch has processed +system.cpu.fetch.Branches 890 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 350 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1015 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 436 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1109 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1206 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 931 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 153 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.904014 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.325149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 802 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 146 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.818654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.224131 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6086 84.54% 84.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 49 0.68% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 124 1.72% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 82 1.14% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 134 1.86% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 58 0.81% 90.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 66 0.92% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 57 0.79% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 543 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5799 86.13% 86.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30 0.45% 86.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 91 1.35% 87.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 76 1.13% 89.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 118 1.75% 90.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 72 1.07% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40 0.59% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 56 0.83% 93.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 451 6.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.043123 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.258418 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5197 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 794 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 178 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5639 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 178 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5280 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 486 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 6733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.035992 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.222905 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5190 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 505 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 865 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 28 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 145 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 132 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 4839 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 145 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5257 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 942 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5401 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3881 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6086 # Number of integer rename lookups +system.cpu.rename.RunCycles 824 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 4680 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenamedOperands 3347 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5270 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2113 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 1579 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 52 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 418 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4078 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3880 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2292 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1214 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3608 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 32 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1696 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 859 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.538964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.280196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 6733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.535868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.279819 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5699 79.16% 79.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 500 6.95% 86.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 351 4.88% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 251 3.49% 94.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 194 2.69% 97.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 116 1.61% 98.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 57 0.79% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 21 0.29% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5352 79.49% 79.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 449 6.67% 86.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 318 4.72% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 240 3.56% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 185 2.75% 97.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 110 1.63% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 49 0.73% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 21 0.31% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6733 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 8.70% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 39 56.52% 65.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 24 34.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2765 71.26% 71.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 738 19.02% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 376 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2482 68.79% 68.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 757 20.98% 89.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 368 10.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3880 # Type of FU issued -system.cpu.iq.rate 0.154066 # Inst issue rate -system.cpu.iq.fu_busy_cnt 51 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15012 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6969 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3584 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3608 # Type of FU issued +system.cpu.iq.rate 0.145907 # Inst issue rate +system.cpu.iq.fu_busy_cnt 69 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019124 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14037 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 5777 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3273 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3924 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3670 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 380 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 124 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 91 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 178 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 422 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5018 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 145 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 4365 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 29 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 418 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 168 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3751 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 707 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 129 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 20 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 120 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 140 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3509 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 730 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 99 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1077 # number of memory reference insts executed -system.cpu.iew.exec_branches 639 # Number of branches executed -system.cpu.iew.exec_stores 370 # Number of stores executed -system.cpu.iew.exec_rate 0.148944 # Inst execution rate -system.cpu.iew.wb_sent 3648 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3590 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1708 # num instructions producing a value -system.cpu.iew.wb_consumers 2182 # num instructions consuming a value +system.cpu.iew.exec_nop 281 # number of nop insts executed +system.cpu.iew.exec_refs 1093 # number of memory reference insts executed +system.cpu.iew.exec_branches 570 # Number of branches executed +system.cpu.iew.exec_stores 363 # Number of stores executed +system.cpu.iew.exec_rate 0.141904 # Inst execution rate +system.cpu.iew.wb_sent 3329 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3279 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1560 # num instructions producing a value +system.cpu.iew.wb_consumers 1998 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.142551 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.782768 # average fanout of values written-back +system.cpu.iew.wb_rate 0.132603 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.780781 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2428 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1787 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 155 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6748 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.381743 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.245988 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 122 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.402374 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273029 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5894 87.34% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193 2.86% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 303 4.49% 94.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 109 1.62% 96.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.07% 97.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 56 0.83% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.49% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.30% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5545 86.61% 86.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194 3.03% 89.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 304 4.75% 94.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 116 1.81% 96.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 62 0.97% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 60 0.94% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 35 0.55% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.31% 98.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 66 1.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6402 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,101 +567,101 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 68 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 11437 # The number of ROB reads -system.cpu.rob.rob_writes 10476 # The number of ROB writes -system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17985 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 10452 # The number of ROB reads +system.cpu.rob.rob_writes 9060 # The number of ROB writes +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17995 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.550482 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.550482 # CPI: Total CPI of All Threads -system.cpu.ipc 0.094782 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.094782 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4532 # number of integer regfile reads -system.cpu.int_regfile_writes 2777 # number of integer regfile writes +system.cpu.cpi 10.359447 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.359447 # CPI: Total CPI of All Threads +system.cpu.ipc 0.096530 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.096530 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4249 # number of integer regfile reads +system.cpu.int_regfile_writes 2511 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.864197 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 731 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 45.334739 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 716 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.600000 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.423529 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.864197 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011197 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011197 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.334739 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011068 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011068 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1937 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1937 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 518 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 518 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1873 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1873 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 503 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 503 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 731 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 731 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 731 # number of overall hits -system.cpu.dcache.overall_hits::total 731 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 716 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 716 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 716 # number of overall hits +system.cpu.dcache.overall_hits::total 716 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 195 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 195 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 195 # number of overall misses -system.cpu.dcache.overall_misses::total 195 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7589500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7589500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5666500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5666500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13256000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13256000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13256000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13256000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 632 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 632 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 178 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 178 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 178 # number of overall misses +system.cpu.dcache.overall_misses::total 178 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6583000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6583000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5672000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5672000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12255000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12255000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12255000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12255000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 926 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 926 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 926 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 926 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180380 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180380 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 894 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 894 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 894 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 894 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.161667 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.161667 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.210583 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.210583 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.210583 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.210583 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66574.561404 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66574.561404 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69956.790123 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69956.790123 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67979.487179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67979.487179 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.199105 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.199105 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.199105 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.199105 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67865.979381 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67865.979381 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68848.314607 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68848.314607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68848.314607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68848.314607 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.444444 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 110 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 110 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 110 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -671,82 +670,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4809500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4810000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4810000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6660500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096519 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096519 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6661000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6661000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6661000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6661000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.101667 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.101667 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091793 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091793 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78844.262295 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78844.262295 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.095078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.095078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.095078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.095078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78852.459016 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78852.459016 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78364.705882 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78364.705882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78364.705882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78364.705882 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.507771 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 679 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 90.143737 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 552 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.631016 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 2.951872 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.507771 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044682 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044682 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 90.143737 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044015 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2049 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2049 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 679 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 679 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 679 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 679 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 679 # number of overall hits -system.cpu.icache.overall_hits::total 679 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 252 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 252 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 252 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 252 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 252 # number of overall misses -system.cpu.icache.overall_misses::total 252 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18724999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18724999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18724999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18724999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18724999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18724999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 931 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.270677 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.270677 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.270677 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.270677 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.270677 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.270677 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74305.551587 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74305.551587 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74305.551587 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74305.551587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74305.551587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74305.551587 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1791 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1791 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 552 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 552 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 552 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 552 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 552 # number of overall hits +system.cpu.icache.overall_hits::total 552 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18739499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18739499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18739499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18739499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18739499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18739499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 802 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 802 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.311721 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.311721 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.311721 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.311721 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.311721 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.311721 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74957.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74957.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74957.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74957.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74957.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74957.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -755,51 +754,51 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14173499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14173499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14173499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14173499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14173499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14173499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.200859 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.200859 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.200859 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.200859 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.200859 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.200859 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75794.112299 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75794.112299 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75794.112299 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75794.112299 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75794.112299 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75794.112299 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14179499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14179499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14179499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14179499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14179499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14179499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.233167 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.233167 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.233167 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.233167 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.233167 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.233167 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75826.197861 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75826.197861 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75826.197861 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75826.197861 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75826.197861 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75826.197861 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 120.686426 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 118.927175 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.663709 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29.022716 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000886 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.302552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.624623 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002756 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003629 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses @@ -817,16 +816,16 @@ system.cpu.l2cache.overall_misses::cpu.data 85 # system.cpu.l2cache.overall_misses::total 272 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13892000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13892000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4718000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4718000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13892000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6531500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20423500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13892000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6531500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20423500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13898000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13898000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4718500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4718500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13898000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6532000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20430000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13898000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6532000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20430000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) @@ -853,16 +852,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74288.770053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74288.770053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77344.262295 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77344.262295 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74288.770053 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75086.397059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74288.770053 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75086.397059 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74320.855615 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74320.855615 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77352.459016 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77352.459016 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75110.294118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75110.294118 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -885,16 +884,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 85 system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12022000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12022000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12022000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5681500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17703500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12022000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5681500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17703500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12028000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12028000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12028000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5682000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17710000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12028000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5682000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17710000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -909,16 +908,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64288.770053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64288.770053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67344.262295 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67344.262295 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64320.855615 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64320.855615 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67352.459016 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67352.459016 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -946,7 +945,7 @@ system.cpu.toL2Bus.snoop_fanout::total 272 # Re system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 248 # Transaction distribution @@ -968,9 +967,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 335500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1441250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1441000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini index 32421c7b3..0c42ac84b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 0d1926cd4..f0b756165 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index ebc9b7aa1..a00344038 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index d78920aa6..6e0294d29 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 408894bb9..46fd0f447 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] |