diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/se/00.hello/ref/alpha | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha')
14 files changed, 2169 insertions, 2099 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index c9524dba5..954061e30 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35022500 # Number of ticks simulated -final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 34993500 # Number of ticks simulated +final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71946 # Simulator instruction rate (inst/s) -host_op_rate 71929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 393524726 # Simulator tick rate (ticks/s) -host_mem_usage 237176 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 162128 # Simulator instruction rate (inst/s) +host_op_rate 162075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 885888965 # Simulator tick rate (ticks/s) +host_mem_usage 292456 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 974809607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 974809607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34924000 # Total gap between requests +system.physmem.totGap 34895000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,19 +196,19 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3887500 # Total ticks spent queuing -system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3849750 # Total ticks spent queuing +system.physmem.totMemAccLat 13843500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7222.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25972.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 974.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 974.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.61 # Data bus utilization in percentage -system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.62 # Data bus utilization in percentage +system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -216,31 +216,36 @@ system.physmem.readRowHits 435 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65523.45 # Average gap between requests +system.physmem.avgGap 65469.04 # Average gap between requests system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 15500 # Time in different power states -system.physmem.memoryStateTime::REF 1040000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 30393500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 140250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 210375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2082600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1677000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ) -system.physmem.averagePower::0 827.295718 # Core power per rank (mW) -system.physmem.averagePower::1 815.785757 # Core power per rank (mW) +system.physmem_0.actEnergy 257040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25985700 # Total energy per rank (pJ) +system.physmem_0.averagePower 827.438306 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1677000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 20164320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1173750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25645245 # Total energy per rank (pJ) +system.physmem_1.averagePower 815.785757 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2149750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28549750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1972 # Number of BP lookups system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect @@ -284,26 +289,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 70045 # number of cpu cycles simulated +system.cpu.numCycles 69987 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.944531 # CPI: cycles per instruction -system.cpu.ipc 0.091370 # IPC: instructions per cycle -system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped +system.cpu.cpi 10.935469 # CPI: cycles per instruction +system.cpu.ipc 0.091446 # IPC: instructions per cycle +system.cpu.tickCycles 12616 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57371 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.036694 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 104.036694 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.025400 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -328,12 +333,12 @@ system.cpu.dcache.overall_misses::cpu.inst 227 # system.cpu.dcache.overall_misses::total 227 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8670250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 16373500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 16373500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) @@ -352,12 +357,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,12 +389,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 169 system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5119000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12250000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses @@ -400,25 +405,25 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70123.287671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 176.047314 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.126032 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 176.047314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085961 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses system.cpu.icache.tags.data_accesses 5649 # Number of data accesses @@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25915750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25915750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25915750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25915750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25915750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25915750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25886500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25886500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25886500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25886500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25886500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25886500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses @@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71002.054795 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71002.054795 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70921.917808 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70921.917808 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,37 +477,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25028250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25028250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25028250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25028250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25028250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25028250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24998500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24998500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24998500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24998500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24998500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24998500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.857006 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.762820 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.857006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.762820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -520,14 +525,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 533 # system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31686750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31686750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5053000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5053000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 36739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36739750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36739750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31657000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31657000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5044000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5044000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36701000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36701000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) @@ -544,14 +549,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68819.565217 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.890411 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68857.410882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68857.410882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -568,14 +573,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25921750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25921750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30069250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30069250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25891500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30029500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -584,14 +589,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56285.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution @@ -617,7 +622,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) @@ -642,7 +647,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 533 # Request fanout histogram system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4968000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index c9776266f..7064bc28f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20537500 # Number of ticks simulated final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69014 # Simulator instruction rate (inst/s) -host_op_rate 69006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 222388397 # Simulator tick rate (ticks/s) -host_mem_usage 237256 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 92569 # Simulator instruction rate (inst/s) +host_op_rate 92553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 298254404 # Simulator tick rate (ticks/s) +host_mem_usage 293992 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 80.08 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 41913.76 # Average gap between requests system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 22000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15339250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 332640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 127875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 181500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1755000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1365000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10809765 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10569510 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 38250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 249000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13982370 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13714770 # Total energy per rank (pJ) -system.physmem.averagePower::0 881.195525 # Core power per rank (mW) -system.physmem.averagePower::1 864.330865 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 415 # Transaction distribution -system.membus.trans_dist::ReadResp 415 # Transaction distribution -system.membus.trans_dist::ReadExReq 72 # Transaction distribution -system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 487 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 487 # Request fanout histogram -system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1755000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10809765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13982370 # Total energy per rank (pJ) +system.physmem_0.averagePower 881.195525 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1365000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10541295 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 252750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13690305 # Total energy per rank (pJ) +system.physmem_1.averagePower 864.696352 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 637250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14974750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2806 # Number of BP lookups system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -605,34 +587,118 @@ system.cpu.fp_regfile_reads 8 # nu system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits +system.cpu.dcache.overall_hits::total 2314 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses +system.cpu.dcache.overall_misses::total 522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. @@ -854,117 +920,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits -system.cpu.dcache.overall_hits::total 2314 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 415 # Transaction distribution +system.membus.trans_dist::ReadResp 415 # Transaction distribution +system.membus.trans_dist::ReadExReq 72 # Transaction distribution +system.membus.trans_dist::ReadExResp 72 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 487 # Request fanout histogram +system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 95f3db4f2..aeda1c330 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138637 # Number of ticks simulated final_tick 138637 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12523 # Simulator instruction rate (inst/s) -host_op_rate 12523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 271684 # Simulator tick rate (ticks/s) -host_mem_usage 436940 # Number of bytes of host memory used -host_seconds 0.51 # Real time elapsed on the host +host_inst_rate 45640 # Simulator instruction rate (inst/s) +host_op_rate 45635 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 990010 # Simulator tick rate (ticks/s) +host_mem_usage 451208 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -237,29 +237,126 @@ system.mem_ctrls.readRowHitRate 81.03 # Ro system.mem_ctrls.writeRowHitRate 75.41 # Row buffer hit rate for writes system.mem_ctrls.avgGap 79.75 # Average gap between requests system.mem_ctrls.pageHitRate 80.50 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 211 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 4420 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 128005 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 559440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1103760 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 310800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 613200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5828160 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 8112000 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 362880 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 673920 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 75333024 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 89081424 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 13491600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1431600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 104531424 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 109661424 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 788.190677 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 826.872042 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5828160 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 362880 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 75338496 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 13486800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 104532096 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 788.195744 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 25869 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 4420 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 106214 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 8112000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 673920 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 89081424 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1431600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 109661424 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 826.872042 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1728 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 4420 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 126488 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 138637 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 138637 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -279,8 +376,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 15.410630 -system.ruby.latency_hist::gmean 5.220511 -system.ruby.latency_hist::stdev 29.550250 +system.ruby.latency_hist::gmean 5.220490 +system.ruby.latency_hist::stdev 29.556532 system.ruby.latency_hist | 7278 86.15% 86.15% | 1151 13.62% 99.78% | 3 0.04% 99.81% | 2 0.02% 99.83% | 6 0.07% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 @@ -294,8 +391,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1490 system.ruby.miss_latency_hist::mean 73.365772 -system.ruby.miss_latency_hist::gmean 69.379008 -system.ruby.miss_latency_hist::stdev 29.545012 +system.ruby.miss_latency_hist::gmean 69.377440 +system.ruby.miss_latency_hist::stdev 29.580633 system.ruby.miss_latency_hist | 320 21.48% 21.48% | 1151 77.25% 98.72% | 3 0.20% 98.93% | 2 0.13% 99.06% | 6 0.40% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1490 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits @@ -304,7 +401,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -314,6 +410,10 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 3.776229 system.ruby.network.routers0.msg_count.Control::0 1490 system.ruby.network.routers0.msg_count.Request_Control::2 1041 @@ -331,9 +431,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6392 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328 -system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 7.332278 system.ruby.network.routers1.msg_count.Control::0 2950 system.ruby.network.routers1.msg_count.Request_Control::2 1041 @@ -387,98 +484,6 @@ system.ruby.network.msg_byte.Response_Data 697032 system.ruby.network.msg_byte.Response_Control 114288 system.ruby.network.msg_byte.Writeback_Data 61776 system.ruby.network.msg_byte.Writeback_Control 6984 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 138637 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 138637 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.369057 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490 @@ -609,9 +614,9 @@ system.ruby.LD.miss_latency_hist::total 583 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 17.899422 -system.ruby.ST.latency_hist::gmean 6.261931 -system.ruby.ST.latency_hist::stdev 30.808929 +system.ruby.ST.latency_hist::mean 17.890173 +system.ruby.ST.latency_hist::gmean 6.261514 +system.ruby.ST.latency_hist::stdev 30.772511 system.ruby.ST.latency_hist | 767 88.67% 88.67% | 95 10.98% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 @@ -624,17 +629,17 @@ system.ruby.ST.hit_latency_hist::total 649 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 216 -system.ruby.ST.miss_latency_hist::mean 62.666667 -system.ruby.ST.miss_latency_hist::gmean 57.141141 -system.ruby.ST.miss_latency_hist::stdev 33.628615 +system.ruby.ST.miss_latency_hist::mean 62.629630 +system.ruby.ST.miss_latency_hist::gmean 57.125913 +system.ruby.ST.miss_latency_hist::stdev 33.544027 system.ruby.ST.miss_latency_hist | 118 54.63% 54.63% | 95 43.98% 98.61% | 1 0.46% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 216 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 11.389844 -system.ruby.IFETCH.latency_hist::gmean 4.264766 -system.ruby.IFETCH.latency_hist::stdev 26.115167 +system.ruby.IFETCH.latency_hist::mean 11.391094 +system.ruby.IFETCH.latency_hist::gmean 4.264782 +system.ruby.IFETCH.latency_hist::stdev 26.130654 system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 673 10.52% 99.80% | 1 0.02% 99.81% | 2 0.03% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -647,11 +652,21 @@ system.ruby.IFETCH.hit_latency_hist::total 5709 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 691 -system.ruby.IFETCH.miss_latency_hist::mean 80.706223 -system.ruby.IFETCH.miss_latency_hist::gmean 78.001693 -system.ruby.IFETCH.miss_latency_hist::stdev 30.507480 +system.ruby.IFETCH.miss_latency_hist::mean 80.717800 +system.ruby.IFETCH.miss_latency_hist::gmean 78.004389 +system.ruby.IFETCH.miss_latency_hist::stdev 30.603968 system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 673 97.40% 98.12% | 1 0.14% 98.26% | 2 0.29% 98.55% | 5 0.72% 99.28% | 5 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 691 +system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.Data 277 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -716,15 +731,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data 570 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 686 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 204 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 799 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% -system.ruby.Directory_Controller.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index a7cf38c09..d5c587675 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000126 # Nu sim_ticks 126195 # Number of ticks simulated final_tick 126195 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17040 # Simulator instruction rate (inst/s) -host_op_rate 17039 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 336486 # Simulator tick rate (ticks/s) -host_mem_usage 440076 # Number of bytes of host memory used -host_seconds 0.38 # Real time elapsed on the host +host_inst_rate 43805 # Simulator instruction rate (inst/s) +host_op_rate 43801 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864948 # Simulator tick rate (ticks/s) +host_mem_usage 454088 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,36 +230,133 @@ system.mem_ctrls.busUtil 4.32 # Da system.mem_ctrls.busUtilRead 4.00 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 22.42 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 799 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 76 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 79.19 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 68.47 # Row buffer hit rate for writes system.mem_ctrls.avgGap 91.66 # Average gap between requests system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 232 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 4160 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 120458 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 551880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 306600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 4992000 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 7450560 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 186624 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 64157832 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 84064968 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 18622800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1160400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 96954696 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 103087560 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 776.656541 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 825.783908 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 551880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 306600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 186624 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 64142784 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 18636000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 96952848 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 776.641738 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 31414 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 4160 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 90106 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1035720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 575400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7450560 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 84064968 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1160400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 103087560 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 825.783908 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1262 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 119428 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 126195 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 126195 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -272,8 +369,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 13.937855 -system.ruby.latency_hist::gmean 4.957822 -system.ruby.latency_hist::stdev 28.418252 +system.ruby.latency_hist::gmean 4.957827 +system.ruby.latency_hist::stdev 28.413153 system.ruby.latency_hist | 7438 88.04% 88.04% | 992 11.74% 99.79% | 2 0.02% 99.81% | 1 0.01% 99.82% | 11 0.13% 99.95% | 3 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 @@ -287,8 +384,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1421 system.ruby.miss_latency_hist::mean 68.026742 -system.ruby.miss_latency_hist::gmean 59.451623 -system.ruby.miss_latency_hist::stdev 35.838026 +system.ruby.miss_latency_hist::gmean 59.451968 +system.ruby.miss_latency_hist::stdev 35.813966 system.ruby.miss_latency_hist | 411 28.92% 28.92% | 992 69.81% 98.73% | 2 0.14% 98.87% | 1 0.07% 98.94% | 11 0.77% 99.72% | 3 0.21% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1421 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits @@ -297,7 +394,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.974286 system.ruby.network.routers0.msg_count.Request_Control::0 1421 system.ruby.network.routers0.msg_count.Response_Data::2 1182 @@ -311,9 +411,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736 -system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 8.972820 system.ruby.network.routers1.msg_count.Request_Control::0 1421 system.ruby.network.routers1.msg_count.Request_Control::1 1182 @@ -371,98 +468,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624 system.ruby.network.msg_byte.Writeback_Data 324432 system.ruby.network.msg_byte.Writeback_Control 74304 system.ruby.network.msg_byte.Unblock_Control 63576 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 126195 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 126195 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.603629 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 @@ -553,9 +558,9 @@ system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456 system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 29.355030 -system.ruby.LD.latency_hist::gmean 10.774857 -system.ruby.LD.latency_hist::stdev 36.604149 +system.ruby.LD.latency_hist::mean 29.370245 +system.ruby.LD.latency_hist::gmean 10.775321 +system.ruby.LD.latency_hist::stdev 36.738545 system.ruby.LD.latency_hist | 860 72.70% 72.70% | 320 27.05% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 @@ -568,9 +573,9 @@ system.ruby.LD.hit_latency_hist::total 658 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 525 -system.ruby.LD.miss_latency_hist::mean 62.386667 -system.ruby.LD.miss_latency_hist::gmean 53.502649 -system.ruby.LD.miss_latency_hist::stdev 32.511258 +system.ruby.LD.miss_latency_hist::mean 62.420952 +system.ruby.LD.miss_latency_hist::gmean 53.507846 +system.ruby.LD.miss_latency_hist::stdev 32.816863 system.ruby.LD.miss_latency_hist | 202 38.48% 38.48% | 320 60.95% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 525 system.ruby.ST.latency_hist::bucket_size 64 @@ -599,9 +604,9 @@ system.ruby.ST.miss_latency_hist::total 250 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 10.378594 -system.ruby.IFETCH.latency_hist::gmean 4.114908 -system.ruby.IFETCH.latency_hist::stdev 25.040800 +system.ruby.IFETCH.latency_hist::mean 10.375781 +system.ruby.IFETCH.latency_hist::gmean 4.114880 +system.ruby.IFETCH.latency_hist::stdev 24.994631 system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 564 8.81% 99.83% | 0 0.00% 99.83% | 1 0.02% 99.84% | 8 0.12% 99.97% | 1 0.02% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -614,11 +619,33 @@ system.ruby.IFETCH.hit_latency_hist::total 5754 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 646 -system.ruby.IFETCH.miss_latency_hist::mean 76.100619 -system.ruby.IFETCH.miss_latency_hist::gmean 68.669414 -system.ruby.IFETCH.miss_latency_hist::stdev 37.537546 +system.ruby.IFETCH.miss_latency_hist::mean 76.072755 +system.ruby.IFETCH.miss_latency_hist::gmean 68.664868 +system.ruby.IFETCH.miss_latency_hist::stdev 37.280241 system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 564 87.31% 98.30% | 0 0.00% 98.30% | 1 0.15% 98.45% | 8 1.24% 99.69% | 1 0.15% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 646 +system.ruby.Directory_Controller.GETX 198 0.00% 0.00% +system.ruby.Directory_Controller.GETS 984 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -696,27 +723,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 52 0.00% system.ruby.L2Cache_Controller.SS.Unblock 141 0.00% 0.00% system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 46 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.GETX 198 0.00% 0.00% -system.ruby.Directory_Controller.GETS 984 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index abe542f63..23f7e060f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000117 # Nu sim_ticks 116770 # Number of ticks simulated final_tick 116770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 333 # Simulator instruction rate (inst/s) -host_op_rate 333 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6085 # Simulator tick rate (ticks/s) -host_mem_usage 436992 # Number of bytes of host memory used -host_seconds 19.19 # Real time elapsed on the host +host_inst_rate 63656 # Simulator instruction rate (inst/s) +host_op_rate 63646 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1162909 # Simulator tick rate (ticks/s) +host_mem_usage 451252 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -236,29 +236,126 @@ system.mem_ctrls.readRowHitRate 79.80 # Ro system.mem_ctrls.writeRowHitRate 77.31 # Row buffer hit rate for writes system.mem_ctrls.avgGap 83.10 # Average gap between requests system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 105625 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 514080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 937440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 285600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 520800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5041920 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 6764160 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 269568 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 725760 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 60929352 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 72381564 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 12117000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 2071200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 86277360 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 90520764 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 789.557896 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 828.390947 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 285600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5041920 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 269568 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 60923196 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 12117000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 86271204 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 789.566591 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 22175 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 85821 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 937440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 520800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 725760 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 72391140 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2062800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 90521940 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 828.401709 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2878 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 102769 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 116770 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 116770 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -271,8 +368,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 12.822206 -system.ruby.latency_hist::gmean 3.506831 -system.ruby.latency_hist::stdev 27.804874 +system.ruby.latency_hist::gmean 3.506830 +system.ruby.latency_hist::stdev 27.805292 system.ruby.latency_hist | 7433 87.99% 87.99% | 995 11.78% 99.76% | 6 0.07% 99.83% | 2 0.02% 99.86% | 8 0.09% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 4 @@ -287,8 +384,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1176 system.ruby.miss_latency_hist::mean 75.774660 -system.ruby.miss_latency_hist::gmean 72.686076 -system.ruby.miss_latency_hist::stdev 29.372665 +system.ruby.miss_latency_hist::gmean 72.686009 +system.ruby.miss_latency_hist::stdev 29.375504 system.ruby.miss_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1176 system.ruby.Directory.incomplete_times 1175 @@ -298,7 +395,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 189 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.578702 system.ruby.network.routers0.msg_count.Request_Control::1 1383 system.ruby.network.routers0.msg_count.Response_Data::4 1176 @@ -312,9 +412,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 320 -system.ruby.l2_cntrl0.L2cache.demand_hits 189 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.210200 system.ruby.network.routers1.msg_count.Request_Control::1 1383 system.ruby.network.routers1.msg_count.Request_Control::2 1194 @@ -372,98 +469,6 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 341712 system.ruby.network.msg_byte.Writeback_Control 23184 system.ruby.network.msg_byte.Persistent_Control 960 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 116770 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 116770 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.338700 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1176 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 207 @@ -585,8 +590,8 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 system.ruby.IFETCH.latency_hist::mean 9.334062 -system.ruby.IFETCH.latency_hist::gmean 2.862492 -system.ruby.IFETCH.latency_hist::stdev 24.015420 +system.ruby.IFETCH.latency_hist::gmean 2.862491 +system.ruby.IFETCH.latency_hist::stdev 24.016058 system.ruby.IFETCH.latency_hist | 5815 90.86% 90.86% | 573 8.95% 99.81% | 4 0.06% 99.87% | 0 0.00% 99.87% | 7 0.11% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 4 @@ -601,8 +606,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 585 system.ruby.IFETCH.miss_latency_hist::mean 79.849573 -system.ruby.IFETCH.miss_latency_hist::gmean 77.699187 -system.ruby.IFETCH.miss_latency_hist::stdev 27.986383 +system.ruby.IFETCH.miss_latency_hist::gmean 77.699044 +system.ruby.IFETCH.miss_latency_hist::stdev 27.992378 system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 585 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 @@ -624,8 +629,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1176 system.ruby.Directory.miss_mach_latency_hist::mean 75.774660 -system.ruby.Directory.miss_mach_latency_hist::gmean 72.686076 -system.ruby.Directory.miss_mach_latency_hist::stdev 29.372665 +system.ruby.Directory.miss_mach_latency_hist::gmean 72.686009 +system.ruby.Directory.miss_mach_latency_hist::stdev 29.375504 system.ruby.Directory.miss_mach_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1176 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -719,10 +724,37 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 585 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 79.849573 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699187 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.986383 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699044 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.992378 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 585 +system.ruby.Directory_Controller.GETX 209 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 219 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 903 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1176 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 228 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 1008 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 18 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 219 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 903 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 5 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 228 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 9 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 9 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -796,32 +828,5 @@ system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 1122 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETX 1 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 9 0.00% 0.00% -system.ruby.Directory_Controller.GETX 209 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 219 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 903 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1176 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 228 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 1008 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 18 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 219 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 903 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 5 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 228 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 72fcefa3c..4d5f2d93a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000096 # Nu sim_ticks 96381 # Number of ticks simulated final_tick 96381 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32379 # Simulator instruction rate (inst/s) -host_op_rate 32376 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 488288 # Simulator tick rate (ticks/s) -host_mem_usage 436896 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 66831 # Simulator instruction rate (inst/s) +host_op_rate 66821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1007748 # Simulator tick rate (ticks/s) +host_mem_usage 449612 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,12 +186,12 @@ system.mem_ctrls.wrQLenPdf::62 0 # Wh system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 194 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 352.659794 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 218.108055 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 333.620332 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 54 27.84% 27.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 26.29% 54.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 19 9.79% 63.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 16 8.25% 72.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 217.534506 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 333.874690 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 55 28.35% 28.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 50 25.77% 54.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 18 9.28% 63.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17 8.76% 72.16% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 12 6.19% 78.35% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 7 3.61% 81.96% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 7 3.61% 85.57% # Bytes accessed per row activation @@ -231,138 +231,42 @@ system.mem_ctrls.busUtil 5.65 # Da system.mem_ctrls.busUtilRead 5.20 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.45 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.25 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 21.24 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 82 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 80.56 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 70.69 # Row buffer hit rate for writes system.mem_ctrls.avgGap 69.83 # Average gap between requests system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 90575 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 476280 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 975240 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 264600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 541800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5104320 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 7063680 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 238464 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 54836964 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 61829496 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 8112600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1978800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 75135948 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 79155288 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 801.946249 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 844.845750 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 10.408736 -system.ruby.latency_hist::gmean 3.320045 -system.ruby.latency_hist::stdev 22.997500 -system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 2 -system.ruby.hit_latency_hist::max_bucket 19 -system.ruby.hit_latency_hist::samples 7289 -system.ruby.hit_latency_hist::mean 2.306352 -system.ruby.hit_latency_hist::gmean 2.107025 -system.ruby.hit_latency_hist::stdev 1.810102 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 7289 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1159 -system.ruby.miss_latency_hist::mean 61.364970 -system.ruby.miss_latency_hist::gmean 57.951867 -system.ruby.miss_latency_hist::stdev 28.728264 -system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1159 -system.ruby.Directory.incomplete_times 1158 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54887580 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 8068200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 75142164 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 802.012594 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 14237 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 77447 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7063680 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 61908840 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1909200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 79165032 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 844.949750 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2762 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 87824 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 4.652888 -system.ruby.network.routers0.msg_count.Request_Control::2 1159 -system.ruby.network.routers0.msg_count.Response_Data::4 1159 -system.ruby.network.routers0.msg_count.Writeback_Data::5 220 -system.ruby.network.routers0.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers0.msg_count.Writeback_Control::5 923 -system.ruby.network.routers0.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers0.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers0.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 4.652888 -system.ruby.network.routers1.msg_count.Request_Control::2 1159 -system.ruby.network.routers1.msg_count.Response_Data::4 1159 -system.ruby.network.routers1.msg_count.Writeback_Data::5 220 -system.ruby.network.routers1.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers1.msg_count.Writeback_Control::5 923 -system.ruby.network.routers1.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers1.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers1.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers2.percent_links_utilized 4.652888 -system.ruby.network.routers2.msg_count.Request_Control::2 1159 -system.ruby.network.routers2.msg_count.Response_Data::4 1159 -system.ruby.network.routers2.msg_count.Writeback_Data::5 220 -system.ruby.network.routers2.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers2.msg_count.Writeback_Control::5 923 -system.ruby.network.routers2.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers2.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers2.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.msg_count.Request_Control 3477 -system.ruby.network.msg_count.Response_Data 3477 -system.ruby.network.msg_count.Writeback_Data 660 -system.ruby.network.msg_count.Writeback_Control 9627 -system.ruby.network.msg_count.Unblock_Control 3477 -system.ruby.network.msg_byte.Request_Control 27816 -system.ruby.network.msg_byte.Response_Data 250344 -system.ruby.network.msg_byte.Writeback_Data 47520 -system.ruby.network.msg_byte.Writeback_Control 77016 -system.ruby.network.msg_byte.Unblock_Control 27816 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -454,6 +358,107 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 8449 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8449 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 8448 +system.ruby.latency_hist::mean 10.408736 +system.ruby.latency_hist::gmean 3.320047 +system.ruby.latency_hist::stdev 22.995606 +system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 8448 +system.ruby.hit_latency_hist::bucket_size 2 +system.ruby.hit_latency_hist::max_bucket 19 +system.ruby.hit_latency_hist::samples 7289 +system.ruby.hit_latency_hist::mean 2.306352 +system.ruby.hit_latency_hist::gmean 2.107025 +system.ruby.hit_latency_hist::stdev 1.810102 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 7289 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1159 +system.ruby.miss_latency_hist::mean 61.364970 +system.ruby.miss_latency_hist::gmean 57.952099 +system.ruby.miss_latency_hist::stdev 28.717200 +system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1159 +system.ruby.Directory.incomplete_times 1158 +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 4.652888 +system.ruby.network.routers0.msg_count.Request_Control::2 1159 +system.ruby.network.routers0.msg_count.Response_Data::4 1159 +system.ruby.network.routers0.msg_count.Writeback_Data::5 220 +system.ruby.network.routers0.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers0.msg_count.Writeback_Control::5 923 +system.ruby.network.routers0.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers0.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers0.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.routers1.percent_links_utilized 4.652888 +system.ruby.network.routers1.msg_count.Request_Control::2 1159 +system.ruby.network.routers1.msg_count.Response_Data::4 1159 +system.ruby.network.routers1.msg_count.Writeback_Data::5 220 +system.ruby.network.routers1.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers1.msg_count.Writeback_Control::5 923 +system.ruby.network.routers1.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers1.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers1.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.routers2.percent_links_utilized 4.652888 +system.ruby.network.routers2.msg_count.Request_Control::2 1159 +system.ruby.network.routers2.msg_count.Response_Data::4 1159 +system.ruby.network.routers2.msg_count.Writeback_Data::5 220 +system.ruby.network.routers2.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers2.msg_count.Writeback_Control::5 923 +system.ruby.network.routers2.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers2.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers2.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.msg_count.Request_Control 3477 +system.ruby.network.msg_count.Response_Data 3477 +system.ruby.network.msg_count.Writeback_Data 660 +system.ruby.network.msg_count.Writeback_Control 9627 +system.ruby.network.msg_count.Unblock_Control 3477 +system.ruby.network.msg_byte.Request_Control 27816 +system.ruby.network.msg_byte.Response_Data 250344 +system.ruby.network.msg_byte.Writeback_Data 47520 +system.ruby.network.msg_byte.Writeback_Control 77016 +system.ruby.network.msg_byte.Unblock_Control 27816 system.ruby.network.routers0.throttle0.link_utilization 6.004295 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143 @@ -554,9 +559,9 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 system.ruby.IFETCH.latency_hist::mean 7.937812 -system.ruby.IFETCH.latency_hist::gmean 2.788276 -system.ruby.IFETCH.latency_hist::stdev 21.096217 -system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 1 0.02% 99.86% | 4 0.06% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::gmean 2.788278 +system.ruby.IFETCH.latency_hist::stdev 21.093490 +system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 2 system.ruby.IFETCH.hit_latency_hist::max_bucket 19 @@ -570,9 +575,9 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 581 system.ruby.IFETCH.miss_latency_hist::mean 66.177281 -system.ruby.IFETCH.miss_latency_hist::gmean 63.049831 -system.ruby.IFETCH.miss_latency_hist::stdev 34.055805 -system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::gmean 63.050334 +system.ruby.IFETCH.miss_latency_hist::stdev 34.037169 +system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 581 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 @@ -592,9 +597,9 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1159 system.ruby.Directory.miss_mach_latency_hist::mean 61.364970 -system.ruby.Directory.miss_mach_latency_hist::gmean 57.951867 -system.ruby.Directory.miss_mach_latency_hist::stdev 28.728264 -system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::gmean 57.952099 +system.ruby.Directory.miss_mach_latency_hist::stdev 28.717200 +system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1159 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -684,10 +689,28 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 581 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.177281 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.049831 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.055805 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.050334 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.037169 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581 +system.ruby.Directory_Controller.GETX 185 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% +system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1191 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6411 0.00% 0.00% system.ruby.L1Cache_Controller.Store 892 0.00% 0.00% @@ -729,23 +752,5 @@ system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1143 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00% -system.ruby.Directory_Controller.GETX 185 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% -system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 01d67d280..e18c35fff 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000124 # Nu sim_ticks 123564 # Number of ticks simulated final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 34581 # Simulator instruction rate (inst/s) -host_op_rate 34578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 668563 # Simulator tick rate (ticks/s) -host_mem_usage 436724 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 69668 # Simulator instruction rate (inst/s) +host_op_rate 69633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1346306 # Simulator tick rate (ticks/s) +host_mem_usage 450680 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate 75.06 # Ro system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes system.mem_ctrls.avgGap 35.73 # Average gap between requests system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11701 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3900 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 101465 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 771120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1081080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 428400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 600600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 4879680 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 5466240 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 4281984 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 4323456 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 69482088 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 69027912 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 9282000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 9680400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 96753672 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 97808088 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 826.587089 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 835.595188 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 3456 # delay histogram for all message -system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 3456 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 13.626420 -system.ruby.latency_hist::gmean 5.329740 -system.ruby.latency_hist::stdev 25.242996 -system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6718 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6718 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1730 -system.ruby.miss_latency_hist::mean 54.891329 -system.ruby.miss_latency_hist::gmean 49.648144 -system.ruby.miss_latency_hist::stdev 31.153546 -system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1730 -system.ruby.Directory.incomplete_times 1729 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 771120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 428400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4879680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4281984 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 69480720 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 9282000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 96752304 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 826.589526 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 15125 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 98100 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1081080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 600600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 5466240 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 4323456 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 69027912 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 9680400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 97808088 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 835.595188 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 15368 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 97798 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.992328 -system.ruby.network.routers0.msg_count.Control::2 1730 -system.ruby.network.routers0.msg_count.Data::2 1726 -system.ruby.network.routers0.msg_count.Response_Data::4 1730 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers0.msg_bytes.Control::2 13840 -system.ruby.network.routers0.msg_bytes.Data::2 124272 -system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers1.percent_links_utilized 6.992328 -system.ruby.network.routers1.msg_count.Control::2 1730 -system.ruby.network.routers1.msg_count.Data::2 1726 -system.ruby.network.routers1.msg_count.Response_Data::4 1730 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers1.msg_bytes.Control::2 13840 -system.ruby.network.routers1.msg_bytes.Data::2 124272 -system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.percent_links_utilized 6.992328 -system.ruby.network.routers2.msg_count.Control::2 1730 -system.ruby.network.routers2.msg_count.Data::2 1726 -system.ruby.network.routers2.msg_count.Response_Data::4 1730 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers2.msg_bytes.Control::2 13840 -system.ruby.network.routers2.msg_bytes.Data::2 124272 -system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.msg_count.Control 5190 -system.ruby.network.msg_count.Data 5178 -system.ruby.network.msg_count.Response_Data 5190 -system.ruby.network.msg_count.Writeback_Control 5178 -system.ruby.network.msg_byte.Control 41520 -system.ruby.network.msg_byte.Data 372816 -system.ruby.network.msg_byte.Response_Data 373680 -system.ruby.network.msg_byte.Writeback_Control 41424 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 3456 # delay histogram for all message +system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 3456 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 8449 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8449 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 8448 +system.ruby.latency_hist::mean 13.626420 +system.ruby.latency_hist::gmean 5.329740 +system.ruby.latency_hist::stdev 25.242996 +system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 8448 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 6718 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 6718 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1730 +system.ruby.miss_latency_hist::mean 54.891329 +system.ruby.miss_latency_hist::gmean 49.648144 +system.ruby.miss_latency_hist::stdev 31.153546 +system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1730 +system.ruby.Directory.incomplete_times 1729 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.992328 +system.ruby.network.routers0.msg_count.Control::2 1730 +system.ruby.network.routers0.msg_count.Data::2 1726 +system.ruby.network.routers0.msg_count.Response_Data::4 1730 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers0.msg_bytes.Control::2 13840 +system.ruby.network.routers0.msg_bytes.Data::2 124272 +system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.routers1.percent_links_utilized 6.992328 +system.ruby.network.routers1.msg_count.Control::2 1730 +system.ruby.network.routers1.msg_count.Data::2 1726 +system.ruby.network.routers1.msg_count.Response_Data::4 1730 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers1.msg_bytes.Control::2 13840 +system.ruby.network.routers1.msg_bytes.Data::2 124272 +system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.routers2.percent_links_utilized 6.992328 +system.ruby.network.routers2.msg_count.Control::2 1730 +system.ruby.network.routers2.msg_count.Data::2 1726 +system.ruby.network.routers2.msg_count.Response_Data::4 1730 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers2.msg_bytes.Control::2 13840 +system.ruby.network.routers2.msg_bytes.Data::2 124272 +system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.msg_count.Control 5190 +system.ruby.network.msg_count.Data 5178 +system.ruby.network.msg_count.Response_Data 5190 +system.ruby.network.msg_count.Writeback_Control 5178 +system.ruby.network.msg_byte.Control 41520 +system.ruby.network.msg_byte.Data 372816 +system.ruby.network.msg_byte.Response_Data 373680 +system.ruby.network.msg_byte.Writeback_Control 41424 system.ruby.network.routers0.throttle0.link_utilization 6.998802 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 @@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 +system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 0513960dd..8eeabeb60 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18733500 # Number of ticks simulated final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41421 # Simulator instruction rate (inst/s) -host_op_rate 41407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 299977624 # Simulator tick rate (ticks/s) -host_mem_usage 235900 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 81438 # Simulator instruction rate (inst/s) +host_op_rate 81405 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 589715743 # Simulator tick rate (ticks/s) +host_mem_usage 292180 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # By system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation -system.physmem.totQLat 1958750 # Total ticks spent queuing -system.physmem.totMemAccLat 7733750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1952250 # Total ticks spent queuing +system.physmem.totMemAccLat 7727250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6359.58 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6338.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25109.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25088.47 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 83.44 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 60556.82 # Average gap between requests system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 15500 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15310750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 83160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 219240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 45375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 119625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 795600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1294800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10790100 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10507095 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 282750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 12765855 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13440630 # Total energy per rank (pJ) -system.physmem.averagePower::0 806.306964 # Core power per rank (mW) -system.physmem.averagePower::1 848.926575 # Core power per rank (mW) +system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12765855 # Total energy per rank (pJ) +system.physmem_0.averagePower 806.306964 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 894750 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1294800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10507095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 282750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13440630 # Total energy per rank (pJ) +system.physmem_1.averagePower 848.926575 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 429000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14897250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 793 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect @@ -296,14 +301,14 @@ system.cpu.ipc 0.068994 # IP system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.468521 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.478730 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 48.468521 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.011833 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011833 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 48.478730 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.011836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id @@ -326,14 +331,14 @@ system.cpu.dcache.demand_misses::cpu.inst 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4636500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4636500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3517500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3517500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 8154000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8154000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 8154000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8154000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4644500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3502000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 8146500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 8146500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses) @@ -350,14 +355,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76008.196721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76008.196721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81802.325581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81802.325581 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78403.846154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78403.846154 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76139.344262 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81441.860465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,14 +387,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2086500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6389000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4310500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2079250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses @@ -398,24 +403,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74181.034483 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74181.034483 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74318.965517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77009.259259 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.426247 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 118.465909 # Cycle average of tags in use system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.426247 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057825 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057825 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 118.465909 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057845 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id @@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst 223 # n system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15431500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15431500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15431500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15431500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15431500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15423500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15423500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15423500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15423500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15423500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15423500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses @@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69199.551570 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69199.551570 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69199.551570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69199.551570 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69163.677130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69163.677130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69163.677130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69163.677130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,34 +477,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14892500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14892500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14884500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14884500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14884500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14884500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14884500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14884500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66782.511211 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66782.511211 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66746.636771 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66746.636771 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 146.486275 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 146.534478 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.486275 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.534478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id @@ -516,12 +521,12 @@ system.cpu.l2cache.overall_misses::cpu.inst 308 # system.cpu.l2cache.overall_misses::total 308 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18913000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2059500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2059500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20972500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20972500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2052250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20965250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20965250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20965250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20965250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses) @@ -540,12 +545,12 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76277.777778 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76277.777778 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68092.532468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68092.532468 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76009.259259 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,12 +569,12 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15398500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1725500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1725500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17124000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17124000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1718250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17116750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17116750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -580,12 +585,12 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63907.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63907.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63638.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution @@ -613,7 +618,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 154000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 137000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 136750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution @@ -636,7 +641,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 308 # Request fanout histogram system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2868500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2868750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 15.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index dd62dc740..49b58755c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11765500 # Number of ticks simulated final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35174 # Simulator instruction rate (inst/s) -host_op_rate 35164 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173275234 # Simulator tick rate (ticks/s) -host_mem_usage 235920 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 73154 # Simulator instruction rate (inst/s) +host_op_rate 73124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 360297045 # Simulator tick rate (ticks/s) +host_mem_usage 293708 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 81.99 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 42926.47 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 22000 # Time in different power states -system.physmem.memoryStateTime::REF 260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 7778000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 68040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 158760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 37125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 86625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 631800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 850200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5478840 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5222340 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 246750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 6746115 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 7073235 # Total energy per rank (pJ) -system.physmem.averagePower::0 838.417275 # Core power per rank (mW) -system.physmem.averagePower::1 879.072239 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 248 # Transaction distribution -system.membus.trans_dist::ReadResp 248 # Transaction distribution -system.membus.trans_dist::ReadExReq 24 # Transaction distribution -system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 272 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 631800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 6746115 # Total energy per rank (pJ) +system.physmem_0.averagePower 838.417275 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206000 # Time in different power states +system.physmem_0.memoryStateTime::REF 260000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7778000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 158760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 86625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 850200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5222340 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 7073235 # Total energy per rank (pJ) +system.physmem_1.averagePower 879.072239 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 397500 # Time in different power states +system.physmem_1.memoryStateTime::REF 260000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7402500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1090 # Number of BP lookups system.cpu.branchPred.condPredicted 548 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 231 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 27.520436 # BTB Hit Percentage system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -603,34 +585,118 @@ system.cpu.int_regfile_writes 2774 # nu system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits +system.cpu.dcache.overall_hits::total 729 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses +system.cpu.dcache.overall_misses::total 198 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 92.065177 # Cycle average of tags in use system.cpu.icache.tags.total_refs 685 # Total number of references to valid blocks. @@ -846,117 +912,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits -system.cpu.dcache.overall_hits::total 729 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses -system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.membus.trans_dist::ReadResp 248 # Transaction distribution +system.membus.trans_dist::ReadExReq 24 # Transaction distribution +system.membus.trans_dist::ReadExResp 24 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 272 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 272 # Request fanout histogram +system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index d47845159..84bb9ed03 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu sim_ticks 52301 # Number of ticks simulated final_tick 52301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 11256 # Simulator instruction rate (inst/s) -host_op_rate 11255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 228406 # Simulator tick rate (ticks/s) -host_mem_usage 435628 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 42059 # Simulator instruction rate (inst/s) +host_op_rate 42050 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 853239 # Simulator tick rate (ticks/s) +host_mem_usage 450140 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 79.91 # Ro system.mem_ctrls.writeRowHitRate 30.43 # Row buffer hit rate for writes system.mem_ctrls.avgGap 80.33 # Average gap between requests system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 20 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45410 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 393120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 218400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1971840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2907840 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 31347036 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 31310100 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 688200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 720600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 37328916 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 38767308 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 794.638028 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 825.257749 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 31347036 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 688200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 37328916 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 794.638028 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1179 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 44437 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 393120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 218400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2907840 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 31309416 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 721200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 38767224 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 825.255960 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1048 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44382 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 52301 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 52301 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -299,7 +396,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2285 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 300 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -309,6 +405,10 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 3.803943 system.ruby.network.routers0.msg_count.Control::0 572 system.ruby.network.routers0.msg_count.Request_Control::2 431 @@ -326,9 +426,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 2176 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632 -system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 7.327776 system.ruby.network.routers1.msg_count.Control::0 1119 system.ruby.network.routers1.msg_count.Request_Control::2 431 @@ -382,98 +479,6 @@ system.ruby.network.msg_byte.Response_Data 263952 system.ruby.network.msg_byte.Response_Control 41760 system.ruby.network.msg_byte.Writeback_Data 23112 system.ruby.network.msg_byte.Writeback_Control 1896 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 52301 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52301 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.452095 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 @@ -647,6 +652,16 @@ system.ruby.IFETCH.miss_latency_hist::gmean 75.006009 system.ruby.IFETCH.miss_latency_hist::stdev 25.337433 system.ruby.IFETCH.miss_latency_hist | 9 3.00% 3.00% | 0 0.00% 3.00% | 276 92.00% 95.00% | 10 3.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 1 0.33% 99.00% | 1 0.33% 99.33% | 1 0.33% 99.67% | 1 0.33% 100.00% system.ruby.IFETCH.miss_latency_hist::total 300 +system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% +system.ruby.Directory_Controller.Data 103 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -711,15 +726,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data 192 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 291 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 64 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 272 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 2e81c65b5..b603fabdb 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000048 # Nu sim_ticks 48283 # Number of ticks simulated final_tick 48283 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12943 # Simulator instruction rate (inst/s) -host_op_rate 12941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 242448 # Simulator tick rate (ticks/s) -host_mem_usage 437744 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 45603 # Simulator instruction rate (inst/s) +host_op_rate 45593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 854052 # Simulator tick rate (ticks/s) +host_mem_usage 451760 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 77.66 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 88.76 # Average gap between requests system.mem_ctrls.pageHitRate 72.85 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 76 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45412 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 446040 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 247800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1884480 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2808000 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 31539240 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 30693132 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 520800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1263000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 37266360 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 38675220 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 793.272596 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 823.262378 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1884480 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 31537872 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 520800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 37264992 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 793.277248 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 968 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 44716 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 446040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 247800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2808000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 30693132 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1263000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 38675220 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 823.262378 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2007 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 43481 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 48283 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 48283 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -292,7 +389,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.874739 system.ruby.network.routers0.msg_count.Request_Control::0 544 system.ruby.network.routers0.msg_count.Response_Data::2 465 @@ -306,9 +406,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5688 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512 -system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 8.967442 system.ruby.network.routers1.msg_count.Request_Control::0 544 system.ruby.network.routers1.msg_count.Request_Control::1 465 @@ -366,98 +463,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 17064 system.ruby.network.msg_byte.Writeback_Data 120960 system.ruby.network.msg_byte.Writeback_Control 27840 system.ruby.network.msg_byte.Unblock_Control 24688 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 48283 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 48283 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.589959 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 465 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 79 @@ -614,6 +619,29 @@ system.ruby.IFETCH.miss_latency_hist::gmean 69.413198 system.ruby.IFETCH.miss_latency_hist::stdev 30.681798 system.ruby.IFETCH.miss_latency_hist | 26 9.63% 9.63% | 239 88.52% 98.15% | 2 0.74% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 270 +system.ruby.Directory_Controller.GETX 80 0.00% 0.00% +system.ruby.Directory_Controller.GETS 385 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -691,28 +719,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 12 0.00% system.ruby.L2Cache_Controller.SS.Unblock 51 0.00% 0.00% system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 16 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.GETX 80 0.00% 0.00% -system.ruby.Directory_Controller.GETS 385 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 69664e25a..166a3264e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000044 # Nu sim_ticks 43869 # Number of ticks simulated final_tick 43869 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 107 # Simulator instruction rate (inst/s) -host_op_rate 107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1826 # Simulator tick rate (ticks/s) -host_mem_usage 435688 # Number of bytes of host memory used -host_seconds 24.02 # Real time elapsed on the host +host_inst_rate 63661 # Simulator instruction rate (inst/s) +host_op_rate 63637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1082971 # Simulator tick rate (ticks/s) +host_mem_usage 449944 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 78.40 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 82.31 # Average gap between requests system.mem_ctrls.pageHitRate 73.40 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 37882 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 158760 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 355320 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 88200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 197400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1697280 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2483520 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 25360668 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 26385300 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1267800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 369000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 31115508 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 32499228 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 793.965501 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 829.273488 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1697280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 25360668 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1267800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 31115508 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 793.965501 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1987 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 35917 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 355320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 197400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2483520 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 26385300 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 369000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 32499228 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 829.273488 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 583 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 37415 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 43869 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 43869 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -294,7 +391,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.531811 system.ruby.network.routers0.msg_count.Request_Control::1 518 system.ruby.network.routers0.msg_count.Response_Data::4 448 @@ -308,9 +408,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 64 -system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.129340 system.ruby.network.routers1.msg_count.Request_Control::1 518 system.ruby.network.routers1.msg_count.Request_Control::2 454 @@ -368,98 +465,6 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 126576 system.ruby.network.msg_byte.Writeback_Control 8760 system.ruby.network.msg_byte.Persistent_Control 192 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 43869 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 43869 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.319246 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 @@ -718,6 +723,32 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.741160 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.366891 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 1 0.40% 98.79% | 3 1.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 247 +system.ruby.Directory_Controller.GETX 61 0.00% 0.00% +system.ruby.Directory_Controller.GETS 398 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 446 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -786,31 +817,5 @@ system.ruby.L2Cache_Controller.M.L1_GETS 52 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 415 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.GETX 61 0.00% 0.00% -system.ruby.Directory_Controller.GETS 398 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 446 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 391ee4c59..2c1a5d0e0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu sim_ticks 36255 # Number of ticks simulated final_tick 36255 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16369 # Simulator instruction rate (inst/s) -host_op_rate 16367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 230240 # Simulator tick rate (ticks/s) -host_mem_usage 435584 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 60442 # Simulator instruction rate (inst/s) +host_op_rate 60421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 849780 # Simulator tick rate (ticks/s) +host_mem_usage 449324 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 80.27 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 69.32 # Average gap between requests system.mem_ctrls.pageHitRate 75.06 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 30367 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 143640 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 79800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 172200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1634880 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2446080 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 20833956 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 21069936 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 567000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 360000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 25293516 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 26558304 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 805.423386 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 845.698128 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 143640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 79800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1634880 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 20833956 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 567000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 25293516 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 805.423386 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 847 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 29531 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 172200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2446080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 21069936 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 360000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 26558304 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 845.698128 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1450 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 29876 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 36255 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 36255 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -288,7 +385,9 @@ system.ruby.miss_latency_hist::stdev 26.697338 system.ruby.miss_latency_hist | 59 13.38% 13.38% | 290 65.76% 79.14% | 87 19.73% 98.87% | 1 0.23% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 1 0.23% 99.32% | 3 0.68% 100.00% system.ruby.miss_latency_hist::total 441 system.ruby.Directory.incomplete_times 440 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -298,7 +397,7 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 4.670390 system.ruby.network.routers0.msg_count.Request_Control::2 441 system.ruby.network.routers0.msg_count.Response_Data::4 441 @@ -314,9 +413,6 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.670390 system.ruby.network.routers1.msg_count.Request_Control::2 441 system.ruby.network.routers1.msg_count.Response_Data::4 441 @@ -357,97 +453,6 @@ system.ruby.network.msg_byte.Response_Data 95256 system.ruby.network.msg_byte.Writeback_Data 17496 system.ruby.network.msg_byte.Writeback_Control 28656 system.ruby.network.msg_byte.Unblock_Control 10560 -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 36255 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 36255 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.059854 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 @@ -682,6 +687,25 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.229629 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 23.299188 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 199 80.24% 80.24% | 46 18.55% 98.79% | 1 0.40% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 2 0.81% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 248 +system.ruby.Directory_Controller.GETX 51 0.00% 0.00% +system.ruby.Directory_Controller.GETS 409 0.00% 0.00% +system.ruby.Directory_Controller.PUT 425 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% system.ruby.L1Cache_Controller.Load 422 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2591 0.00% 0.00% system.ruby.L1Cache_Controller.Store 298 0.00% 0.00% @@ -723,24 +747,5 @@ system.ruby.L1Cache_Controller.MI.Store 4 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 425 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 45 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 24 0.00% 0.00% -system.ruby.Directory_Controller.GETX 51 0.00% 0.00% -system.ruby.Directory_Controller.GETS 409 0.00% 0.00% -system.ruby.Directory_Controller.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 58855671d..19e3fb417 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000048 # Nu sim_ticks 47840 # Number of ticks simulated final_tick 47840 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 31483 # Simulator instruction rate (inst/s) -host_op_rate 31473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 584131 # Simulator tick rate (ticks/s) -host_mem_usage 435420 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 35814 # Simulator instruction rate (inst/s) +host_op_rate 35808 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 664620 # Simulator tick rate (ticks/s) +host_mem_usage 449364 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate 74.87 # Ro system.mem_ctrls.writeRowHitRate 87.91 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.30 # Average gap between requests system.mem_ctrls.pageHitRate 81.48 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 140 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45290 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 249480 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 574560 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 138600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 319200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 2009280 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2758080 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 1575936 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 2208384 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 30369600 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 31087116 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1545600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 916200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 38939856 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 40914900 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 828.930858 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 870.974540 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 1248 # delay histogram for all message -system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1248 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 3295 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 3295 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 13.523376 -system.ruby.latency_hist::gmean 5.183572 -system.ruby.latency_hist::stdev 25.409311 -system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 3294 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 2668 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2668 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 626 -system.ruby.miss_latency_hist::mean 58.373802 -system.ruby.miss_latency_hist::gmean 53.319163 -system.ruby.miss_latency_hist::stdev 30.235728 -system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 626 -system.ruby.Directory.incomplete_times 625 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 249480 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 138600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2009280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1575936 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 30369600 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1545600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 38939856 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 828.930858 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 2928 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 43008 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 574560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 319200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2758080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2208384 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 31087116 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 916200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 40914900 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 870.974540 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1359 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44071 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.521739 -system.ruby.network.routers0.msg_count.Control::2 626 -system.ruby.network.routers0.msg_count.Data::2 622 -system.ruby.network.routers0.msg_count.Response_Data::4 626 -system.ruby.network.routers0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers0.msg_bytes.Control::2 5008 -system.ruby.network.routers0.msg_bytes.Data::2 44784 -system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.percent_links_utilized 6.521739 -system.ruby.network.routers1.msg_count.Control::2 626 -system.ruby.network.routers1.msg_count.Data::2 622 -system.ruby.network.routers1.msg_count.Response_Data::4 626 -system.ruby.network.routers1.msg_count.Writeback_Control::3 622 -system.ruby.network.routers1.msg_bytes.Control::2 5008 -system.ruby.network.routers1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.percent_links_utilized 6.521739 -system.ruby.network.routers2.msg_count.Control::2 626 -system.ruby.network.routers2.msg_count.Data::2 622 -system.ruby.network.routers2.msg_count.Response_Data::4 626 -system.ruby.network.routers2.msg_count.Writeback_Control::3 622 -system.ruby.network.routers2.msg_bytes.Control::2 5008 -system.ruby.network.routers2.msg_bytes.Data::2 44784 -system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.msg_count.Control 1878 -system.ruby.network.msg_count.Data 1866 -system.ruby.network.msg_count.Response_Data 1878 -system.ruby.network.msg_count.Writeback_Control 1866 -system.ruby.network.msg_byte.Control 15024 -system.ruby.network.msg_byte.Data 134352 -system.ruby.network.msg_byte.Response_Data 135216 -system.ruby.network.msg_byte.Writeback_Control 14928 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 1248 # delay histogram for all message +system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1248 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 3295 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 3295 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 3294 +system.ruby.latency_hist::mean 13.523376 +system.ruby.latency_hist::gmean 5.183572 +system.ruby.latency_hist::stdev 25.409311 +system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 3294 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 2668 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 2668 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 626 +system.ruby.miss_latency_hist::mean 58.373802 +system.ruby.miss_latency_hist::gmean 53.319163 +system.ruby.miss_latency_hist::stdev 30.235728 +system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 626 +system.ruby.Directory.incomplete_times 625 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.521739 +system.ruby.network.routers0.msg_count.Control::2 626 +system.ruby.network.routers0.msg_count.Data::2 622 +system.ruby.network.routers0.msg_count.Response_Data::4 626 +system.ruby.network.routers0.msg_count.Writeback_Control::3 622 +system.ruby.network.routers0.msg_bytes.Control::2 5008 +system.ruby.network.routers0.msg_bytes.Data::2 44784 +system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers1.percent_links_utilized 6.521739 +system.ruby.network.routers1.msg_count.Control::2 626 +system.ruby.network.routers1.msg_count.Data::2 622 +system.ruby.network.routers1.msg_count.Response_Data::4 626 +system.ruby.network.routers1.msg_count.Writeback_Control::3 622 +system.ruby.network.routers1.msg_bytes.Control::2 5008 +system.ruby.network.routers1.msg_bytes.Data::2 44784 +system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers2.percent_links_utilized 6.521739 +system.ruby.network.routers2.msg_count.Control::2 626 +system.ruby.network.routers2.msg_count.Data::2 622 +system.ruby.network.routers2.msg_count.Response_Data::4 626 +system.ruby.network.routers2.msg_count.Writeback_Control::3 622 +system.ruby.network.routers2.msg_bytes.Control::2 5008 +system.ruby.network.routers2.msg_bytes.Data::2 44784 +system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.msg_count.Control 1878 +system.ruby.network.msg_count.Data 1866 +system.ruby.network.msg_count.Response_Data 1878 +system.ruby.network.msg_count.Writeback_Control 1866 +system.ruby.network.msg_byte.Control 15024 +system.ruby.network.msg_byte.Data 134352 +system.ruby.network.msg_byte.Response_Data 135216 +system.ruby.network.msg_byte.Writeback_Control 14928 system.ruby.network.routers0.throttle0.link_utilization 6.538462 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 @@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.999958 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.587258 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297 +system.ruby.Directory_Controller.GETX 626 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement 622 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 542 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 84 0.00% 0.00% -system.ruby.Directory_Controller.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% ---------- End Simulation Statistics ---------- |