stats: updates due to recent changesets including d0934b57735a

1 files changed, 193 insertions, 193 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index e5ff065c1..3e86bd3ac 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    29934500                       # Number of ticks simulated
-final_tick                                   29934500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    29941500                       # Number of ticks simulated
+final_tick                                   29941500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 115469                       # Simulator instruction rate (inst/s)
-host_op_rate                                   135130                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              750106498                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310152                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  58660                       # Simulator instruction rate (inst/s)
+host_op_rate                                    68656                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              381226078                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304332                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        4605                       # Number of instructions simulated
 sim_ops                                          5391                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           19520                       # Nu
 system.physmem.num_reads::cpu.inst                305                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                116                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   421                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            652090397                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            248008151                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               900098548                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       652090397                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          652090397                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           652090397                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           248008151                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              900098548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            651937946                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            247950169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               899888115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       651937946                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          651937946                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           651937946                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           247950169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              899888115                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           421                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         421                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        29844000                       # Total gap between requests
+system.physmem.totGap                        29851000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895            3      4.84%     83.87% # By
 system.physmem.bytesPerActivate::896-1023            1      1.61%     85.48% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            9     14.52%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
-system.physmem.totQLat                        2214000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10107750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        2218000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10111750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2105000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5258.91                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        5268.41                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24008.91                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         900.10                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24018.41                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         899.89                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      900.10                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      899.89                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           7.03                       # Data bus utilization in percentage
@@ -220,7 +220,7 @@ system.physmem.readRowHits                        350                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.14                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        70888.36                       # Average gap between requests
+system.physmem.avgGap                        70904.99                       # Average gap between requests
 system.physmem.pageHitRate                      83.14                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     272160                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     148500                       # Energy for precharge commands per rank (pJ)
@@ -250,14 +250,14 @@ system.physmem_1.memoryStateTime::REF          780000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT        22328250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    1918                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1150                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               336                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1604                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     341                       # Number of BTB hits
+system.cpu.branchPred.lookups                    1912                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1153                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               338                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1608                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     347                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             21.259352                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     218                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             21.579602                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     219                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -377,44 +377,44 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            59869                       # number of cpu cycles simulated
+system.cpu.numCycles                            59883                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4605                       # Number of instructions committed
 system.cpu.committedOps                          5391                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1116                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                          1120                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              13.000869                       # CPI: cycles per instruction
-system.cpu.ipc                               0.076918                       # IPC: instructions per cycle
-system.cpu.tickCycles                           10574                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           49295                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              13.003909                       # CPI: cycles per instruction
+system.cpu.ipc                               0.076900                       # IPC: instructions per cycle
+system.cpu.tickCycles                           10593                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           49290                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            86.493580                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1918                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            86.506122                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1915                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.136986                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.116438                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    86.493580                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021117                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021117                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    86.506122                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021120                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021120                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4346                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4346                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1050                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1050                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              4340                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4340                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1047                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1047                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          846                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            846                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          1896                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1896                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1896                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1896                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1893                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1893                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1893                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1893                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          115                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           67                       # number of WriteReq misses
@@ -423,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data          182                       # n
 system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          182                       # number of overall misses
 system.cpu.dcache.overall_misses::total           182                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      6956000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6956000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6956500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6956500                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data      5019500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total      5019500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     11975500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     11975500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     11975500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     11975500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1165                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1165                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data     11976000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     11976000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     11976000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     11976000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1162                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1162                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2078                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2078                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2078                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2078                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098712                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098712                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2075                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2075                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2075                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2075                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098967                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098967                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.073384                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.073384                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.087584                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.087584                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.087584                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.087584                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60486.956522                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60486.956522                       # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.087711                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.087711                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.087711                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.087711                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65799.450549                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65799.450549                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65799.450549                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65799.450549                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65802.197802                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65802.197802                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -483,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          146
 system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6353000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6353000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6353500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6353500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3198000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      3198000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9551000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9551000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9551000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9551000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088412                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088412                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9551500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9551500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9551500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9551500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088640                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088640                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070260                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.070260                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070260                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.070260                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61679.611650                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61679.611650                       # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070361                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.070361                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070361                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.070361                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65417.808219                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65417.808219                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65417.808219                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65417.808219                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           161.765243                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1909                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           161.800750                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1920                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               322                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.928571                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.962733                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   161.765243                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.078987                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.078987                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   161.800750                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.079004                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.079004                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          319                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.155762                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4784                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4784                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1909                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1909                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1909                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1909                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1909                       # number of overall hits
-system.cpu.icache.overall_hits::total            1909                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              4806                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4806                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1920                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1920                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1920                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1920                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1920                       # number of overall hits
+system.cpu.icache.overall_hits::total            1920                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          322                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           322                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          322                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            322                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          322                       # number of overall misses
 system.cpu.icache.overall_misses::total           322                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23594000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23594000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23594000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23594000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23594000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23594000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2231                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2231                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2231                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2231                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2231                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2231                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.144330                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.144330                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.144330                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.144330                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.144330                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.144330                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73273.291925                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 73273.291925                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 73273.291925                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 73273.291925                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 73273.291925                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 73273.291925                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     23597500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     23597500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     23597500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     23597500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     23597500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     23597500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2242                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2242                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2242                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2242                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2242                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2242                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.143622                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.143622                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.143622                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.143622                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.143622                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.143622                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73284.161491                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73284.161491                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -573,36 +573,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          322
 system.cpu.icache.demand_mshr_misses::total          322                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          322                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          322                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23272000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     23272000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23272000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     23272000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23272000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     23272000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.144330                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.144330                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.144330                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.144330                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.144330                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.144330                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72273.291925                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72273.291925                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72273.291925                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72273.291925                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72273.291925                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72273.291925                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23275500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     23275500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     23275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23275500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     23275500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143622                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143622                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143622                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.143622                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143622                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.143622                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          195.411120                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          195.452372                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 41                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              378                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.108466                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   154.281002                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    41.130118                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004708                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   154.314702                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    41.137670                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004709                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001255                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005963                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005965                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          378                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          253                       # Occupied blocks per task id
@@ -633,16 +633,16 @@ system.cpu.l2cache.overall_misses::cpu.data          124                       #
 system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3133500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      3133500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22610500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     22610500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5960500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      5960500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22610500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9094000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     31704500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22610500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9094000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     31704500                       # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22614000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     22614000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5961000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5961000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22614000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9094500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     31708500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22614000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9094500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     31708500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          322                       # number of ReadCleanReq accesses(hits+misses)
@@ -669,16 +669,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data     0.849315
 system.cpu.l2cache.overall_miss_rate::total     0.916667                       # miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74132.786885                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74132.786885                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73586.419753                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73586.419753                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74132.786885                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73338.709677                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73903.263403                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74132.786885                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73338.709677                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73903.263403                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -707,16 +707,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data          116
 system.cpu.l2cache.overall_mshr_misses::total          421                       # number of overall MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2703500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2703500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19560500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19560500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4700500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4700500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19560500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7404000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26964500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19560500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7404000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26964500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19564000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19564000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4701000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4701000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19564000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7404500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26968500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19564000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7404500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26968500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for ReadCleanReq accesses
@@ -731,16 +731,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.794521
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.899573                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64132.786885                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64132.786885                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64390.410959                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64390.410959                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64132.786885                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63827.586207                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64048.693587                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64132.786885                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63827.586207                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64048.693587                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadResp           425                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict            2                       # Transaction distribution