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author | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
commit | 607c2772915628c2c67c1c5bfdefaa33ae66a06e (patch) | |
tree | f8f23fd4012f9a0053d65ac91792a7dc61d6baff /tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt | |
parent | 71c982ff708cc3adc7c0eccf536fea34c20cc5f0 (diff) | |
download | gem5-607c2772915628c2c67c1c5bfdefaa33ae66a06e.tar.xz |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt')
-rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 48cd9ae26..4822d2cee 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000033 # Nu sim_ticks 32719500 # Number of ticks simulated final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127457 # Simulator instruction rate (inst/s) -host_op_rate 149152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 904929733 # Simulator tick rate (ticks/s) -host_mem_usage 267332 # Number of bytes of host memory used +host_inst_rate 128948 # Simulator instruction rate (inst/s) +host_op_rate 150916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 915725978 # Simulator tick rate (ticks/s) +host_mem_usage 269308 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction @@ -438,7 +440,9 @@ system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Cl system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction -system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemWrite 922 17.10% 99.70% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction |