stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

1 files changed, 19 insertions, 4 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index 605a65a27..acde8b0d6 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.000030                       # Nu
 sim_ticks                                    29977500                       # Number of ticks simulated
 final_tick                                   29977500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 146522                       # Simulator instruction rate (inst/s)
-host_op_rate                                   171470                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              953185288                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264656                       # Number of bytes of host memory used
+host_inst_rate                                 147440                       # Simulator instruction rate (inst/s)
+host_op_rate                                   172555                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              959274014                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309288                       # Number of bytes of host memory used
 host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        4605                       # Number of instructions simulated
 sim_ops                                          5391                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             19520                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7424                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26944                       # Number of bytes read from this memory
@@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF          780000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT        22324250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups                    1949                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1165                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               351                       # Number of conditional branches incorrect
@@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits                  8                       # Nu
 system.cpu.branchPred.indirectMisses              125                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted           62                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -381,6 +387,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON        29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                            59955                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Cl
 system.cpu.op_class_0::total                     5391                       # Class of committed instruction
 system.cpu.tickCycles                           10654                       # Number of cycles that the object actually ticked
 system.cpu.idleCycles                           49301                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
 system.cpu.dcache.tags.tagsinuse            86.495507                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1916                       # Total number of references to valid blocks.
@@ -442,6 +450,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          108
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4342                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4342                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          846                       # number of WriteReq hits
@@ -544,6 +553,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 4                       # number of replacements
 system.cpu.icache.tags.tagsinuse           162.122030                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1926                       # Total number of references to valid blocks.
@@ -559,6 +569,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          213
 system.cpu.icache.tags.occ_task_id_percent::1024     0.155762                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              4821                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             4821                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst         1926                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1926                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1926                       # number of demand (read+write) hits
@@ -627,6 +638,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214
 system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          195.781809                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 43                       # Total number of references to valid blocks.
@@ -644,6 +656,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1          254
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011536                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4197                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4197                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            3                       # number of WritebackClean hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           18                       # number of ReadCleanReq hits
@@ -784,6 +797,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           426                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            4                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
@@ -814,6 +828,7 @@ system.cpu.toL2Bus.respLayer0.occupancy        484500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.6                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        222992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED     29977500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                378                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               43                       # Transaction distribution