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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout | |
parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout')
-rwxr-xr-x | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index df6ac8e30..d6f213d3f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:43:45 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 26 2013 15:15:53 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13354000 because target called exit() +Exiting @ tick 13706000 because target called exit() |