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authorAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:34 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:34 -0600
commitcfb805cc71bd1c4b72691b69faa879663e548c11 (patch)
tree4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
parent612f8f074fa1099cf70faf495d46cc647762a031 (diff)
downloadgem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout')
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout6
1 files changed, 4 insertions, 2 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index dc275e0b8..9a11b77d6 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,11 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:24:06
-gem5 started Jan 22 2014 17:30:22
+gem5 compiled Jan 23 2014 12:08:08
+gem5 started Jan 23 2014 17:05:52
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu.checker.isa: ISA system set to: 0 0x5d826c0
+ 0: system.cpu.isa: ISA system set to: 0 0x5d826c0
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 16981000 because target called exit()