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author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout | |
parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout')
-rwxr-xr-x | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 9a11b77d6..09918a5fe 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:05:52 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 11:25:19 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second - 0: system.cpu.checker.isa: ISA system set to: 0 0x5d826c0 - 0: system.cpu.isa: ISA system set to: 0 0x5d826c0 + 0: system.cpu.checker.isa: ISA system set to: 0 0x54ee6d0 + 0: system.cpu.isa: ISA system set to: 0 0x54ee6d0 info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 16981000 because target called exit() +Exiting @ tick 16786000 because target called exit() |